1 /* SPDX-License-Identifier: GPL-2.0 */
4  * Copyright (C) 2017-2025 Microchip Technology Inc.
13 #include <linux/pcs/pcs-xpcs.h>
14 #include <linux/phy.h>
18 #include <linux/platform_data/microchip-ksz.h>
72 	 * side MDIO channel for accessing integrated PHYs.
133 	u32 fiber:1;			/* port is fiber */
136 	u32 freeze:1;			/* MIB counter freeze is enabled */
207 	 * @phy_addr_map: Array mapping switch ports to their corresponding PHY
215 	 * This points to an external MDIO bus controller that is used to access
216 	 * the  PHYs integrated within the switch. Unlike an integrated MDIO
360 	 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus
366 	 * This function pointer is used to configure the MDIO bus for PHY
367 	 * access before initiating regular PHY operations. It enables either
372 	 *  - 0 on success.
373 	 *  - Negative error code on failure.
378 	 * @create_phy_addr_map: Function pointer to create a port-to-PHY
384 	 * This function pointer is responsible for mapping switch ports to PHY
388 	 * address mapping for PHY communication.
391 	 *  - 0 on success.
392 	 *  - Negative error code on failure (e.g., invalid configuration).
395 	int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
396 	int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
475 	return dev->regmap[KSZ_REGMAP_8];  in ksz_regmap_8()
480 	return dev->regmap[KSZ_REGMAP_16];  in ksz_regmap_16()
485 	return dev->regmap[KSZ_REGMAP_32];  in ksz_regmap_32()
490 	return dev->chip_id == KSZ8463_CHIP_ID;  in ksz_is_ksz8463()
499 		dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,  in ksz_read8()
512 		dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,  in ksz_read16()
525 		dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,  in ksz_read32()
539 		dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,  in ksz_read64()
553 		dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,  in ksz_write8()
565 		dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,  in ksz_write16()
577 		dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,  in ksz_write32()
590 		dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,  in ksz_rmw16()
603 		dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,  in ksz_rmw32()
627 		dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,  in ksz_rmw8()
636 	return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pread8()
642 	return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pread16()
648 	return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pread32()
654 	return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pwrite8()
660 	return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_pwrite16()
667 	return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_pwrite32()
674 	return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_prmw8()
681 	return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_prmw32()
699 	return dev->chip_id == KSZ8795_CHIP_ID ||  in ksz_is_ksz87xx()
700 	       dev->chip_id == KSZ8794_CHIP_ID ||  in ksz_is_ksz87xx()
701 	       dev->chip_id == KSZ8765_CHIP_ID;  in ksz_is_ksz87xx()
706 	return dev->chip_id == KSZ88X3_CHIP_ID;  in ksz_is_ksz88x3()
711 	return dev->chip_id == KSZ8895_CHIP_ID ||  in ksz_is_8895_family()
712 	       dev->chip_id == KSZ8864_CHIP_ID;  in ksz_is_8895_family()
729 	return dev->chip_id == KSZ9477_CHIP_ID;  in is_ksz9477()
734 	return dev->chip_id == LAN9370_CHIP_ID ||  in is_lan937x()
735 		dev->chip_id == LAN9371_CHIP_ID ||  in is_lan937x()
736 		dev->chip_id == LAN9372_CHIP_ID ||  in is_lan937x()
737 		dev->chip_id == LAN9373_CHIP_ID ||  in is_lan937x()
738 		dev->chip_id == LAN9374_CHIP_ID;  in is_lan937x()
743 	return (dev->chip_id == LAN9371_CHIP_ID ||  in is_lan937x_tx_phy()
744 		dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4;  in is_lan937x_tx_phy()
749 	return dev->info->sgmii_port - 1;  in ksz_get_sgmii_port()
754 	return dev->info->sgmii_port > 0;  in ksz_has_sgmii_port()
759 	return dev->info->sgmii_port == port + 1;  in ksz_is_sgmii_port()
821 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */
868 /* TXQ Split Control Register for per-port, per-queue configuration.
869  * Register 0xAF is TXQ Split for Q3 on Port 1.
870  * Register offset formula: 0xAF + (port * 4) + (3 - queue)
874 	(0xAF + ((port) * 4) + (3 - (queue)))
877  *   0 = Strict priority mode (highest-priority queue first)
880  *       If any queues are empty, weight is redistributed.
882  * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873
929 		.max_register = BIT(regbits) - 1,			\
959 		.max_register = BIT(regbits) - 1,			\