Lines Matching +full:0 +full:x0564
11 #define KS_PRIO_M 0x7
14 /* 0 - Operation */
15 #define REG_CHIP_ID0__1 0x0000
17 #define REG_CHIP_ID1__1 0x0001
19 #define FAMILY_ID 0x95
20 #define FAMILY_ID_94 0x94
21 #define FAMILY_ID_95 0x95
22 #define FAMILY_ID_85 0x85
23 #define FAMILY_ID_98 0x98
24 #define FAMILY_ID_88 0x88
26 #define REG_CHIP_ID2__1 0x0002
28 #define CHIP_ID_66 0x66
29 #define CHIP_ID_67 0x67
30 #define CHIP_ID_77 0x77
31 #define CHIP_ID_93 0x93
32 #define CHIP_ID_96 0x96
33 #define CHIP_ID_97 0x97
35 #define REG_CHIP_ID3__1 0x0003
37 #define SWITCH_REVISION_M 0x0F
39 #define SWITCH_RESET 0x01
41 #define REG_GLOBAL_OPTIONS 0x000F
46 #define SW_9567_RL_5_2 0xC
47 #define SW_9477_SL_5_2 0xD
49 #define SW_9896_GL_5_1 0xB
50 #define SW_9896_RL_5_1 0x8
51 #define SW_9896_SL_5_1 0x9
53 #define SW_9895_GL_4_1 0x7
54 #define SW_9895_RL_4_1 0x4
55 #define SW_9895_SL_4_1 0x5
57 #define SW_9896_RL_4_2 0x6
59 #define SW_9893_RL_2_1 0x0
60 #define SW_9893_SL_2_1 0x1
61 #define SW_9893_GL_2_1 0x3
64 #define SW_9893_RN_2_1 0xC
66 #define REG_SW_INT_STATUS__4 0x0010
67 #define REG_SW_INT_MASK__4 0x0014
75 #define REG_SW_PORT_INT_STATUS__4 0x0018
76 #define REG_SW_PORT_INT_MASK__4 0x001C
77 #define REG_SW_PHY_INT_STATUS 0x0020
78 #define REG_SW_PHY_INT_ENABLE 0x0024
81 #define REG_SW_GLOBAL_SERIAL_CTRL_0 0x0100
87 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
89 #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
91 #define SW_REFCLKO_IS_125MHZ BIT(0)
93 #define REG_SW_IBA__4 0x0104
98 #define SW_IBA_QID_M 0xF
100 #define SW_IBA_PORT_M 0x2F
102 #define SW_IBA_FRAME_TPID_M 0xFFFF
104 #define REG_SW_APB_TIMEOUT_ADDR__4 0x0108
108 #define REG_SW_IBA_SYNC__1 0x010C
110 #define REG_SW_IBA_STATUS__4 0x0110
120 #define REG_SW_IBA_STATES__4 0x0114
125 #define SW_IBA_STATE_M 0x3
126 #define SW_IBA_PACKET_SIZE_M 0x7F
128 #define SW_IBA_FMT_ID_M 0xFFFF
130 #define REG_SW_IBA_RESULT__4 0x0118
137 #define REG_SW_POWER_MANAGEMENT_CTRL 0x0201
140 #define SW_POWER_DOWN_MODE 0x3
146 #define REG_SW_OPERATION 0x0300
151 #define REG_SW_MTU__2 0x0308
152 #define REG_SW_MTU_MASK GENMASK(13, 0)
154 #define REG_SW_ISP_TPID__2 0x030A
156 #define REG_SW_HSR_TPID__2 0x030C
158 #define REG_AVB_STRATEGY__2 0x030E
161 #define SW_POLICING_CREDIT_ACCT BIT(0)
163 #define REG_SW_LUE_CTRL_0 0x0310
169 #define SW_HASH_OPTION_M 0x03
174 #define REG_SW_LUE_CTRL_1 0x0311
183 #define SW_LINK_AUTO_AGING BIT(0)
185 #define REG_SW_LUE_CTRL_2 0x0312
190 #define SW_FLUSH_OPTION_M 0x3
195 #define SW_PRIO_M 0x3
196 #define SW_PRIO_DA 0
201 #define REG_SW_LUE_CTRL_3 0x0313
202 #define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)
204 #define REG_SW_LUE_INT_STATUS 0x0314
205 #define REG_SW_LUE_INT_ENABLE 0x0315
209 #define WRITE_FAIL_INT BIT(0)
211 #define REG_SW_LUE_INDEX_0__2 0x0316
213 #define ENTRY_INDEX_M 0x0FFF
215 #define REG_SW_LUE_INDEX_1__2 0x0318
217 #define FAIL_INDEX_M 0x03FF
219 #define REG_SW_LUE_INDEX_2__2 0x031A
221 #define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320
225 #define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324
229 #define REG_SW_LUE_UNK_VID_CTRL__4 0x0328
233 #define REG_SW_MAC_CTRL_0 0x0330
238 #define SW_AGGR_BACKOFF BIT(0)
240 #define REG_SW_MAC_CTRL_1 0x0331
243 #define SW_BACK_PRESSURE_COLLISION 0
248 #define SW_PASS_SHORT_FRAME BIT(0)
250 #define REG_SW_MAC_CTRL_2 0x0332
254 #define REG_SW_MAC_CTRL_3 0x0333
256 #define REG_SW_MAC_CTRL_4 0x0334
260 #define REG_SW_MAC_CTRL_5 0x0335
264 #define REG_SW_MAC_CTRL_6 0x0336
269 #define REG_SW_MAC_802_1P_MAP_0 0x0338
270 #define REG_SW_MAC_802_1P_MAP_1 0x0339
271 #define REG_SW_MAC_802_1P_MAP_2 0x033A
272 #define REG_SW_MAC_802_1P_MAP_3 0x033B
277 #define REG_SW_MAC_ISP_CTRL 0x033C
279 #define REG_SW_MAC_TOS_CTRL 0x033E
282 #define SW_TOS_DSCP_REMAP BIT(0)
284 #define REG_SW_MAC_TOS_PRIO_0 0x0340
285 #define REG_SW_MAC_TOS_PRIO_1 0x0341
286 #define REG_SW_MAC_TOS_PRIO_2 0x0342
287 #define REG_SW_MAC_TOS_PRIO_3 0x0343
288 #define REG_SW_MAC_TOS_PRIO_4 0x0344
289 #define REG_SW_MAC_TOS_PRIO_5 0x0345
290 #define REG_SW_MAC_TOS_PRIO_6 0x0346
291 #define REG_SW_MAC_TOS_PRIO_7 0x0347
292 #define REG_SW_MAC_TOS_PRIO_8 0x0348
293 #define REG_SW_MAC_TOS_PRIO_9 0x0349
294 #define REG_SW_MAC_TOS_PRIO_10 0x034A
295 #define REG_SW_MAC_TOS_PRIO_11 0x034B
296 #define REG_SW_MAC_TOS_PRIO_12 0x034C
297 #define REG_SW_MAC_TOS_PRIO_13 0x034D
298 #define REG_SW_MAC_TOS_PRIO_14 0x034E
299 #define REG_SW_MAC_TOS_PRIO_15 0x034F
300 #define REG_SW_MAC_TOS_PRIO_16 0x0350
301 #define REG_SW_MAC_TOS_PRIO_17 0x0351
302 #define REG_SW_MAC_TOS_PRIO_18 0x0352
303 #define REG_SW_MAC_TOS_PRIO_19 0x0353
304 #define REG_SW_MAC_TOS_PRIO_20 0x0354
305 #define REG_SW_MAC_TOS_PRIO_21 0x0355
306 #define REG_SW_MAC_TOS_PRIO_22 0x0356
307 #define REG_SW_MAC_TOS_PRIO_23 0x0357
308 #define REG_SW_MAC_TOS_PRIO_24 0x0358
309 #define REG_SW_MAC_TOS_PRIO_25 0x0359
310 #define REG_SW_MAC_TOS_PRIO_26 0x035A
311 #define REG_SW_MAC_TOS_PRIO_27 0x035B
312 #define REG_SW_MAC_TOS_PRIO_28 0x035C
313 #define REG_SW_MAC_TOS_PRIO_29 0x035D
314 #define REG_SW_MAC_TOS_PRIO_30 0x035E
315 #define REG_SW_MAC_TOS_PRIO_31 0x035F
317 #define REG_SW_MRI_CTRL_0 0x0370
322 #define SW_MIRROR_RX_TX BIT(0)
324 #define REG_SW_CLASS_D_IP_CTRL__4 0x0374
328 #define REG_SW_MRI_CTRL_8 0x0378
333 #define SW_GREEN_COLOR_S 0
334 #define SW_COLOR_M 0x3
336 #define REG_SW_QM_CTRL__4 0x0390
340 #define PRIO_MAP_3_HI 0
345 #define REG_SW_EEE_QM_CTRL__2 0x03C0
347 #define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2
350 #define REG_SW_VLAN_ENTRY__4 0x0400
356 #define VLAN_MSTP_M 0x7
358 #define VLAN_FID_M 0x7F
360 #define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404
361 #define REG_SW_VLAN_ENTRY_PORTS__4 0x0408
363 #define REG_SW_VLAN_ENTRY_INDEX__2 0x040C
365 #define VLAN_INDEX_M 0x0FFF
367 #define REG_SW_VLAN_CTRL 0x040E
370 #define VLAN_ACTION 0x3
375 #define REG_SW_ALU_INDEX_0 0x0410
378 #define ALU_MAC_ADDR_HI 0xFFFF
380 #define REG_SW_ALU_INDEX_1 0x0414
384 #define REG_SW_ALU_CTRL__4 0x0418
391 #define ALU_ACTION 0x3
396 #define REG_SW_ALU_STAT_CTRL__4 0x041C
401 #define REG_SW_ALU_VAL_A 0x0420
408 #define ALU_V_MSTP_M 0x7
410 #define REG_SW_ALU_VAL_B 0x0424
416 #define REG_SW_ALU_VAL_C 0x0428
420 #define ALU_V_MAC_ADDR_HI 0xFFFF
422 #define REG_SW_ALU_VAL_D 0x042C
424 #define REG_HSR_ALU_INDEX_0 0x0440
426 #define REG_HSR_ALU_INDEX_1 0x0444
429 #define HSR_SRC_MAC_INDEX_HI 0xFFFF
431 #define REG_HSR_ALU_INDEX_2 0x0448
436 #define REG_HSR_ALU_INDEX_3 0x044C
440 #define REG_HSR_ALU_CTRL__4 0x0450
448 #define HSR_ACTION 0x3
453 #define REG_HSR_ALU_VAL_A 0x0454
460 #define REG_HSR_ALU_VAL_B 0x0458
462 #define REG_HSR_ALU_VAL_C 0x045C
465 #define HSR_V_SRC_MAC_ADDR_HI 0xFFFF
467 #define REG_HSR_ALU_VAL_D 0x0460
469 #define REG_HSR_ALU_VAL_E 0x0464
472 #define HSR_V_START_SEQ_2_S 0
474 #define REG_HSR_ALU_VAL_F 0x0468
477 #define HSR_V_EXP_SEQ_2_S 0
479 #define REG_HSR_ALU_VAL_G 0x046C
482 #define HSR_V_SEQ_CNT_2_S 0
487 #define REG_PTP_CLK_CTRL 0x0500
495 #define PTP_CLK_RESET BIT(0)
497 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
499 #define PTP_RTC_SUB_NANOSEC_M 0x0007
501 #define REG_PTP_RTC_NANOSEC 0x0504
502 #define REG_PTP_RTC_NANOSEC_H 0x0504
503 #define REG_PTP_RTC_NANOSEC_L 0x0506
505 #define REG_PTP_RTC_SEC 0x0508
506 #define REG_PTP_RTC_SEC_H 0x0508
507 #define REG_PTP_RTC_SEC_L 0x050A
509 #define REG_PTP_SUBNANOSEC_RATE 0x050C
510 #define REG_PTP_SUBNANOSEC_RATE_H 0x050C
515 #define REG_PTP_SUBNANOSEC_RATE_L 0x050E
517 #define REG_PTP_RATE_DURATION 0x0510
518 #define REG_PTP_RATE_DURATION_H 0x0510
519 #define REG_PTP_RATE_DURATION_L 0x0512
521 #define REG_PTP_MSG_CONF1 0x0514
530 #define PTP_1STEP BIT(0)
532 #define REG_PTP_MSG_CONF2 0x0516
544 #define REG_PTP_DOMAIN_VERSION 0x0518
545 #define PTP_VERSION_M 0xFF00
546 #define PTP_DOMAIN_M 0x00FF
548 #define REG_PTP_UNIT_INDEX__4 0x0520
550 #define PTP_UNIT_M 0xF
554 #define PTP_TOU_INDEX_S 0
556 #define REG_PTP_TRIG_STATUS__4 0x0524
559 #define TRIG_DONE_S 0
561 #define REG_PTP_INT_STATUS__4 0x0528
564 #define TS_INT_S 0
566 #define TRIG_UNIT_M 0x7
567 #define TS_UNIT_M 0x3
569 #define REG_PTP_CTRL_STAT__4 0x052C
578 #define TS_RESET BIT(0)
588 #define REG_TRIG_TARGET_NANOSEC 0x0530
589 #define REG_TRIG_TARGET_SEC 0x0534
591 #define REG_TRIG_CTRL__4 0x0538
595 #define TRIG_CASCADE_UPS_M 0xF
601 #define TRIG_PATTERN_M 0x7
602 #define TRIG_NEG_EDGE 0
610 #define TRIG_GPO_M 0xF
611 #define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF
613 #define REG_TRIG_CYCLE_WIDTH 0x053C
615 #define REG_TRIG_CYCLE_CNT 0x0540
617 #define TRIG_CYCLE_CNT_M 0xFFFF
619 #define TRIG_BIT_PATTERN_M 0xFFFF
621 #define REG_TRIG_ITERATE_TIME 0x0544
623 #define REG_TRIG_PULSE_WIDTH__4 0x0548
625 #define TRIG_PULSE_WIDTH_M 0x00FFFFFF
627 #define REG_TS_CTRL_STAT__4 0x0550
629 #define TS_EVENT_DETECT_M 0xF
632 #define TS_GPI_M 0xF
638 #define TS_CASCADE_UPS_M 0xF
640 #define TS_CASCADE_ENABLE BIT(0)
645 #define REG_TS_EVENT_0_NANOSEC 0x0554
646 #define REG_TS_EVENT_0_SEC 0x0558
647 #define REG_TS_EVENT_0_SUB_NANOSEC 0x055C
649 #define REG_TS_EVENT_1_NANOSEC 0x0560
650 #define REG_TS_EVENT_1_SEC 0x0564
651 #define REG_TS_EVENT_1_SUB_NANOSEC 0x0568
653 #define REG_TS_EVENT_2_NANOSEC 0x056C
654 #define REG_TS_EVENT_2_SEC 0x0570
655 #define REG_TS_EVENT_2_SUB_NANOSEC 0x0574
657 #define REG_TS_EVENT_3_NANOSEC 0x0578
658 #define REG_TS_EVENT_3_SEC 0x057C
659 #define REG_TS_EVENT_3_SUB_NANOSEC 0x0580
661 #define REG_TS_EVENT_4_NANOSEC 0x0584
662 #define REG_TS_EVENT_4_SEC 0x0588
663 #define REG_TS_EVENT_4_SUB_NANOSEC 0x058C
665 #define REG_TS_EVENT_5_NANOSEC 0x0590
666 #define REG_TS_EVENT_5_SEC 0x0594
667 #define REG_TS_EVENT_5_SUB_NANOSEC 0x0598
669 #define REG_TS_EVENT_6_NANOSEC 0x059C
670 #define REG_TS_EVENT_6_SEC 0x05A0
671 #define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4
673 #define REG_TS_EVENT_7_NANOSEC 0x05A8
674 #define REG_TS_EVENT_7_SEC 0x05AC
675 #define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0
677 #define TS_EVENT_EDGE_M 0x1
681 #define TS_EVENT_SUB_NANOSEC_M 0x7
688 #define REG_GLOBAL_RR_INDEX__1 0x0600
691 #define REG_DLR_SRC_PORT__4 0x0604
694 #define DLR_SRC_PORT_M 0x3
695 #define DLR_SRC_PORT_BOTH 0
698 #define REG_DLR_IP_ADDR__4 0x0608
700 #define REG_DLR_CTRL__1 0x0610
705 #define DLR_ASSIST_ENABLE BIT(0)
707 #define REG_DLR_STATE__1 0x0611
709 #define DLR_NODE_STATE_M 0x3
711 #define DLR_NODE_STATE_IDLE 0
714 #define DLR_RING_STATE_FAULT 0
717 #define REG_DLR_PRECEDENCE__1 0x0612
719 #define REG_DLR_BEACON_INTERVAL__4 0x0614
721 #define REG_DLR_BEACON_TIMEOUT__4 0x0618
723 #define REG_DLR_TIMEOUT_WINDOW__4 0x061C
727 #define REG_DLR_VLAN_ID__2 0x0620
731 #define REG_DLR_DEST_ADDR_0 0x0622
732 #define REG_DLR_DEST_ADDR_1 0x0623
733 #define REG_DLR_DEST_ADDR_2 0x0624
734 #define REG_DLR_DEST_ADDR_3 0x0625
735 #define REG_DLR_DEST_ADDR_4 0x0626
736 #define REG_DLR_DEST_ADDR_5 0x0627
738 #define REG_DLR_PORT_MAP__4 0x0628
740 #define REG_DLR_CLASS__1 0x062C
742 #define DLR_FRAME_QID_M 0x3
745 #define REG_HSR_PORT_MAP__4 0x0640
747 #define REG_HSR_ALU_CTRL_0__1 0x0644
751 #define HSR_AGE_CNT_DEFAULT_M 0x7
754 #define HSR_HASH_OPTION_M 0x3
755 #define HSR_HASH_DISABLE 0
760 #define REG_HSR_ALU_CTRL_1__1 0x0645
767 #define REG_HSR_ALU_CTRL_2__2 0x0646
769 #define REG_HSR_ALU_AGE_PERIOD__4 0x0648
771 #define REG_HSR_ALU_INT_STATUS__1 0x064C
772 #define REG_HSR_ALU_INT_MASK__1 0x064D
777 #define HSR_WRITE_FAIL_INT BIT(0)
779 #define REG_HSR_ALU_ENTRY_0__2 0x0650
784 #define REG_HSR_ALU_ENTRY_1__2 0x0652
788 #define REG_HSR_ALU_ENTRY_3__2 0x0654
792 /* 0 - Operation */
793 #define REG_PORT_DEFAULT_VID 0x0000
795 #define REG_PORT_CUSTOM_VID 0x0002
796 #define REG_PORT_AVB_SR_1_VID 0x0004
797 #define REG_PORT_AVB_SR_2_VID 0x0006
799 #define REG_PORT_AVB_SR_1_TYPE 0x0008
800 #define REG_PORT_AVB_SR_2_TYPE 0x000A
802 #define REG_PORT_INT_STATUS 0x001B
803 #define REG_PORT_INT_MASK 0x001F
808 #define PORT_ACL_INT BIT(0)
813 #define REG_PORT_CTRL_0 0x0020
819 #define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0)
820 #define PORT_EIGHT_QUEUE 0x3
821 #define PORT_FOUR_QUEUE 0x2
822 #define PORT_TWO_QUEUE 0x1
823 #define PORT_SINGLE_QUEUE 0x0
825 #define REG_PORT_CTRL_1 0x0021
827 #define PORT_SRP_ENABLE 0x3
829 #define REG_PORT_STATUS_0 0x0030
832 #define PORT_INTF_SPEED_NONE GENMASK(1, 0)
835 #define PORT_RX_FLOW_CTRL BIT(0)
837 #define REG_PORT_STATUS_1 0x0034
840 #define REG_PORT_PHY_CTRL 0x0100
853 #define REG_PORT_PHY_STATUS 0x0102
867 #define PORT_EXTENDED_CAPABILITY BIT(0)
869 #define REG_PORT_PHY_ID_HI 0x0104
870 #define REG_PORT_PHY_ID_LO 0x0106
872 #define KSZ9477_ID_HI 0x0022
873 #define KSZ9477_ID_LO 0x1622
875 #define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108
886 #define PORT_AUTO_NEG_SELECTOR 0x001F
887 #define PORT_AUTO_NEG_802_3 0x0001
892 #define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A
904 #define REG_PORT_PHY_1000_CTRL 0x0112
912 #define REG_PORT_PHY_1000_STATUS 0x0114
920 #define PORT_REMOTE_IDLE_CNT_M 0x0F
928 #define REG_PORT_PHY_MMD_SETUP 0x011A
930 #define PORT_MMD_OP_MODE_M 0x3
932 #define PORT_MMD_OP_INDEX 0
936 #define PORT_MMD_DEVICE_ID_M 0x1F
941 #define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
945 #define MMD_DSP_SQI_CHAN_A 0xAC
946 #define MMD_DSP_SQI_CHAN_B 0xAD
947 #define MMD_DSP_SQI_CHAN_C 0xAE
948 #define MMD_DSP_SQI_CHAN_D 0xAF
951 #define DSP_SQI_AVG_ERR 0x7FFF
957 #define MMD_EEE_ADV 0x3C
961 #define MMD_EEE_LP_ADV 0x3D
962 #define MMD_EEE_MSG_CODE 0x3F
964 #define MMD_DEVICE_ID_AFED 0x1C
966 #define REG_PORT_PHY_EXTENDED_STATUS 0x011E
973 #define REG_PORT_SGMII_ADDR__4 0x0200
975 #define PORT_SGMII_DEVICE_ID_M 0x1F
979 #define REG_PORT_SGMII_DATA__4 0x0204
982 #define MMD_DEVICE_ID_PMA 0x01
983 #define MMD_DEVICE_ID_PCS 0x03
984 #define MMD_DEVICE_ID_PHY_XS 0x04
985 #define MMD_DEVICE_ID_DTE_XS 0x05
986 #define MMD_DEVICE_ID_AN 0x07
987 #define MMD_DEVICE_ID_VENDOR_CTRL 0x1E
988 #define MMD_DEVICE_ID_VENDOR_MII 0x1F
992 #define MMD_SR_MII_CTRL 0x0000
1003 #define MMD_SR_MII_STATUS 0x0001
1004 #define MMD_SR_MII_ID_1 0x0002
1005 #define MMD_SR_MII_ID_2 0x0003
1006 #define MMD_SR_MII_AUTO_NEGOTIATION 0x0004
1009 #define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x3
1011 #define SR_MII_AUTO_NEG_NO_ERROR 0
1015 #define SR_MII_AUTO_NEG_PAUSE_M 0x3
1017 #define SR_MII_AUTO_NEG_NO_PAUSE 0
1024 #define MMD_SR_MII_REMOTE_CAPABILITY 0x0005
1025 #define MMD_SR_MII_AUTO_NEG_EXP 0x0006
1026 #define MMD_SR_MII_AUTO_NEG_EXT 0x000F
1028 #define MMD_SR_MII_DIGITAL_CTRL_1 0x8000
1030 #define MMD_SR_MII_AUTO_NEG_CTRL 0x8001
1035 #define SR_MII_PCS_MODE_M 0x3
1038 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1040 #define MMD_SR_MII_AUTO_NEG_STATUS 0x8002
1043 #define SR_MII_STAT_M 0x3
1045 #define SR_MII_STAT_10_MBPS 0
1050 #define MMD_SR_MII_PHY_CTRL 0x80A0
1052 #define SR_MII_PHY_LANE_SEL_M 0xF
1055 #define SR_MII_PHY_START_BUSY BIT(0)
1057 #define MMD_SR_MII_PHY_ADDR 0x80A1
1061 #define MMD_SR_MII_PHY_DATA 0x80A2
1065 #define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C
1066 #define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D
1068 #define REG_PORT_PHY_REMOTE_LB_LED 0x0122
1076 #define PORT_LINK_MD_PASS BIT(0)
1078 #define REG_PORT_PHY_LINK_MD 0x0124
1082 #define PORT_CABLE_DIAG_PAIR_M 0x3
1084 #define PORT_CABLE_DIAG_SELECT_M 0x3
1086 #define PORT_CABLE_DIAG_RESULT_M 0x3
1088 #define PORT_CABLE_STAT_NORMAL 0
1092 #define PORT_CABLE_FAULT_COUNTER 0x00FF
1094 #define REG_PORT_PHY_PMA_STATUS 0x0126
1097 #define PORT_100_LINK_GOOD BIT(0)
1099 #define REG_PORT_PHY_DIGITAL_STATUS 0x0128
1106 #define REG_PORT_PHY_RXER_COUNTER 0x012A
1108 #define REG_PORT_PHY_INT_ENABLE 0x0136
1109 #define REG_PORT_PHY_INT_STATUS 0x0137
1118 #define LINK_UP_INT BIT(0)
1120 #define REG_PORT_PHY_DIGITAL_DEBUG_1 0x0138
1127 #define PORT_PHY_PCS_LOOPBACK BIT(0)
1129 #define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A
1131 #define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C
1135 #define REG_PORT_PHY_PHY_CTRL 0x013E
1147 #define PORT_LINK_STATUS_FAIL BIT(0)
1151 #define PORT_GRXC_ENABLE BIT(0)
1156 #define REG_PMAVBC 0x03AC
1159 #define PMAVBC_MIN 0x580
1162 #define REG_PORT_MAC_CTRL_0 0x0400
1165 #define PORT_JUMBO_FRAME BIT(0)
1167 #define REG_PORT_MAC_CTRL_1 0x0401
1170 #define PORT_PASS_ALL BIT(0)
1172 #define REG_PORT_MAC_CTRL_2 0x0402
1177 #define REG_PORT_MAC_IN_RATE_LIMIT 0x0403
1183 #define PORT_COUNT_PREAMBLE_S 0
1187 #define PORT_IN_LIMIT_MODE_M 0x3
1189 #define PORT_IN_ALL 0
1194 #define PORT_COUNT_PREAMBLE BIT(0)
1196 #define REG_PORT_IN_RATE_0 0x0410
1197 #define REG_PORT_IN_RATE_1 0x0411
1198 #define REG_PORT_IN_RATE_2 0x0412
1199 #define REG_PORT_IN_RATE_3 0x0413
1200 #define REG_PORT_IN_RATE_4 0x0414
1201 #define REG_PORT_IN_RATE_5 0x0415
1202 #define REG_PORT_IN_RATE_6 0x0416
1203 #define REG_PORT_IN_RATE_7 0x0417
1205 #define REG_PORT_OUT_RATE_0 0x0420
1206 #define REG_PORT_OUT_RATE_1 0x0421
1207 #define REG_PORT_OUT_RATE_2 0x0422
1208 #define REG_PORT_OUT_RATE_3 0x0423
1213 #define REG_PORT_MIB_CTRL_STAT__4 0x0500
1219 #define MIB_COUNTER_DATA_HI_M 0xF
1221 #define REG_PORT_MIB_DATA 0x0504
1224 #define REG_PORT_ACL_0 0x0600
1226 #define ACL_FIRST_RULE_M 0xF
1228 #define REG_PORT_ACL_1 0x0601
1230 #define ACL_MODE_M 0x3
1232 #define ACL_MODE_DISABLE 0
1236 #define ACL_ENABLE_M 0x3
1238 #define ACL_ENABLE_2_COUNT 0
1244 #define ACL_ENABLE_4_PROTOCOL 0
1249 #define ACL_EQUAL BIT(0)
1251 #define REG_PORT_ACL_2 0x0602
1252 #define REG_PORT_ACL_3 0x0603
1254 #define ACL_MAX_PORT 0xFFFF
1256 #define REG_PORT_ACL_4 0x0604
1257 #define REG_PORT_ACL_5 0x0605
1259 #define ACL_MIN_PORT 0xFFFF
1260 #define ACL_IP_ADDR 0xFFFFFFFF
1261 #define ACL_TCP_SEQNUM 0xFFFFFFFF
1263 #define REG_PORT_ACL_6 0x0606
1265 #define ACL_RESERVED 0xF8
1266 #define ACL_PORT_MODE_M 0x3
1268 #define ACL_PORT_MODE_DISABLE 0
1273 #define REG_PORT_ACL_7 0x0607
1275 #define ACL_TCP_FLAG_ENABLE BIT(0)
1277 #define REG_PORT_ACL_8 0x0608
1279 #define ACL_TCP_FLAG_M 0xFF
1281 #define REG_PORT_ACL_9 0x0609
1283 #define ACL_TCP_FLAG 0xFF
1284 #define ACL_ETH_TYPE 0xFFFF
1285 #define ACL_IP_M 0xFFFFFFFF
1287 #define REG_PORT_ACL_A 0x060A
1289 #define ACL_PRIO_MODE_M 0x3
1291 #define ACL_PRIO_MODE_DISABLE 0
1299 #define ACL_VLAN_PRIO_HI_M 0x3
1301 #define REG_PORT_ACL_B 0x060B
1303 #define ACL_VLAN_PRIO_LO_M 0x8
1305 #define ACL_MAP_MODE_M 0x3
1307 #define ACL_MAP_MODE_DISABLE 0
1315 #define REG_PORT_ACL_C 0x060C
1317 #define REG_PORT_ACL_D 0x060D
1320 #define ACL_PORT_MAP 0x7F
1322 #define REG_PORT_ACL_E 0x060E
1323 #define REG_PORT_ACL_F 0x060F
1325 #define REG_PORT_ACL_BYTE_EN_MSB 0x0610
1326 #define REG_PORT_ACL_BYTE_EN_LSB 0x0611
1328 #define ACL_ACTION_START 0xA
1330 #define ACL_INTR_CNT_START 0xD
1331 #define ACL_RULESET_START 0xE
1335 #define ACL_ACTION_ENABLE 0x003C
1336 #define ACL_MATCH_ENABLE 0x7FC3
1337 #define ACL_RULESET_ENABLE 0x8003
1338 #define ACL_BYTE_ENABLE 0xFFFF
1340 #define REG_PORT_ACL_CTRL_0 0x0612
1345 #define PORT_ACL_INDEX_M 0xF
1347 #define REG_PORT_ACL_CTRL_1 0x0613
1350 #define REG_PORT_MRI_MIRROR_CTRL 0x0800
1356 #define REG_PORT_MRI_PRIO_CTRL 0x0801
1364 #define PORT_ACL_PRIO_ENABLE BIT(0)
1366 #define REG_PORT_MRI_MAC_CTRL 0x0802
1372 #define PORT_BASED_PRIO_S 0
1374 #define REG_PORT_MRI_AUTHEN_CTRL 0x0803
1377 #define PORT_AUTHEN_MODE 0x3
1378 #define PORT_AUTHEN_PASS 0
1382 #define REG_PORT_MRI_INDEX__4 0x0804
1384 #define MRI_INDEX_P_M 0x7
1386 #define MRI_INDEX_Q_M 0x3
1387 #define MRI_INDEX_Q_S 0
1389 #define REG_PORT_MRI_TC_MAP__4 0x0808
1391 #define PORT_TC_MAP_M 0xf
1394 #define REG_PORT_MRI_POLICE_CTRL__4 0x080C
1397 #define POLICE_PACKET_TYPE_M 0x3
1399 #define POLICE_PACKET_DROPPED 0
1404 #define NON_DSCP_COLOR_M 0x3
1410 #define POLICE_ENABLE BIT(0)
1412 #define REG_PORT_POLICE_COLOR_0__4 0x0810
1413 #define REG_PORT_POLICE_COLOR_1__4 0x0814
1414 #define REG_PORT_POLICE_COLOR_2__4 0x0818
1415 #define REG_PORT_POLICE_COLOR_3__4 0x081C
1420 #define REG_PORT_POLICE_RATE__4 0x0820
1423 #define POLICE_PIR_S 0
1425 #define REG_PORT_POLICE_BURST_SIZE__4 0x0824
1427 #define POLICE_BURST_SIZE_M 0x3FFF
1429 #define POLICE_PBS_S 0
1431 #define REG_PORT_WRED_PM_CTRL_0__4 0x0830
1436 #define WRED_PM_MIN_THRESHOLD_S 0
1438 #define REG_PORT_WRED_PM_CTRL_1__4 0x0834
1441 #define WRED_PM_AVG_QUEUE_SIZE_S 0
1443 #define REG_PORT_WRED_QUEUE_CTRL_0__4 0x0840
1444 #define REG_PORT_WRED_QUEUE_CTRL_1__4 0x0844
1446 #define REG_PORT_WRED_QUEUE_PMON__4 0x0848
1458 #define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904
1460 #define MTI_PVID_REPLACE BIT(0)
1462 #define REG_PORT_MTI_CREDIT_INCREMENT 0x091A
1466 #define REG_PORT_QM_CTRL__4 0x0A00
1468 #define PORT_QM_DROP_PRIO_M 0x3
1470 #define REG_PORT_VLAN_MEMBERSHIP__4 0x0A04
1472 #define REG_PORT_QM_QUEUE_INDEX__4 0x0A08
1478 #define REG_PORT_QM_WATER_MARK__4 0x0A0C
1481 #define PORT_QM_LO_WATER_MARK_S 0
1484 #define REG_PORT_QM_TX_CNT_0__4 0x0A10
1486 #define PORT_QM_TX_CNT_USED_S 0
1488 #define PORT_QM_TX_CNT_MAX 0x200
1490 #define REG_PORT_QM_TX_CNT_1__4 0x0A14
1493 #define PORT_QM_TX_CNT_AVAIL_S 0
1496 #define REG_PORT_LUE_CTRL 0x0B00
1504 #define REG_PORT_LUE_MSTP_INDEX 0x0B01
1506 #define REG_PORT_LUE_MSTP_STATE 0x0B04
1510 #define REG_PTP_PORT_RX_DELAY__2 0x0C00
1511 #define REG_PTP_PORT_TX_DELAY__2 0x0C02
1512 #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04
1514 #define REG_PTP_PORT_XDELAY_TS 0x0C08
1515 #define REG_PTP_PORT_XDELAY_TS_H 0x0C08
1516 #define REG_PTP_PORT_XDELAY_TS_L 0x0C0A
1518 #define REG_PTP_PORT_SYNC_TS 0x0C0C
1519 #define REG_PTP_PORT_SYNC_TS_H 0x0C0C
1520 #define REG_PTP_PORT_SYNC_TS_L 0x0C0E
1522 #define REG_PTP_PORT_PDRESP_TS 0x0C10
1523 #define REG_PTP_PORT_PDRESP_TS_H 0x0C10
1524 #define REG_PTP_PORT_PDRESP_TS_L 0x0C12
1526 #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14
1527 #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16
1533 #define REG_PTP_PORT_LINK_DELAY__4 0x0C18
1542 #define KSZ9477_COUNTER_NUM 0x20