Lines Matching +full:0 +full:x105
17 #define KS_PORT_M 0x1F
19 #define KS_PRIO_M 0x3
22 #define SW_REVISION_M 0x0E
25 #define KSZ8863_REG_SW_RESET 0x43
28 #define KSZ8863_PCS_RESET BIT(0)
30 #define KSZ88X3_REG_FVID_AND_HOST_MODE 0xC6
33 #define REG_SW_CTRL_0 0x02
39 #define SW_LINK_AUTO_AGING BIT(0)
41 #define REG_SW_CTRL_1 0x03
49 #define SW_AGGR_BACKOFF BIT(0)
51 #define REG_SW_CTRL_2 0x04
62 #define REG_SW_CTRL_3 0x05
67 #define SW_MIRROR_RX_TX BIT(0)
69 #define REG_SW_CTRL_4 0x06
77 #define REG_SW_CTRL_5 0x07
79 #define REG_SW_CTRL_6 0x08
85 #define REG_SW_CTRL_9 0x0B
87 #define SPI_CLK_125_MHZ 0x80
88 #define SPI_CLK_62_5_MHZ 0x40
89 #define SPI_CLK_31_25_MHZ 0x00
91 #define SW_LED_MODE_M 0x3
93 #define SW_LED_LINK_ACT_SPEED 0
98 #define REG_SW_CTRL_10 0x0C
100 #define SW_PASS_PAUSE BIT(0)
102 #define REG_SW_CTRL_11 0x0D
104 #define REG_POWER_MANAGEMENT_1 0x0E
107 #define SW_POWER_MANAGEMENT_MODE_M 0x3
109 #define SW_POWER_NORMAL 0
113 #define REG_POWER_MANAGEMENT_2 0x0F
115 #define REG_PORT_1_CTRL_0 0x10
116 #define REG_PORT_2_CTRL_0 0x20
117 #define REG_PORT_3_CTRL_0 0x30
118 #define REG_PORT_4_CTRL_0 0x40
119 #define REG_PORT_5_CTRL_0 0x50
126 #define PORT_BASED_PRIO_0 0
132 #define KSZ8795_PORT_2QUEUE_SPLIT_EN BIT(0)
133 #define KSZ8873_PORT_4QUEUE_SPLIT_EN BIT(0)
135 #define REG_PORT_1_CTRL_1 0x11
136 #define REG_PORT_2_CTRL_1 0x21
137 #define REG_PORT_3_CTRL_1 0x31
138 #define REG_PORT_4_CTRL_1 0x41
139 #define REG_PORT_5_CTRL_1 0x51
146 #define REG_PORT_1_CTRL_2 0x12
147 #define REG_PORT_2_CTRL_2 0x22
148 #define REG_PORT_3_CTRL_2 0x32
149 #define REG_PORT_4_CTRL_2 0x42
150 #define REG_PORT_5_CTRL_2 0x52
158 #define REG_PORT_1_CTRL_3 0x13
159 #define REG_PORT_2_CTRL_3 0x23
160 #define REG_PORT_3_CTRL_3 0x33
161 #define REG_PORT_4_CTRL_3 0x43
162 #define REG_PORT_5_CTRL_3 0x53
163 #define REG_PORT_1_CTRL_4 0x14
164 #define REG_PORT_2_CTRL_4 0x24
165 #define REG_PORT_3_CTRL_4 0x34
166 #define REG_PORT_4_CTRL_4 0x44
167 #define REG_PORT_5_CTRL_4 0x54
169 #define PORT_DEFAULT_VID 0x0001
171 #define REG_PORT_1_CTRL_5 0x15
172 #define REG_PORT_2_CTRL_5 0x25
173 #define REG_PORT_3_CTRL_5 0x35
174 #define REG_PORT_4_CTRL_5 0x45
175 #define REG_PORT_5_CTRL_5 0x55
178 #define PORT_AUTHEN_MODE 0x3
179 #define PORT_AUTHEN_PASS 0
183 #define REG_PORT_5_CTRL_6 0x56
188 #define REG_PORT_1_CTRL_7 0x17
189 #define REG_PORT_2_CTRL_7 0x27
190 #define REG_PORT_3_CTRL_7 0x37
191 #define REG_PORT_4_CTRL_7 0x47
198 #define PORT_AUTO_NEG_10BT BIT(0)
200 #define REG_PORT_1_STATUS_0 0x18
201 #define REG_PORT_2_STATUS_0 0x28
202 #define REG_PORT_3_STATUS_0 0x38
203 #define REG_PORT_4_STATUS_0 0x48
211 #define PORT_REMOTE_10BT BIT(0)
213 #define REG_PORT_1_STATUS_1 0x19
214 #define REG_PORT_2_STATUS_1 0x29
215 #define REG_PORT_3_STATUS_1 0x39
216 #define REG_PORT_4_STATUS_1 0x49
225 #define PORT_REMOTE_FAULT BIT(0)
227 #define REG_PORT_1_LINK_MD_CTRL 0x1A
228 #define REG_PORT_2_LINK_MD_CTRL 0x2A
229 #define REG_PORT_3_LINK_MD_CTRL 0x3A
230 #define REG_PORT_4_LINK_MD_CTRL 0x4A
235 #define PORT_CABLE_STAT_NORMAL 0
243 #define PORT_CABLE_FAULT_COUNTER_H 0x01
245 #define REG_PORT_1_LINK_MD_RESULT 0x1B
246 #define REG_PORT_2_LINK_MD_RESULT 0x2B
247 #define REG_PORT_3_LINK_MD_RESULT 0x3B
248 #define REG_PORT_4_LINK_MD_RESULT 0x4B
250 #define PORT_CABLE_FAULT_COUNTER_L 0xFF
251 #define PORT_CABLE_FAULT_COUNTER 0x1FF
253 #define REG_PORT_1_CTRL_9 0x1C
254 #define REG_PORT_2_CTRL_9 0x2C
255 #define REG_PORT_3_CTRL_9 0x3C
256 #define REG_PORT_4_CTRL_9 0x4C
263 #define REG_PORT_1_CTRL_10 0x1D
264 #define REG_PORT_2_CTRL_10 0x2D
265 #define REG_PORT_3_CTRL_10 0x3D
266 #define REG_PORT_4_CTRL_10 0x4D
274 #define PORT_MAC_LOOPBACK BIT(0)
275 #define KSZ8873_PORT_PHY_LOOPBACK BIT(0)
277 #define REG_PORT_1_STATUS_2 0x1E
278 #define REG_PORT_2_STATUS_2 0x2E
279 #define REG_PORT_3_STATUS_2 0x3E
280 #define REG_PORT_4_STATUS_2 0x4E
286 #define REG_PORT_1_STATUS_3 0x1F
287 #define REG_PORT_2_STATUS_3 0x2F
288 #define REG_PORT_3_STATUS_3 0x3F
289 #define REG_PORT_4_STATUS_3 0x4F
295 #define PORT_PHY_MODE_M 0x7
303 #define REG_PORT_CTRL_0 0x00
304 #define REG_PORT_CTRL_1 0x01
305 #define REG_PORT_CTRL_2 0x02
306 #define REG_PORT_CTRL_VID 0x03
308 #define REG_PORT_CTRL_5 0x05
310 #define REG_PORT_STATUS_1 0x09
311 #define REG_PORT_LINK_MD_CTRL 0x0A
312 #define REG_PORT_LINK_MD_RESULT 0x0B
313 #define REG_PORT_CTRL_9 0x0C
314 #define REG_PORT_CTRL_10 0x0D
315 #define REG_PORT_STATUS_3 0x0F
317 #define REG_PORT_CTRL_12 0xA0
318 #define REG_PORT_CTRL_13 0xA1
319 #define REG_PORT_RATE_CTRL_3 0xA2
320 #define REG_PORT_RATE_CTRL_2 0xA3
321 #define REG_PORT_RATE_CTRL_1 0xA4
322 #define REG_PORT_RATE_CTRL_0 0xA5
323 #define REG_PORT_RATE_LIMIT 0xA6
324 #define REG_PORT_IN_RATE_0 0xA7
325 #define REG_PORT_IN_RATE_1 0xA8
326 #define REG_PORT_IN_RATE_2 0xA9
327 #define REG_PORT_IN_RATE_3 0xAA
328 #define REG_PORT_OUT_RATE_0 0xAB
329 #define REG_PORT_OUT_RATE_1 0xAC
330 #define REG_PORT_OUT_RATE_2 0xAD
331 #define REG_PORT_OUT_RATE_3 0xAE
348 #define TABLE_STATIC_MAC_V 0
357 #define REG_IND_CTRL_1 0x6F
359 #define TABLE_ENTRY_MASK 0x03FF
360 #define TABLE_EXT_ENTRY_MASK 0x0FFF
362 #define REG_IND_DATA_5 0x73
363 #define REG_IND_DATA_2 0x76
364 #define REG_IND_DATA_1 0x77
365 #define REG_IND_DATA_0 0x78
367 #define REG_INT_STATUS 0x7C
368 #define REG_INT_ENABLE 0x7D
372 #define REG_ACL_INT_STATUS 0x7E
373 #define REG_ACL_INT_ENABLE 0x7F
379 #define INT_PORT_1 BIT(0)
384 #define REG_SW_CTRL_12 0x80
385 #define REG_SW_CTRL_13 0x81
394 #define REG_SWITCH_CTRL_14 0x82
398 #define SW_PRIO_MAP_3_HI 0
402 #define REG_SW_CTRL_15 0x83
403 #define REG_SW_CTRL_16 0x84
404 #define REG_SW_CTRL_17 0x85
405 #define REG_SW_CTRL_18 0x86
409 #define REG_SW_UNK_UCAST_CTRL 0x83
410 #define REG_SW_UNK_MCAST_CTRL 0x84
411 #define REG_SW_UNK_VID_CTRL 0x85
412 #define REG_SW_UNK_IP_MCAST_CTRL 0x86
417 #define REG_SW_CTRL_19 0x87
419 #define SW_IN_RATE_LIMIT_PERIOD_M 0x3
421 #define SW_IN_RATE_LIMIT_16_MS 0
427 #define REG_TOS_PRIO_CTRL_0 0x90
428 #define REG_TOS_PRIO_CTRL_1 0x91
429 #define REG_TOS_PRIO_CTRL_2 0x92
430 #define REG_TOS_PRIO_CTRL_3 0x93
431 #define REG_TOS_PRIO_CTRL_4 0x94
432 #define REG_TOS_PRIO_CTRL_5 0x95
433 #define REG_TOS_PRIO_CTRL_6 0x96
434 #define REG_TOS_PRIO_CTRL_7 0x97
435 #define REG_TOS_PRIO_CTRL_8 0x98
436 #define REG_TOS_PRIO_CTRL_9 0x99
437 #define REG_TOS_PRIO_CTRL_10 0x9A
438 #define REG_TOS_PRIO_CTRL_11 0x9B
439 #define REG_TOS_PRIO_CTRL_12 0x9C
440 #define REG_TOS_PRIO_CTRL_13 0x9D
441 #define REG_TOS_PRIO_CTRL_14 0x9E
442 #define REG_TOS_PRIO_CTRL_15 0x9F
447 #define REG_SW_CTRL_21 0xA4
452 #define REG_PORT_1_CTRL_12 0xB0
453 #define REG_PORT_2_CTRL_12 0xC0
454 #define REG_PORT_3_CTRL_12 0xD0
455 #define REG_PORT_4_CTRL_12 0xE0
456 #define REG_PORT_5_CTRL_12 0xF0
463 #define PORT_INS_TAG_FOR_PORT_2 BIT(0)
465 #define REG_PORT_1_CTRL_13 0xB1
466 #define REG_PORT_2_CTRL_13 0xC1
467 #define REG_PORT_3_CTRL_13 0xD1
468 #define REG_PORT_4_CTRL_13 0xE1
469 #define REG_PORT_5_CTRL_13 0xF1
472 #define PORT_DROP_TAG BIT(0)
474 #define REG_PORT_1_CTRL_14 0xB2
475 #define REG_PORT_2_CTRL_14 0xC2
476 #define REG_PORT_3_CTRL_14 0xD2
477 #define REG_PORT_4_CTRL_14 0xE2
478 #define REG_PORT_5_CTRL_14 0xF2
479 #define REG_PORT_1_CTRL_15 0xB3
480 #define REG_PORT_2_CTRL_15 0xC3
481 #define REG_PORT_3_CTRL_15 0xD3
482 #define REG_PORT_4_CTRL_15 0xE3
483 #define REG_PORT_5_CTRL_15 0xF3
484 #define REG_PORT_1_CTRL_16 0xB4
485 #define REG_PORT_2_CTRL_16 0xC4
486 #define REG_PORT_3_CTRL_16 0xD4
487 #define REG_PORT_4_CTRL_16 0xE4
488 #define REG_PORT_5_CTRL_16 0xF4
489 #define REG_PORT_1_CTRL_17 0xB5
490 #define REG_PORT_2_CTRL_17 0xC5
491 #define REG_PORT_3_CTRL_17 0xD5
492 #define REG_PORT_4_CTRL_17 0xE5
493 #define REG_PORT_5_CTRL_17 0xF5
495 #define REG_PORT_1_RATE_CTRL_3 0xB2
496 #define REG_PORT_1_RATE_CTRL_2 0xB3
497 #define REG_PORT_1_RATE_CTRL_1 0xB4
498 #define REG_PORT_1_RATE_CTRL_0 0xB5
499 #define REG_PORT_2_RATE_CTRL_3 0xC2
500 #define REG_PORT_2_RATE_CTRL_2 0xC3
501 #define REG_PORT_2_RATE_CTRL_1 0xC4
502 #define REG_PORT_2_RATE_CTRL_0 0xC5
503 #define REG_PORT_3_RATE_CTRL_3 0xD2
504 #define REG_PORT_3_RATE_CTRL_2 0xD3
505 #define REG_PORT_3_RATE_CTRL_1 0xD4
506 #define REG_PORT_3_RATE_CTRL_0 0xD5
507 #define REG_PORT_4_RATE_CTRL_3 0xE2
508 #define REG_PORT_4_RATE_CTRL_2 0xE3
509 #define REG_PORT_4_RATE_CTRL_1 0xE4
510 #define REG_PORT_4_RATE_CTRL_0 0xE5
511 #define REG_PORT_5_RATE_CTRL_3 0xF2
512 #define REG_PORT_5_RATE_CTRL_2 0xF3
513 #define REG_PORT_5_RATE_CTRL_1 0xF4
514 #define REG_PORT_5_RATE_CTRL_0 0xF5
521 #define REG_PORT_1_RATE_LIMIT 0xB6
522 #define REG_PORT_2_RATE_LIMIT 0xC6
523 #define REG_PORT_3_RATE_LIMIT 0xD6
524 #define REG_PORT_4_RATE_LIMIT 0xE6
525 #define REG_PORT_5_RATE_LIMIT 0xF6
530 #define PORT_IN_LIMIT_MODE_M 0x3
533 #define PORT_COUNT_PREAMBLE_S 0
537 #define PORT_IN_ALL 0
544 #define REG_PORT_1_IN_RATE_0 0xB7
545 #define REG_PORT_2_IN_RATE_0 0xC7
546 #define REG_PORT_3_IN_RATE_0 0xD7
547 #define REG_PORT_4_IN_RATE_0 0xE7
548 #define REG_PORT_5_IN_RATE_0 0xF7
549 #define REG_PORT_1_IN_RATE_1 0xB8
550 #define REG_PORT_2_IN_RATE_1 0xC8
551 #define REG_PORT_3_IN_RATE_1 0xD8
552 #define REG_PORT_4_IN_RATE_1 0xE8
553 #define REG_PORT_5_IN_RATE_1 0xF8
554 #define REG_PORT_1_IN_RATE_2 0xB9
555 #define REG_PORT_2_IN_RATE_2 0xC9
556 #define REG_PORT_3_IN_RATE_2 0xD9
557 #define REG_PORT_4_IN_RATE_2 0xE9
558 #define REG_PORT_5_IN_RATE_2 0xF9
559 #define REG_PORT_1_IN_RATE_3 0xBA
560 #define REG_PORT_2_IN_RATE_3 0xCA
561 #define REG_PORT_3_IN_RATE_3 0xDA
562 #define REG_PORT_4_IN_RATE_3 0xEA
563 #define REG_PORT_5_IN_RATE_3 0xFA
568 #define REG_PORT_1_OUT_RATE_0 0xBB
569 #define REG_PORT_2_OUT_RATE_0 0xCB
570 #define REG_PORT_3_OUT_RATE_0 0xDB
571 #define REG_PORT_4_OUT_RATE_0 0xEB
572 #define REG_PORT_5_OUT_RATE_0 0xFB
573 #define REG_PORT_1_OUT_RATE_1 0xBC
574 #define REG_PORT_2_OUT_RATE_1 0xCC
575 #define REG_PORT_3_OUT_RATE_1 0xDC
576 #define REG_PORT_4_OUT_RATE_1 0xEC
577 #define REG_PORT_5_OUT_RATE_1 0xFC
578 #define REG_PORT_1_OUT_RATE_2 0xBD
579 #define REG_PORT_2_OUT_RATE_2 0xCD
580 #define REG_PORT_3_OUT_RATE_2 0xDD
581 #define REG_PORT_4_OUT_RATE_2 0xED
582 #define REG_PORT_5_OUT_RATE_2 0xFD
583 #define REG_PORT_1_OUT_RATE_3 0xBE
584 #define REG_PORT_2_OUT_RATE_3 0xCE
585 #define REG_PORT_3_OUT_RATE_3 0xDE
586 #define REG_PORT_4_OUT_RATE_3 0xEE
587 #define REG_PORT_5_OUT_RATE_3 0xFE
591 #define REG_SW_INSERT_SRC_PVID 0xC2
596 #define SW_PME_ACTIVE_HIGH BIT(0)
600 #define PORT_ENERGY_DETECT BIT(0)
604 #define ACL_FIRST_RULE_M 0xF
606 #define ACL_MODE_M 0x3
608 #define ACL_MODE_DISABLE 0
612 #define ACL_ENABLE_M 0x3
614 #define ACL_ENABLE_2_COUNT 0
620 #define ACL_ENABLE_4_PROTOCOL 0
625 #define ACL_EQUAL BIT(0)
627 #define ACL_MAX_PORT 0xFFFF
629 #define ACL_MIN_PORT 0xFFFF
630 #define ACL_IP_ADDR 0xFFFFFFFF
631 #define ACL_TCP_SEQNUM 0xFFFFFFFF
633 #define ACL_RESERVED 0xF8
634 #define ACL_PORT_MODE_M 0x3
636 #define ACL_PORT_MODE_DISABLE 0
641 #define ACL_TCP_FLAG_ENABLE BIT(0)
643 #define ACL_TCP_FLAG_M 0xFF
645 #define ACL_TCP_FLAG 0xFF
646 #define ACL_ETH_TYPE 0xFFFF
647 #define ACL_IP_M 0xFFFFFFFF
649 #define ACL_PRIO_MODE_M 0x3
651 #define ACL_PRIO_MODE_DISABLE 0
655 #define ACL_PRIO_M 0x7
658 #define ACL_VLAN_PRIO_M 0x7
659 #define ACL_VLAN_PRIO_HI_M 0x3
661 #define ACL_VLAN_PRIO_LO_M 0x8
663 #define ACL_MAP_MODE_M 0x3
665 #define ACL_MAP_MODE_DISABLE 0
669 #define ACL_MAP_PORT_M 0x1F
676 #define REG_PORT_ACL_BYTE_EN_MSB 0x10
678 #define ACL_BYTE_EN_MSB_M 0x3F
680 #define REG_PORT_ACL_BYTE_EN_LSB 0x11
682 #define ACL_ACTION_START 0xA
684 #define ACL_INTR_CNT_START 0xB
685 #define ACL_RULESET_START 0xC
689 #define ACL_ACTION_ENABLE 0x000C
690 #define ACL_MATCH_ENABLE 0x1FF0
691 #define ACL_RULESET_ENABLE 0x2003
692 #define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF)
693 #define ACL_MODE_ENABLE (0x10 << 8)
695 #define REG_PORT_ACL_CTRL_0 0x12
700 #define PORT_ACL_INDEX_M 0xF
702 #define REG_PORT_ACL_CTRL_1 0x13
704 #define PORT_ACL_FORCE_DLR_MISS BIT(0)
706 #define KSZ8795_ID_HI 0x0022
707 #define KSZ8795_ID_LO 0x1550
708 #define KSZ8863_ID_LO 0x1430
710 #define PHY_REG_LINK_MD 0x1D
714 #define PHY_CABLE_DIAG_RESULT 0x6000
715 #define PHY_CABLE_STAT_NORMAL 0x0000
716 #define PHY_CABLE_STAT_OPEN 0x2000
717 #define PHY_CABLE_STAT_SHORT 0x4000
718 #define PHY_CABLE_STAT_FAILED 0x6000
720 #define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0)
722 #define PHY_REG_PHY_CTRL 0x1F
724 #define PHY_MODE_M 0x7
733 #define P1MBCR 0x4C
734 #define P1MBSR 0x4E
735 #define PHY1ILR 0x50
736 #define PHY1IHR 0x52
737 #define P1ANAR 0x54
738 #define P1ANLPR 0x56
739 #define P2MBCR 0x58
740 #define P2MBSR 0x5A
741 #define PHY2ILR 0x5C
742 #define PHY2IHR 0x5E
743 #define P2ANAR 0x60
744 #define P2ANLPR 0x62
746 #define P1CR1 0x6C
747 #define P1CR2 0x6E
748 #define P1CR3 0x72
749 #define P1CR4 0x7E
750 #define P1SR 0x80
752 #define KSZ8463_FLUSH_TABLE_CTRL 0xAD
757 #define KSZ8463_REG_SW_CTRL_9 0xAE
759 #define KSZ8463_REG_CFG_CTRL 0xD8
765 #define KSZ8463_REG_SW_RESET 0x126
767 #define KSZ8463_GLOBAL_SOFTWARE_RESET BIT(0)
769 #define KSZ8463_PTP_CLK_CTRL 0x600
773 #define KSZ8463_PTP_MSG_CONF1 0x620
777 #define KSZ8463_REG_DSP_CTRL_6 0x734
787 #define MIB_COUNTER_NUM 0x20
817 #define REG_IND_EEE_GLOB2_LO 0x34
818 #define REG_IND_EEE_GLOB2_HI 0x35
828 #define MIB_COUNTER_VALUE 0x3FFFFFFF
830 #define KSZ8795_MIB_TOTAL_RX_0 0x100
831 #define KSZ8795_MIB_TOTAL_TX_0 0x101
832 #define KSZ8795_MIB_TOTAL_RX_1 0x104
833 #define KSZ8795_MIB_TOTAL_TX_1 0x105
835 #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100
836 #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x103
838 #define KSZ8895_MIB_PACKET_DROPPED_RX_0 0x105
840 #define MIB_PACKET_DROPPED 0x0000FFFF
842 #define MIB_TOTAL_BYTES_H 0x0000000F