Lines Matching +full:can +full:- +full:transceiver
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface
6 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver
11 * Based on CAN bus driver for the CCAN controller written by
12 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
13 * - Simon Kallweit, intefo AG
17 #include <linux/can/core.h>
18 #include <linux/can/dev.h>
145 struct can_priv can; member
171 struct regulator *transceiver; member
179 if (priv->tx_skb || priv->tx_busy) in hi3110_clean()
180 net->stats.tx_errors++; in hi3110_clean()
181 dev_kfree_skb(priv->tx_skb); in hi3110_clean()
182 if (priv->tx_busy) in hi3110_clean()
183 can_free_echo_skb(priv->net, 0, NULL); in hi3110_clean()
184 priv->tx_skb = NULL; in hi3110_clean()
185 priv->tx_busy = false; in hi3110_clean()
204 .tx_buf = priv->spi_tx_buf, in hi3110_spi_trans()
205 .rx_buf = priv->spi_rx_buf, in hi3110_spi_trans()
218 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); in hi3110_spi_trans()
226 priv->spi_tx_buf[0] = command; in hi3110_cmd()
227 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command); in hi3110_cmd()
237 priv->spi_tx_buf[0] = command; in hi3110_read()
239 val = priv->spi_rx_buf[1]; in hi3110_read()
248 priv->spi_tx_buf[0] = reg; in hi3110_write()
249 priv->spi_tx_buf[1] = val; in hi3110_write()
257 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO; in hi3110_hw_tx_frame()
258 memcpy(priv->spi_tx_buf + 1, buf, len); in hi3110_hw_tx_frame()
268 if (frame->can_id & CAN_EFF_FLAG) { in hi3110_hw_tx()
270 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21; in hi3110_hw_tx()
272 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) | in hi3110_hw_tx()
274 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07); in hi3110_hw_tx()
276 (frame->can_id & CAN_EFF_MASK) >> 7; in hi3110_hw_tx()
278 ((frame->can_id & CAN_EFF_MASK) << 1) | in hi3110_hw_tx()
279 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0); in hi3110_hw_tx()
281 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->len; in hi3110_hw_tx()
284 frame->data, frame->len); in hi3110_hw_tx()
286 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN - in hi3110_hw_tx()
287 (HI3110_CAN_MAX_DATA_LEN - frame->len)); in hi3110_hw_tx()
290 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3; in hi3110_hw_tx()
292 ((frame->can_id & CAN_SFF_MASK) << 5) | in hi3110_hw_tx()
293 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0); in hi3110_hw_tx()
295 buf[HI3110_FIFO_STD_DLC_OFF] = frame->len; in hi3110_hw_tx()
298 frame->data, frame->len); in hi3110_hw_tx()
300 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN - in hi3110_hw_tx()
301 (HI3110_CAN_MAX_DATA_LEN - frame->len)); in hi3110_hw_tx()
309 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME; in hi3110_hw_rx_frame()
311 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1); in hi3110_hw_rx_frame()
319 u8 buf[HI3110_RX_BUF_LEN - 1]; in hi3110_hw_rx()
321 skb = alloc_can_skb(priv->net, &frame); in hi3110_hw_rx()
323 priv->net->stats.rx_dropped++; in hi3110_hw_rx()
329 /* IDE is recessive (1), indicating extended 29-bit frame */ in hi3110_hw_rx()
330 frame->can_id = CAN_EFF_FLAG; in hi3110_hw_rx()
331 frame->can_id |= in hi3110_hw_rx()
338 /* IDE is dominant (0), frame indicating standard 11-bit */ in hi3110_hw_rx()
339 frame->can_id = in hi3110_hw_rx()
345 frame->len = can_cc_dlc2len(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F); in hi3110_hw_rx()
348 frame->can_id |= CAN_RTR_FLAG; in hi3110_hw_rx()
350 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF, in hi3110_hw_rx()
351 frame->len); in hi3110_hw_rx()
353 priv->net->stats.rx_bytes += frame->len; in hi3110_hw_rx()
355 priv->net->stats.rx_packets++; in hi3110_hw_rx()
369 struct spi_device *spi = priv->spi; in hi3110_hard_start_xmit()
371 if (priv->tx_skb || priv->tx_busy) { in hi3110_hard_start_xmit()
372 dev_err(&spi->dev, "hard_xmit called while tx busy\n"); in hi3110_hard_start_xmit()
380 priv->tx_skb = skb; in hi3110_hard_start_xmit()
381 queue_work(priv->wq, &priv->tx_work); in hi3110_hard_start_xmit()
394 priv->can.state = CAN_STATE_ERROR_ACTIVE; in hi3110_do_set_mode()
395 priv->restart_tx = 1; in hi3110_do_set_mode()
396 if (priv->can.restart_ms == 0) in hi3110_do_set_mode()
397 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART; in hi3110_do_set_mode()
398 queue_work(priv->wq, &priv->restart_work); in hi3110_do_set_mode()
401 return -EOPNOTSUPP; in hi3110_do_set_mode()
411 struct spi_device *spi = priv->spi; in hi3110_get_berr_counter()
413 mutex_lock(&priv->hi3110_lock); in hi3110_get_berr_counter()
414 bec->txerr = hi3110_read(spi, HI3110_READ_TEC); in hi3110_get_berr_counter()
415 bec->rxerr = hi3110_read(spi, HI3110_READ_REC); in hi3110_get_berr_counter()
416 mutex_unlock(&priv->hi3110_lock); in hi3110_get_berr_counter()
432 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in hi3110_set_normal_mode()
434 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in hi3110_set_normal_mode()
445 return -EBUSY; in hi3110_set_normal_mode()
447 priv->can.state = CAN_STATE_ERROR_ACTIVE; in hi3110_set_normal_mode()
454 struct can_bittiming *bt = &priv->can.bittiming; in hi3110_do_set_bittiming()
455 struct spi_device *spi = priv->spi; in hi3110_do_set_bittiming()
458 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) | in hi3110_do_set_bittiming()
459 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT)); in hi3110_do_set_bittiming()
462 (priv->can.ctrlmode & in hi3110_do_set_bittiming()
465 ((bt->phase_seg1 + bt->prop_seg - 1) in hi3110_do_set_bittiming()
467 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT)); in hi3110_do_set_bittiming()
469 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n", in hi3110_do_set_bittiming()
499 return -ENODEV; in hi3110_hw_reset()
520 dev_dbg(&spi->dev, "statf: %02X\n", statf); in hi3110_hw_probe()
523 return -ENODEV; in hi3110_hw_probe()
542 struct spi_device *spi = priv->spi; in hi3110_stop()
546 priv->force_quit = 1; in hi3110_stop()
547 free_irq(spi->irq, priv); in hi3110_stop()
548 destroy_workqueue(priv->wq); in hi3110_stop()
549 priv->wq = NULL; in hi3110_stop()
551 mutex_lock(&priv->hi3110_lock); in hi3110_stop()
562 hi3110_power_enable(priv->transceiver, 0); in hi3110_stop()
564 priv->can.state = CAN_STATE_STOPPED; in hi3110_stop()
566 mutex_unlock(&priv->hi3110_lock); in hi3110_stop()
575 struct spi_device *spi = priv->spi; in hi3110_tx_work_handler()
576 struct net_device *net = priv->net; in hi3110_tx_work_handler()
579 mutex_lock(&priv->hi3110_lock); in hi3110_tx_work_handler()
580 if (priv->tx_skb) { in hi3110_tx_work_handler()
581 if (priv->can.state == CAN_STATE_BUS_OFF) { in hi3110_tx_work_handler()
584 frame = (struct can_frame *)priv->tx_skb->data; in hi3110_tx_work_handler()
586 priv->tx_busy = true; in hi3110_tx_work_handler()
587 can_put_echo_skb(priv->tx_skb, net, 0, 0); in hi3110_tx_work_handler()
588 priv->tx_skb = NULL; in hi3110_tx_work_handler()
591 mutex_unlock(&priv->hi3110_lock); in hi3110_tx_work_handler()
598 struct spi_device *spi = priv->spi; in hi3110_restart_work_handler()
599 struct net_device *net = priv->net; in hi3110_restart_work_handler()
601 mutex_lock(&priv->hi3110_lock); in hi3110_restart_work_handler()
602 if (priv->after_suspend) { in hi3110_restart_work_handler()
605 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) { in hi3110_restart_work_handler()
607 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { in hi3110_restart_work_handler()
615 priv->after_suspend = 0; in hi3110_restart_work_handler()
616 priv->force_quit = 0; in hi3110_restart_work_handler()
619 if (priv->restart_tx) { in hi3110_restart_work_handler()
620 priv->restart_tx = 0; in hi3110_restart_work_handler()
627 mutex_unlock(&priv->hi3110_lock); in hi3110_restart_work_handler()
633 struct spi_device *spi = priv->spi; in hi3110_can_ist()
634 struct net_device *net = priv->net; in hi3110_can_ist()
636 mutex_lock(&priv->hi3110_lock); in hi3110_can_ist()
638 while (!priv->force_quit) { in hi3110_can_ist()
649 /* Update can state */ in hi3110_can_ist()
659 if (new_state != priv->can.state) { in hi3110_can_ist()
677 if (priv->can.restart_ms == 0) { in hi3110_can_ist()
678 priv->force_quit = 1; in hi3110_can_ist()
683 cf->can_id |= CAN_ERR_CNT; in hi3110_can_ist()
684 cf->data[6] = txerr; in hi3110_can_ist()
685 cf->data[7] = rxerr; in hi3110_can_ist()
692 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { in hi3110_can_ist()
700 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; in hi3110_can_ist()
702 priv->can.can_stats.bus_error++; in hi3110_can_ist()
704 priv->net->stats.tx_errors++; in hi3110_can_ist()
706 cf->data[2] |= CAN_ERR_PROT_BIT; in hi3110_can_ist()
708 priv->net->stats.rx_errors++; in hi3110_can_ist()
710 cf->data[2] |= CAN_ERR_PROT_FORM; in hi3110_can_ist()
712 priv->net->stats.rx_errors++; in hi3110_can_ist()
714 cf->data[2] |= CAN_ERR_PROT_STUFF; in hi3110_can_ist()
716 priv->net->stats.rx_errors++; in hi3110_can_ist()
718 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; in hi3110_can_ist()
720 priv->net->stats.tx_errors++; in hi3110_can_ist()
722 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; in hi3110_can_ist()
725 netdev_dbg(priv->net, "Bus Error\n"); in hi3110_can_ist()
727 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC); in hi3110_can_ist()
728 cf->data[7] = hi3110_read(spi, HI3110_READ_REC); in hi3110_can_ist()
734 if (priv->tx_busy && statf & HI3110_STAT_TXMTY) { in hi3110_can_ist()
735 net->stats.tx_packets++; in hi3110_can_ist()
736 net->stats.tx_bytes += can_get_echo_skb(net, 0, NULL); in hi3110_can_ist()
737 priv->tx_busy = false; in hi3110_can_ist()
744 mutex_unlock(&priv->hi3110_lock); in hi3110_can_ist()
751 struct spi_device *spi = priv->spi; in hi3110_open()
759 mutex_lock(&priv->hi3110_lock); in hi3110_open()
760 hi3110_power_enable(priv->transceiver, 1); in hi3110_open()
762 priv->force_quit = 0; in hi3110_open()
763 priv->tx_skb = NULL; in hi3110_open()
764 priv->tx_busy = false; in hi3110_open()
766 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist, in hi3110_open()
769 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); in hi3110_open()
773 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, in hi3110_open()
775 if (!priv->wq) { in hi3110_open()
776 ret = -ENOMEM; in hi3110_open()
779 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler); in hi3110_open()
780 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler); in hi3110_open()
795 mutex_unlock(&priv->hi3110_lock); in hi3110_open()
800 destroy_workqueue(priv->wq); in hi3110_open()
802 free_irq(spi->irq, priv); in hi3110_open()
805 hi3110_power_enable(priv->transceiver, 0); in hi3110_open()
807 mutex_unlock(&priv->hi3110_lock); in hi3110_open()
841 struct device *dev = &spi->dev; in hi3110_can_probe()
848 clk = devm_clk_get_optional(&spi->dev, NULL); in hi3110_can_probe()
850 return dev_err_probe(dev, PTR_ERR(clk), "no CAN clock source defined\n"); in hi3110_can_probe()
855 ret = device_property_read_u32(dev, "clock-frequency", &freq); in hi3110_can_probe()
857 return dev_err_probe(dev, ret, "Failed to get clock-frequency!\n"); in hi3110_can_probe()
862 return -ERANGE; in hi3110_can_probe()
864 /* Allocate can/net device */ in hi3110_can_probe()
867 return -ENOMEM; in hi3110_can_probe()
873 net->netdev_ops = &hi3110_netdev_ops; in hi3110_can_probe()
874 net->ethtool_ops = &hi3110_ethtool_ops; in hi3110_can_probe()
875 net->flags |= IFF_ECHO; in hi3110_can_probe()
878 priv->can.bittiming_const = &hi3110_bittiming_const; in hi3110_can_probe()
879 priv->can.do_set_mode = hi3110_do_set_mode; in hi3110_can_probe()
880 priv->can.do_get_berr_counter = hi3110_get_berr_counter; in hi3110_can_probe()
881 priv->can.clock.freq = freq / 2; in hi3110_can_probe()
882 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | in hi3110_can_probe()
887 priv->model = (enum hi3110_model)(uintptr_t)spi_get_device_match_data(spi); in hi3110_can_probe()
888 priv->net = net; in hi3110_can_probe()
889 priv->clk = clk; in hi3110_can_probe()
894 spi->bits_per_word = 8; in hi3110_can_probe()
899 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); in hi3110_can_probe()
900 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); in hi3110_can_probe()
901 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || in hi3110_can_probe()
902 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { in hi3110_can_probe()
903 ret = -EPROBE_DEFER; in hi3110_can_probe()
907 ret = hi3110_power_enable(priv->power, 1); in hi3110_can_probe()
911 priv->spi = spi; in hi3110_can_probe()
912 mutex_init(&priv->hi3110_lock); in hi3110_can_probe()
914 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, in hi3110_can_probe()
916 if (!priv->spi_tx_buf) { in hi3110_can_probe()
917 ret = -ENOMEM; in hi3110_can_probe()
920 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, in hi3110_can_probe()
923 if (!priv->spi_rx_buf) { in hi3110_can_probe()
924 ret = -ENOMEM; in hi3110_can_probe()
928 SET_NETDEV_DEV(net, &spi->dev); in hi3110_can_probe()
932 dev_err_probe(dev, ret, "Cannot initialize %x. Wrong wiring?\n", priv->model); in hi3110_can_probe()
941 netdev_info(net, "%x successfully initialized.\n", priv->model); in hi3110_can_probe()
946 hi3110_power_enable(priv->power, 0); in hi3110_can_probe()
960 struct net_device *net = priv->net; in hi3110_can_remove()
964 hi3110_power_enable(priv->power, 0); in hi3110_can_remove()
966 clk_disable_unprepare(priv->clk); in hi3110_can_remove()
975 struct net_device *net = priv->net; in hi3110_can_suspend()
977 priv->force_quit = 1; in hi3110_can_suspend()
978 disable_irq(spi->irq); in hi3110_can_suspend()
987 hi3110_power_enable(priv->transceiver, 0); in hi3110_can_suspend()
988 priv->after_suspend = HI3110_AFTER_SUSPEND_UP; in hi3110_can_suspend()
990 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN; in hi3110_can_suspend()
993 if (!IS_ERR_OR_NULL(priv->power)) { in hi3110_can_suspend()
994 regulator_disable(priv->power); in hi3110_can_suspend()
995 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER; in hi3110_can_suspend()
1006 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER) in hi3110_can_resume()
1007 hi3110_power_enable(priv->power, 1); in hi3110_can_resume()
1009 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { in hi3110_can_resume()
1010 hi3110_power_enable(priv->transceiver, 1); in hi3110_can_resume()
1011 queue_work(priv->wq, &priv->restart_work); in hi3110_can_resume()
1013 priv->after_suspend = 0; in hi3110_can_resume()
1016 priv->force_quit = 0; in hi3110_can_resume()
1017 enable_irq(spi->irq); in hi3110_can_resume()
1038 MODULE_DESCRIPTION("Holt HI-3110 CAN driver");