Lines Matching +full:channel +full:- +full:fifo +full:- +full:len
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
74 /* Non-operational status */
87 ((x) & ((FIELD_PREP(RCANFD_GERFL_EEF, (_gpriv)->channels_mask)) | \
88 RCANFD_GERFL_MES | ((_gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0))); \
95 #define RCANFD_GAFLECTR_AFLPN(gpriv, page_num) ((page_num) & (gpriv)->info->max_aflpn)
103 /* Channel register bits */
105 /* RSCFDnCmCFG - Classical CAN only */
111 /* RSCFDnCFDCmNCFG - CAN FD only */
216 /* Common FIFO bits */
222 (((cftml) & (_gpriv)->info->max_cftml) << (_gpriv)->info->sh->cftml); \
224 #define RCANFD_CFCC_CFM(gpriv, x) (((x) & 0x3) << (gpriv)->info->sh->cfm)
226 #define RCANFD_CFCC_CFDC(gpriv, x) (((x) & 0x7) << (gpriv)->info->sh->cfdc)
291 #define RCANFD_RFCC(gpriv, x) ((gpriv)->info->regs->rfcc + (0x04 * (x)))
297 /* Common FIFO Control registers */
301 ((gpriv)->info->regs->cfcc + (0x0c * (ch)) + (0x04 * (idx)))
304 ((gpriv)->info->regs->cfsts + (0x0c * (ch)) + (0x04 * (idx)))
307 ((gpriv)->info->regs->cfpctr + (0x0c * (ch)) + (0x04 * (idx)))
326 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
333 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
345 /* R-Car Gen4 Classical and CAN FD mode specific register map */
350 /* RSCFDnCFDCmXXX -> gpriv->fcbase[m].xxx */
363 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
364 #define RCANFD_F_RFOFFSET(gpriv) ((gpriv)->info->regs->rfoffset)
371 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
372 #define RCANFD_F_CFOFFSET(gpriv) ((gpriv)->info->regs->cfoffset)
388 #define RCANFD_FIFO_DEPTH 8 /* Tx FIFO depth */
394 #define RCANFD_CHANNEL_NUMRULES 1 /* only one rule per channel */
396 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
397 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
402 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
403 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
410 u16 rfcc; /* RX FIFO Configuration/Control Register */
411 u16 cfcc; /* Common FIFO Configuration/Control Register */
412 u16 cfsts; /* Common FIFO Status Register */
413 u16 cfpctr; /* Common FIFO Pointer Control Register */
414 u16 coffset; /* Channel Data Bitrate Configuration Register */
415 u16 rfoffset; /* Receive FIFO buffer access ID register */
416 u16 cfoffset; /* Transmit/receive FIFO buffer access ID register */
425 u8 cftml; /* Common FIFO TX Message Buffer Link */
426 u8 cfm; /* Common FIFO Mode */
427 u8 cfdc; /* Common FIFO Depth Configuration */
443 unsigned multi_channel_irqs:1; /* Has multiple channel irqs */
444 unsigned ch_interface_mode:1; /* Has channel interface mode */
449 /* Channel priv data */
459 u32 channel; /* Channel number */
726 u32 *data = (u32 *)cf->data;
729 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
731 data[i] = rcar_canfd_read(priv->base, off + i * sizeof(u32));
737 const u32 *data = (u32 *)cf->data;
740 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
742 rcar_canfd_write(priv->base, off + i * sizeof(u32), data[i]);
756 unsigned int rnc_stride = 32 / gpriv->info->rnc_field_width;
757 unsigned int shift = 32 - (ch % rnc_stride + 1) * gpriv->info->rnc_field_width;
761 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(w), rnc);
766 struct device *dev = &gpriv->pdev->dev;
773 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
781 rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
782 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
786 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
794 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
797 if (!gpriv->info->ch_interface_mode) {
798 if (gpriv->fdmode)
799 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
802 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
807 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
808 rcar_canfd_clear_bit(gpriv->base,
811 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
815 /* Ensure Channel reset mode */
816 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
820 dev_dbg(dev, "channel %u reset failed\n", ch);
825 if (gpriv->info->ch_interface_mode) {
827 if (!gpriv->fdmode) {
828 rcar_canfd_clear_bit_reg(&gpriv->fcbase[ch].cfdcfg,
830 rcar_canfd_set_bit_reg(&gpriv->fcbase[ch].cfdcfg,
833 rcar_canfd_clear_bit_reg(&gpriv->fcbase[ch].cfdcfg,
835 rcar_canfd_clear_bit_reg(&gpriv->fcbase[ch].cfdcfg,
853 if (gpriv->fdmode)
858 if (gpriv->extclk)
861 rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
863 /* Channel configuration settings */
864 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
865 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
867 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
882 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
886 /* Write number of rules for channel */
888 if (gpriv->info->shared_can_regs)
890 else if (gpriv->fdmode)
896 rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, rule_entry_index), 0);
898 rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, rule_entry_index), 0);
900 rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, rule_entry_index), 0);
901 /* Place the msg in corresponding Rx FIFO entry */
902 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, rule_entry_index),
906 rcar_canfd_clear_bit(gpriv->base,
912 /* Rx FIFO is used for reception */
916 /* Select Rx FIFO based on channel */
919 rfdc = 2; /* b010 - 8 messages Rx FIFO depth */
920 if (gpriv->fdmode)
921 rfpls = 7; /* b111 - Max 64 bytes payload */
923 rfpls = 0; /* b000 - Max 8 bytes payload */
927 rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
932 /* Tx/Rx(Common) FIFO configured in Tx mode is
935 * Each channel has 3 Common FIFO dedicated to them.
942 cfm = 1; /* b01 - Transmit mode */
943 cfdc = 2; /* b010 - 8 messages Tx FIFO depth */
944 if (gpriv->fdmode)
945 cfpls = 7; /* b111 - Max 64 bytes payload */
947 cfpls = 0; /* b000 - Max 8 bytes payload */
952 rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
954 if (gpriv->fdmode)
956 rcar_canfd_write(gpriv->base,
965 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
969 if (gpriv->fdmode)
972 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
979 rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
982 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
988 u32 ctr, ch = priv->channel;
991 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
993 /* Channel interrupts setup */
999 rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
1005 u32 ctr, ch = priv->channel;
1012 rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
1015 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
1021 struct rcar_canfd_global *gpriv = priv->gpriv;
1022 struct net_device_stats *stats = &ndev->stats;
1023 u32 ch = priv->channel;
1027 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1030 stats->tx_dropped++;
1033 sts = rcar_canfd_read(priv->base,
1037 stats->tx_dropped++;
1038 rcar_canfd_write(priv->base,
1043 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1046 stats->rx_dropped++;
1047 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1051 if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
1052 /* Message Lost flag will be set for respective channel
1062 rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
1069 struct net_device_stats *stats = &ndev->stats;
1072 u32 ch = priv->channel;
1079 stats->rx_dropped++;
1083 /* Channel error interrupts */
1086 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1087 cf->data[2] = CAN_ERR_PROT_UNSPEC;
1088 priv->can.can_stats.bus_error++;
1092 stats->tx_errors++;
1093 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1097 stats->tx_errors++;
1098 cf->data[2] |= CAN_ERR_PROT_BIT0;
1102 stats->tx_errors++;
1103 cf->data[2] |= CAN_ERR_PROT_BIT1;
1107 stats->rx_errors++;
1108 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1112 stats->tx_errors++;
1113 cf->can_id |= CAN_ERR_ACK;
1114 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1118 stats->rx_errors++;
1119 cf->data[2] |= CAN_ERR_PROT_FORM;
1123 stats->rx_errors++;
1124 cf->data[2] |= CAN_ERR_PROT_STUFF;
1128 priv->can.can_stats.arbitration_lost++;
1129 cf->can_id |= CAN_ERR_LOSTARB;
1130 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1134 stats->rx_errors++;
1135 cf->can_id |= CAN_ERR_BUSERROR;
1139 priv->can.state = CAN_STATE_ERROR_WARNING;
1140 priv->can.can_stats.error_warning++;
1141 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1142 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1144 cf->data[6] = txerr;
1145 cf->data[7] = rxerr;
1149 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1150 priv->can.can_stats.error_passive++;
1151 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1152 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1154 cf->data[6] = txerr;
1155 cf->data[7] = rxerr;
1158 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1160 priv->can.state = CAN_STATE_BUS_OFF;
1161 priv->can.can_stats.bus_off++;
1163 cf->can_id |= CAN_ERR_BUSOFF;
1168 stats->tx_errors++;
1169 cf->can_id |= CAN_ERR_PROT;
1170 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1173 /* Clear channel error interrupts that are handled */
1174 rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1182 struct rcar_canfd_global *gpriv = priv->gpriv;
1183 struct net_device_stats *stats = &ndev->stats;
1186 u32 ch = priv->channel;
1191 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1192 stats->tx_packets++;
1193 stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1195 spin_lock_irqsave(&priv->tx_lock, flags);
1196 priv->tx_tail++;
1197 sts = rcar_canfd_read(priv->base,
1205 if (priv->tx_head - priv->tx_tail <= unsent) {
1206 spin_unlock_irqrestore(&priv->tx_lock, flags);
1209 spin_unlock_irqrestore(&priv->tx_lock, flags);
1214 rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1220 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1221 struct net_device *ndev = priv->ndev;
1225 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1235 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1243 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1248 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1249 cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1252 if (napi_schedule_prep(&priv->napi)) {
1253 /* Disable Rx FIFO interrupts */
1254 rcar_canfd_clear_bit(priv->base,
1257 __napi_schedule(&priv->napi);
1267 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1279 * to a channel. RxFIFO interrupt is a global interrupt.
1281 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1292 struct net_device_stats *stats = &ndev->stats;
1293 enum can_state rx_state, tx_state, state = priv->can.state;
1303 if (state != priv->can.state) {
1305 state, priv->can.state, txerr, rxerr);
1308 stats->rx_dropped++;
1321 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1322 struct net_device *ndev = priv->ndev;
1326 sts = rcar_canfd_read(priv->base,
1336 rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1343 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1344 struct net_device *ndev = priv->ndev;
1348 /* Handle channel error interrupts */
1349 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1350 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1357 if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1358 priv->can.state != CAN_STATE_BUS_OFF))
1366 rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1376 /* Common FIFO is a per channel resource */
1377 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1388 struct rcar_canfd_global *gpriv = priv->gpriv;
1389 const struct rcar_canfd_hw_info *info = gpriv->info;
1392 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
1393 ntseg1 = (tseg1 & (info->nom_bittiming->tseg1_max - 1)) << info->sh->ntseg1;
1394 ntseg2 = (tseg2 & (info->nom_bittiming->tseg2_max - 1)) << info->sh->ntseg2;
1395 nsjw = (sjw & (info->nom_bittiming->sjw_max - 1)) << info->sh->nsjw;
1412 dtseg1 = (tseg1 & (info->data_bittiming->tseg1_max - 1)) << info->sh->dtseg1;
1413 dtseg2 = (tseg2 & (info->data_bittiming->tseg2_max - 1)) << info->sh->dtseg2;
1414 dsjw = (sjw & (info->data_bittiming->sjw_max - 1)) << 24;
1424 struct rcar_canfd_global *gpriv = priv->gpriv;
1425 const struct can_bittiming *bt = &priv->can.bittiming;
1426 const struct can_bittiming *dbt = &priv->can.fd.data_bittiming;
1427 const struct can_tdc_const *tdc_const = priv->can.fd.tdc_const;
1428 const struct can_tdc *tdc = &priv->can.fd.tdc;
1431 u32 ch = priv->channel;
1434 brp = bt->brp - 1;
1435 sjw = bt->sjw - 1;
1436 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1437 tseg2 = bt->phase_seg2 - 1;
1439 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1441 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
1445 brp = dbt->brp - 1;
1446 sjw = dbt->sjw - 1;
1447 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1448 tseg2 = dbt->phase_seg2 - 1;
1449 cfg = rcar_canfd_compute_data_bit_rate_cfg(gpriv->info, tseg1, tseg2, sjw, brp);
1450 writel(cfg, &gpriv->fcbase[ch].dcfg);
1453 if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_AUTO) {
1456 tdco = tdc->tdco - 1;
1457 } else if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_MANUAL) {
1460 tdco = min(tdc->tdcv + tdc->tdco, tdc_const->tdco_max) - 1;
1463 rcar_canfd_update_bit_reg(&gpriv->fcbase[ch].cfdcfg, mask,
1470 struct rcar_canfd_global *gpriv = priv->gpriv;
1471 int err = -EOPNOTSUPP;
1472 u32 sts, ch = priv->channel;
1479 /* Set channel to Operational mode */
1480 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1483 /* Verify channel mode change */
1484 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1487 netdev_err(ndev, "channel %u communication state failed\n", ch);
1491 /* Enable Common & Rx FIFO */
1492 rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1494 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1496 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1507 struct rcar_canfd_global *gpriv = priv->gpriv;
1510 err = phy_power_on(priv->transceiver);
1517 err = clk_prepare_enable(gpriv->can_clk);
1529 napi_enable(&priv->napi);
1536 napi_disable(&priv->napi);
1539 clk_disable_unprepare(gpriv->can_clk);
1541 phy_power_off(priv->transceiver);
1548 struct rcar_canfd_global *gpriv = priv->gpriv;
1550 u32 sts, ch = priv->channel;
1553 /* Transition to channel reset mode */
1554 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1557 /* Check Channel reset mode */
1558 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1561 netdev_err(ndev, "channel %u reset failed\n", ch);
1565 /* Disable Common & Rx FIFO */
1566 rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1568 rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1571 priv->can.state = CAN_STATE_STOPPED;
1577 struct rcar_canfd_global *gpriv = priv->gpriv;
1581 napi_disable(&priv->napi);
1583 clk_disable_unprepare(gpriv->can_clk);
1584 phy_power_off(priv->transceiver);
1592 struct rcar_canfd_global *gpriv = priv->gpriv;
1593 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1596 u32 ch = priv->channel;
1601 if (cf->can_id & CAN_EFF_FLAG) {
1602 id = cf->can_id & CAN_EFF_MASK;
1605 id = cf->can_id & CAN_SFF_MASK;
1608 if (cf->can_id & CAN_RTR_FLAG)
1611 dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1613 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
1614 rcar_canfd_write(priv->base,
1616 rcar_canfd_write(priv->base,
1622 if (cf->flags & CANFD_BRS)
1625 if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1629 rcar_canfd_write(priv->base,
1635 rcar_canfd_write(priv->base,
1637 rcar_canfd_write(priv->base,
1643 can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1645 spin_lock_irqsave(&priv->tx_lock, flags);
1646 priv->tx_head++;
1648 /* Stop the queue if we've filled all FIFO entries */
1649 if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1652 /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1653 * pointer for the Common FIFO
1655 rcar_canfd_write(priv->base,
1658 spin_unlock_irqrestore(&priv->tx_lock, flags);
1664 struct net_device *ndev = priv->ndev;
1665 struct net_device_stats *stats = &ndev->stats;
1666 struct rcar_canfd_global *gpriv = priv->gpriv;
1670 u32 ch = priv->channel;
1673 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
1674 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1675 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1677 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1679 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1685 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1686 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1691 stats->rx_dropped++;
1696 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1698 cf->can_id = id & CAN_SFF_MASK;
1700 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1702 cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1704 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1707 cf->flags |= CANFD_ESI;
1712 cf->can_id |= CAN_RTR_FLAG;
1715 cf->flags |= CANFD_BRS;
1720 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1722 cf->can_id |= CAN_RTR_FLAG;
1723 else if (gpriv->info->shared_can_regs)
1729 /* Write 0xff to RFPC to increment the CPU-side
1730 * pointer of the Rx FIFO
1732 rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1734 if (!(cf->can_id & CAN_RTR_FLAG))
1735 stats->rx_bytes += cf->len;
1736 stats->rx_packets++;
1744 struct rcar_canfd_global *gpriv = priv->gpriv;
1747 u32 ch = priv->channel;
1751 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1752 /* Check FIFO empty condition */
1760 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1767 /* Enable Rx FIFO interrupts */
1768 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1778 u32 sts = readl(&gpriv->fcbase[ch].cfdsts);
1781 return tdcr & (gpriv->info->tdc_const->tdcv_max - 1);
1787 u32 tdco = priv->can.fd.tdc.tdco;
1791 tdcr = rcar_canfd_get_tdcr(priv->gpriv, priv->channel) + 1;
1793 *tdcv = tdcr < tdco ? 0 : tdcr - tdco;
1810 return -EOPNOTSUPP;
1818 u32 val, ch = priv->channel;
1821 val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1822 bec->txerr = RCANFD_CSTS_TECCNT(val);
1823 bec->rxerr = RCANFD_CSTS_RECCNT(val);
1840 const struct rcar_canfd_hw_info *info = gpriv->info;
1841 struct platform_device *pdev = gpriv->pdev;
1842 struct device *dev = &pdev->dev;
1845 int err = -ENODEV;
1849 return -ENOMEM;
1853 ndev->netdev_ops = &rcar_canfd_netdev_ops;
1854 ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1855 ndev->flags |= IFF_ECHO;
1856 priv->ndev = ndev;
1857 priv->base = gpriv->base;
1858 priv->transceiver = transceiver;
1859 priv->channel = ch;
1860 priv->gpriv = gpriv;
1862 priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1863 priv->can.clock.freq = fcan_freq;
1864 dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1866 if (info->multi_channel_irqs) {
1889 err = -ENOMEM;
1903 err = -ENOMEM;
1916 if (gpriv->fdmode) {
1917 priv->can.bittiming_const = gpriv->info->nom_bittiming;
1918 priv->can.fd.data_bittiming_const = gpriv->info->data_bittiming;
1919 priv->can.fd.tdc_const = gpriv->info->tdc_const;
1926 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
1929 priv->can.fd.do_get_auto_tdcv = rcar_canfd_get_auto_tdcv;
1932 if (gpriv->info->shared_can_regs)
1933 priv->can.bittiming_const = gpriv->info->nom_bittiming;
1935 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1936 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1939 priv->can.do_set_mode = rcar_canfd_do_set_mode;
1940 priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1943 netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1945 spin_lock_init(&priv->tx_lock);
1946 gpriv->ch[priv->channel] = priv;
1952 dev_info(dev, "device registered (channel %u)\n", priv->channel);
1956 netif_napi_del(&priv->napi);
1964 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1967 unregister_candev(priv->ndev);
1968 netif_napi_del(&priv->napi);
1969 free_candev(priv->ndev);
1975 struct device *dev = &gpriv->pdev->dev;
1980 err = reset_control_reset(gpriv->rstc1);
1984 err = reset_control_reset(gpriv->rstc2);
1989 err = clk_prepare_enable(gpriv->clkp);
1997 err = clk_prepare_enable(gpriv->clk_ram);
2010 /* Controller in Global reset & Channel reset mode */
2013 /* Configure per channel attributes */
2014 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2015 /* Configure Channel's Rx fifo */
2018 /* Configure Channel's Tx (Common) fifo */
2030 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2034 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2046 clk_disable_unprepare(gpriv->clk_ram);
2048 clk_disable_unprepare(gpriv->clkp);
2050 reset_control_assert(gpriv->rstc2);
2052 reset_control_assert(gpriv->rstc1);
2064 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2067 clk_disable_unprepare(gpriv->clk_ram);
2068 clk_disable_unprepare(gpriv->clkp);
2069 reset_control_assert(gpriv->rstc2);
2070 reset_control_assert(gpriv->rstc1);
2077 struct device *dev = &pdev->dev;
2084 bool fdmode = true; /* CAN FD only mode - default */
2091 if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
2094 for (i = 0; i < info->max_channels; ++i) {
2096 of_child = of_get_available_child_by_name(dev->of_node, name);
2107 if (info->shared_global_irqs) {
2136 return -ENOMEM;
2138 gpriv->pdev = pdev;
2139 gpriv->channels_mask = channels_mask;
2140 gpriv->fdmode = fdmode;
2141 gpriv->info = info;
2143 gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
2144 if (IS_ERR(gpriv->rstc1))
2145 return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
2148 gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
2149 if (IS_ERR(gpriv->rstc2))
2150 return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
2154 gpriv->clkp = devm_clk_get(dev, "fck");
2155 if (IS_ERR(gpriv->clkp))
2156 return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
2162 gpriv->can_clk = devm_clk_get(dev, "can_clk");
2163 if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
2164 gpriv->can_clk = devm_clk_get(dev, "canfd");
2165 if (IS_ERR(gpriv->can_clk))
2166 return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
2170 fcan_freq = clk_get_rate(gpriv->can_clk) / info->postdiv;
2172 fcan_freq = clk_get_rate(gpriv->can_clk);
2173 gpriv->extclk = gpriv->info->external_clk;
2176 gpriv->clk_ram = devm_clk_get_optional(dev, "ram_clk");
2177 if (IS_ERR(gpriv->clk_ram))
2178 return dev_err_probe(dev, PTR_ERR(gpriv->clk_ram),
2186 gpriv->base = addr;
2187 gpriv->fcbase = addr + gpriv->info->regs->coffset;
2190 if (info->shared_global_irqs) {
2232 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2241 gpriv->extclk ? "ext" : "canfd",
2242 gpriv->fdmode ? "fd" : "classical");
2246 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2259 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2260 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2273 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2274 struct rcar_canfd_channel *priv = gpriv->ch[ch];
2275 struct net_device *ndev = priv->ndev;
2289 priv->can.state = CAN_STATE_SLEEPING;
2292 /* TODO Skip if wake-up (which is not yet supported) is enabled */
2310 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2311 struct rcar_canfd_channel *priv = gpriv->ch[ch];
2312 struct net_device *ndev = priv->ndev;
2334 { .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2335 { .compatible = "renesas,r9a09g047-canfd", .data = &r9a09g047_hw_info },
2336 { .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2337 { .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2338 { .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2358 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");