45 #define ISR					0x08  macro
254 	u32 isr, dma;  in tegra_nand_irq()  local
256 	isr = readl_relaxed(ctrl->regs + ISR);  in tegra_nand_irq()
258 	dev_dbg(ctrl->dev, "isr %08x\n", isr);  in tegra_nand_irq()
260 	if (!isr && !(dma & DMA_MST_CTRL_IS_DONE))  in tegra_nand_irq()
268 	if (isr & ISR_CORRFAIL_ERR)  in tegra_nand_irq()
271 	if (isr & ISR_CMD_DONE)  in tegra_nand_irq()
274 	if (isr & ISR_UND)  in tegra_nand_irq()
277 	if (isr & ISR_OVR)  in tegra_nand_irq()
287 	writel_relaxed(isr, ctrl->regs + ISR);  in tegra_nand_irq()
295 	"ISR",
330 	u32 isr, dma;  in tegra_nand_controller_abort()  local
339 	isr = readl_relaxed(ctrl->regs + ISR);  in tegra_nand_controller_abort()
340 	writel_relaxed(isr, ctrl->regs + ISR);  in tegra_nand_controller_abort()