Lines Matching full:ctrl
253 struct tegra_nand_controller *ctrl = data; in tegra_nand_irq() local
256 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_irq()
257 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
258 dev_dbg(ctrl->dev, "isr %08x\n", isr); in tegra_nand_irq()
269 ctrl->last_read_error = true; in tegra_nand_irq()
272 complete(&ctrl->command_complete); in tegra_nand_irq()
275 dev_err(ctrl->dev, "FIFO underrun\n"); in tegra_nand_irq()
278 dev_err(ctrl->dev, "FIFO overrun\n"); in tegra_nand_irq()
282 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
283 complete(&ctrl->dma_complete); in tegra_nand_irq()
287 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_irq()
311 static void tegra_nand_dump_reg(struct tegra_nand_controller *ctrl) in tegra_nand_dump_reg() argument
316 dev_err(ctrl->dev, "Tegra NAND controller register dump\n"); in tegra_nand_dump_reg()
323 reg = readl_relaxed(ctrl->regs + (i * 4)); in tegra_nand_dump_reg()
324 dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg); in tegra_nand_dump_reg()
328 static void tegra_nand_controller_abort(struct tegra_nand_controller *ctrl) in tegra_nand_controller_abort() argument
332 disable_irq(ctrl->irq); in tegra_nand_controller_abort()
335 writel_relaxed(0, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
336 writel_relaxed(0, ctrl->regs + COMMAND); in tegra_nand_controller_abort()
339 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_controller_abort()
340 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_controller_abort()
341 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
342 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
344 reinit_completion(&ctrl->command_complete); in tegra_nand_controller_abort()
345 reinit_completion(&ctrl->dma_complete); in tegra_nand_controller_abort()
347 enable_irq(ctrl->irq); in tegra_nand_controller_abort()
355 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_cmd() local
373 ctrl->regs + CMD_REG1); in tegra_nand_cmd()
377 ctrl->regs + CMD_REG2); in tegra_nand_cmd()
394 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_cmd()
395 writel_relaxed(addr2, ctrl->regs + ADDR_REG2); in tegra_nand_cmd()
416 writel_relaxed(reg, ctrl->regs + RESP); in tegra_nand_cmd()
425 cmd |= COMMAND_GO | COMMAND_CE(ctrl->cur_cs); in tegra_nand_cmd()
426 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_cmd()
427 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_cmd()
430 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_cmd()
431 tegra_nand_dump_reg(ctrl); in tegra_nand_cmd()
432 tegra_nand_controller_abort(ctrl); in tegra_nand_cmd()
437 reg = readl_relaxed(ctrl->regs + RESP); in tegra_nand_cmd()
464 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_select_target() local
466 ctrl->cur_cs = nand->cs[die_nr]; in tegra_nand_select_target()
480 static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl, in tegra_nand_hw_ecc() argument
486 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
488 writel_relaxed(0, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
491 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
493 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
500 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_page_xfer() local
509 writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
510 writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
512 writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
513 writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
522 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_page_xfer()
525 writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2); in tegra_nand_page_xfer()
532 dma_addr = dma_map_single(ctrl->dev, buf, mtd->writesize, dir); in tegra_nand_page_xfer()
533 ret = dma_mapping_error(ctrl->dev, dma_addr); in tegra_nand_page_xfer()
535 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
539 writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A); in tegra_nand_page_xfer()
540 writel_relaxed(dma_addr, ctrl->regs + DATA_PTR); in tegra_nand_page_xfer()
544 dma_addr_oob = dma_map_single(ctrl->dev, oob_buf, mtd->oobsize, in tegra_nand_page_xfer()
546 ret = dma_mapping_error(ctrl->dev, dma_addr_oob); in tegra_nand_page_xfer()
548 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
553 writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B); in tegra_nand_page_xfer()
554 writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR); in tegra_nand_page_xfer()
571 writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL); in tegra_nand_page_xfer()
574 COMMAND_CE(ctrl->cur_cs); in tegra_nand_page_xfer()
586 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_page_xfer()
588 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_page_xfer()
591 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_page_xfer()
592 tegra_nand_dump_reg(ctrl); in tegra_nand_page_xfer()
593 tegra_nand_controller_abort(ctrl); in tegra_nand_page_xfer()
598 ret = wait_for_completion_timeout(&ctrl->dma_complete, in tegra_nand_page_xfer()
601 dev_err(ctrl->dev, "DMA timeout\n"); in tegra_nand_page_xfer()
602 tegra_nand_dump_reg(ctrl); in tegra_nand_page_xfer()
603 tegra_nand_controller_abort(ctrl); in tegra_nand_page_xfer()
611 dma_unmap_single(ctrl->dev, dma_addr_oob, mtd->oobsize, dir); in tegra_nand_page_xfer()
614 dma_unmap_single(ctrl->dev, dma_addr, mtd->writesize, dir); in tegra_nand_page_xfer()
659 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_read_page_hwecc() local
666 tegra_nand_hw_ecc(ctrl, chip, true); in tegra_nand_read_page_hwecc()
668 tegra_nand_hw_ecc(ctrl, chip, false); in tegra_nand_read_page_hwecc()
673 if (!ctrl->last_read_error) in tegra_nand_read_page_hwecc()
685 ctrl->last_read_error = false; in tegra_nand_read_page_hwecc()
686 dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF); in tegra_nand_read_page_hwecc()
769 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_write_page_hwecc() local
773 tegra_nand_hw_ecc(ctrl, chip, true); in tegra_nand_write_page_hwecc()
776 tegra_nand_hw_ecc(ctrl, chip, false); in tegra_nand_write_page_hwecc()
781 static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl, in tegra_nand_setup_timing() argument
788 unsigned int rate = clk_get_rate(ctrl->clk) / 1000000; in tegra_nand_setup_timing()
811 writel_relaxed(reg, ctrl->regs + TIMING_1); in tegra_nand_setup_timing()
816 writel_relaxed(reg, ctrl->regs + TIMING_2); in tegra_nand_setup_timing()
822 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_setup_interface() local
832 tegra_nand_setup_timing(ctrl, timings); in tegra_nand_setup_interface()
916 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_attach_chip() local
931 dev_err(ctrl->dev, "Unsupported step size %d\n", in tegra_nand_attach_chip()
954 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n"); in tegra_nand_attach_chip()
961 dev_err(ctrl->dev, in tegra_nand_attach_chip()
990 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
1013 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
1019 dev_err(ctrl->dev, "ECC algorithm not supported\n"); in tegra_nand_attach_chip()
1023 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n", in tegra_nand_attach_chip()
1046 dev_err(ctrl->dev, "Unsupported writesize %d\n", in tegra_nand_attach_chip()
1056 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_attach_chip()
1068 struct tegra_nand_controller *ctrl) in tegra_nand_chips_init() argument
1114 chip->controller = &ctrl->controller; in tegra_nand_chips_init()
1141 ctrl->chip = chip; in tegra_nand_chips_init()
1149 struct tegra_nand_controller *ctrl; in tegra_nand_probe() local
1152 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); in tegra_nand_probe()
1153 if (!ctrl) in tegra_nand_probe()
1156 ctrl->dev = &pdev->dev; in tegra_nand_probe()
1157 platform_set_drvdata(pdev, ctrl); in tegra_nand_probe()
1158 nand_controller_init(&ctrl->controller); in tegra_nand_probe()
1159 ctrl->controller.ops = &tegra_nand_controller_ops; in tegra_nand_probe()
1161 ctrl->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_nand_probe()
1162 if (IS_ERR(ctrl->regs)) in tegra_nand_probe()
1163 return PTR_ERR(ctrl->regs); in tegra_nand_probe()
1169 ctrl->clk = devm_clk_get(&pdev->dev, "nand"); in tegra_nand_probe()
1170 if (IS_ERR(ctrl->clk)) in tegra_nand_probe()
1171 return PTR_ERR(ctrl->clk); in tegra_nand_probe()
1188 dev_err(ctrl->dev, "Failed to reset HW: %d\n", err); in tegra_nand_probe()
1192 writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD); in tegra_nand_probe()
1193 writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK); in tegra_nand_probe()
1194 writel_relaxed(INT_MASK, ctrl->regs + IER); in tegra_nand_probe()
1196 init_completion(&ctrl->command_complete); in tegra_nand_probe()
1197 init_completion(&ctrl->dma_complete); in tegra_nand_probe()
1199 ctrl->irq = platform_get_irq(pdev, 0); in tegra_nand_probe()
1200 if (ctrl->irq < 0) { in tegra_nand_probe()
1201 err = ctrl->irq; in tegra_nand_probe()
1204 err = devm_request_irq(&pdev->dev, ctrl->irq, tegra_nand_irq, 0, in tegra_nand_probe()
1205 dev_name(&pdev->dev), ctrl); in tegra_nand_probe()
1207 dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err); in tegra_nand_probe()
1211 writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL); in tegra_nand_probe()
1213 err = tegra_nand_chips_init(ctrl->dev, ctrl); in tegra_nand_probe()
1220 pm_runtime_put_sync_suspend(ctrl->dev); in tegra_nand_probe()
1221 pm_runtime_force_suspend(ctrl->dev); in tegra_nand_probe()
1229 struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev); in tegra_nand_remove() local
1230 struct nand_chip *chip = ctrl->chip; in tegra_nand_remove()
1237 pm_runtime_put_sync_suspend(ctrl->dev); in tegra_nand_remove()
1238 pm_runtime_force_suspend(ctrl->dev); in tegra_nand_remove()
1243 struct tegra_nand_controller *ctrl = dev_get_drvdata(dev); in tegra_nand_runtime_resume() local
1246 err = clk_prepare_enable(ctrl->clk); in tegra_nand_runtime_resume()
1257 struct tegra_nand_controller *ctrl = dev_get_drvdata(dev); in tegra_nand_runtime_suspend() local
1259 clk_disable_unprepare(ctrl->clk); in tegra_nand_runtime_suspend()