Lines Matching +full:nand +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
174 * @ecc_ctl: ECC_CTL register value for this NAND chip
181 * struct sunxi_nand_chip - stores NAND chip device related information
183 * @node: used to store NAND chips into a list
184 * @nand: base NAND chip structure
185 * @ecc: ECC controller structure
186 * @clk_rate: clk_rate required for this NAND chip
187 * @timing_cfg: TIMING_CFG register value for this NAND chip
188 * @timing_ctl: TIMING_CTL register value for this NAND chip
189 * @nsels: number of CS lines required by the NAND chip
194 struct nand_chip nand;
203 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
205 return container_of(nand, struct sunxi_nand_chip, nand);
209 * NAND Controller capabilities structure: stores NAND controller capabilities
224 * struct sunxi_nfc - stores sunxi NAND controller information
226 * @controller: base controller structure
228 * @regs: NAND controller registers
229 * @ahb_clk: NAND controller AHB clock
230 * @mod_clk: NAND controller mod clock
231 * @reset: NAND controller reset line
233 * @clk_rate: NAND controller current clock rate
234 * @chips: a list containing all the NAND chips attached to this NAND
235 * controller
236 * @complete: a completion object used to wait for NAND controller events
237 * @dmac: the DMA channel attached to the NAND controller
238 * @caps: NAND Controller capabilities
241 struct nand_controller controller;
257 return container_of(ctrl, struct sunxi_nfc, controller);
263 u32 st = readl(nfc->regs + NFC_REG_ST);
264 u32 ien = readl(nfc->regs + NFC_REG_INT);
270 complete(&nfc->complete);
272 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
273 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
284 return -EINVAL;
290 init_completion(&nfc->complete);
292 writel(events, nfc->regs + NFC_REG_INT);
294 ret = wait_for_completion_timeout(&nfc->complete,
297 ret = -ETIMEDOUT;
301 writel(0, nfc->regs + NFC_REG_INT);
305 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
310 writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
313 dev_err(nfc->dev, "wait interrupt timedout\n");
323 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
327 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
337 writel(0, nfc->regs + NFC_REG_ECC_CTL);
338 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
340 ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl,
344 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
365 ret = dma_map_sg(nfc->dev, sg, 1, ddir);
367 return -ENOMEM;
369 if (!nfc->caps->has_mdma) {
370 dmad = dmaengine_prep_slave_sg(nfc->dmac, sg, 1, tdir, DMA_CTRL_ACK);
372 ret = -EINVAL;
377 writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
378 nfc->regs + NFC_REG_CTL);
379 writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
380 writel(chunksize, nfc->regs + NFC_REG_CNT);
382 if (nfc->caps->has_mdma) {
383 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_DMA_TYPE_NORMAL,
384 nfc->regs + NFC_REG_CTL);
385 writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
386 writel(sg_dma_address(sg), nfc->regs + NFC_REG_MDMA_ADDR);
398 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
399 nfc->regs + NFC_REG_CTL);
402 dma_unmap_sg(nfc->dev, sg, 1, ddir);
410 dma_unmap_sg(nfc->dev, sg, 1, ddir);
411 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
412 nfc->regs + NFC_REG_CTL);
415 static void sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs)
417 struct mtd_info *mtd = nand_to_mtd(nand);
418 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
419 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
423 if (cs >= sunxi_nand->nsels)
426 ctl = readl(nfc->regs + NFC_REG_CTL) &
429 sel = &sunxi_nand->sels[cs];
430 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN | NFC_PAGE_SHIFT(nand->page_shift);
431 if (sel->rb >= 0)
432 ctl |= NFC_RB_SEL(sel->rb);
434 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
436 if (nfc->clk_rate != sunxi_nand->clk_rate) {
437 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
438 nfc->clk_rate = sunxi_nand->clk_rate;
441 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
442 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
443 writel(ctl, nfc->regs + NFC_REG_CTL);
446 static void sunxi_nfc_read_buf(struct nand_chip *nand, uint8_t *buf, int len)
448 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
449 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
458 cnt = min(len - offs, NFC_SRAM_SIZE);
464 writel(cnt, nfc->regs + NFC_REG_CNT);
466 writel(tmp, nfc->regs + NFC_REG_CMD);
477 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
483 static void sunxi_nfc_write_buf(struct nand_chip *nand, const uint8_t *buf,
486 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
487 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
496 cnt = min(len - offs, NFC_SRAM_SIZE);
502 writel(cnt, nfc->regs + NFC_REG_CNT);
503 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
506 writel(tmp, nfc->regs + NFC_REG_CMD);
595 while (count--)
602 static u16 sunxi_nfc_randomizer_state(struct nand_chip *nand, int page,
605 struct mtd_info *mtd = nand_to_mtd(nand);
607 int mod = mtd_div_by_ws(mtd->erasesize, mtd);
613 if (mtd->ecc_step_size == 512)
622 static void sunxi_nfc_randomizer_config(struct nand_chip *nand, int page,
625 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
626 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
629 if (!(nand->options & NAND_NEED_SCRAMBLING))
632 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
633 state = sunxi_nfc_randomizer_state(nand, page, ecc);
634 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
635 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
638 static void sunxi_nfc_randomizer_enable(struct nand_chip *nand)
640 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
642 if (!(nand->options & NAND_NEED_SCRAMBLING))
645 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
646 nfc->regs + NFC_REG_ECC_CTL);
649 static void sunxi_nfc_randomizer_disable(struct nand_chip *nand)
651 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
653 if (!(nand->options & NAND_NEED_SCRAMBLING))
656 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
657 nfc->regs + NFC_REG_ECC_CTL);
660 static void sunxi_nfc_randomize_bbm(struct nand_chip *nand, int page, u8 *bbm)
662 u16 state = sunxi_nfc_randomizer_state(nand, page, true);
668 static void sunxi_nfc_randomizer_write_buf(struct nand_chip *nand,
672 sunxi_nfc_randomizer_config(nand, page, ecc);
673 sunxi_nfc_randomizer_enable(nand);
674 sunxi_nfc_write_buf(nand, buf, len);
675 sunxi_nfc_randomizer_disable(nand);
678 static void sunxi_nfc_randomizer_read_buf(struct nand_chip *nand, uint8_t *buf,
681 sunxi_nfc_randomizer_config(nand, page, ecc);
682 sunxi_nfc_randomizer_enable(nand);
683 sunxi_nfc_read_buf(nand, buf, len);
684 sunxi_nfc_randomizer_disable(nand);
687 static void sunxi_nfc_hw_ecc_enable(struct nand_chip *nand)
689 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
690 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
692 writel(sunxi_nand->ecc.ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
695 static void sunxi_nfc_hw_ecc_disable(struct nand_chip *nand)
697 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
699 writel(0, nfc->regs + NFC_REG_ECC_CTL);
715 static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8 *oob,
718 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
720 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
723 /* De-randomize the Bad Block Marker. */
724 if (bbm && (nand->options & NAND_NEED_SCRAMBLING))
725 sunxi_nfc_randomize_bbm(nand, page, oob);
728 static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand,
732 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
736 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) {
738 sunxi_nfc_randomize_bbm(nand, page, user_data);
743 nfc->regs + NFC_REG_USER_DATA(step));
746 static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand,
749 struct mtd_info *mtd = nand_to_mtd(nand);
752 mtd->ecc_stats.failed++;
754 mtd->ecc_stats.corrected += ret;
759 static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *oob,
762 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
763 struct nand_ecc_ctrl *ecc = &nand->ecc;
769 return -EBADMSG;
774 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) {
782 memset(data, pattern, ecc->size);
785 memset(oob, pattern, ecc->bytes + 4);
790 tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step));
795 static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip *nand,
802 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
803 struct nand_ecc_ctrl *ecc = &nand->ecc;
809 nand_change_read_column_op(nand, data_off, NULL, 0, false);
811 sunxi_nfc_randomizer_read_buf(nand, NULL, ecc->size, false, page);
813 if (data_off + ecc->size != oob_off)
814 nand_change_read_column_op(nand, oob_off, NULL, 0, false);
820 sunxi_nfc_randomizer_config(nand, page, false);
821 sunxi_nfc_randomizer_enable(nand);
823 nfc->regs + NFC_REG_CMD);
826 sunxi_nfc_randomizer_disable(nand);
830 *cur_off = oob_off + ecc->bytes + 4;
832 ret = sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0,
833 readl(nfc->regs + NFC_REG_ECC_ST),
840 * Re-read the data with the randomizer disabled to identify
843 if (nand->options & NAND_NEED_SCRAMBLING)
844 nand_change_read_column_op(nand, data_off, data,
845 ecc->size, false);
847 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE,
848 ecc->size);
850 nand_change_read_column_op(nand, oob_off, oob, ecc->bytes + 4,
853 ret = nand_check_erased_ecc_chunk(data, ecc->size,
854 oob, ecc->bytes + 4,
855 NULL, 0, ecc->strength);
859 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
862 nand_change_read_column_op(nand, oob_off, NULL, 0,
864 sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + 4,
867 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0,
872 sunxi_nfc_hw_ecc_update_stats(nand, max_bitflips, ret);
877 static void sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip *nand,
881 struct mtd_info *mtd = nand_to_mtd(nand);
882 struct nand_ecc_ctrl *ecc = &nand->ecc;
883 int offset = ((ecc->bytes + 4) * ecc->steps);
884 int len = mtd->oobsize - offset;
890 nand_change_read_column_op(nand, mtd->writesize, NULL, 0,
894 sunxi_nfc_read_buf(nand, oob + offset, len);
896 sunxi_nfc_randomizer_read_buf(nand, oob + offset, len,
900 *cur_off = mtd->oobsize + mtd->writesize;
903 static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf,
907 bool randomized = nand->options & NAND_NEED_SCRAMBLING;
908 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
909 struct mtd_info *mtd = nand_to_mtd(nand);
910 struct nand_ecc_ctrl *ecc = &nand->ecc;
920 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks,
925 sunxi_nfc_hw_ecc_enable(nand);
926 sunxi_nfc_randomizer_config(nand, page, false);
927 sunxi_nfc_randomizer_enable(nand);
930 NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
934 if (nfc->caps->has_mdma)
937 dma_async_issue_pending(nfc->dmac);
940 nfc->regs + NFC_REG_CMD);
943 if (ret && !nfc->caps->has_mdma)
944 dmaengine_terminate_all(nfc->dmac);
946 sunxi_nfc_randomizer_disable(nand);
947 sunxi_nfc_hw_ecc_disable(nand);
954 status = readl(nfc->regs + NFC_REG_ECC_ST);
957 int data_off = i * ecc->size;
958 int oob_off = i * (ecc->bytes + 4);
960 u8 *oob = nand->oob_poi + oob_off;
963 ret = sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL,
973 nand_change_read_column_op(nand,
974 mtd->writesize + oob_off,
975 oob, ecc->bytes + 4, false);
977 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i,
984 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
989 int data_off = i * ecc->size;
990 int oob_off = i * (ecc->bytes + 4);
992 u8 *oob = nand->oob_poi + oob_off;
998 * Re-read the data with the randomizer disabled to
1003 nand_change_read_column_op(nand, data_off,
1004 data, ecc->size,
1008 nand_change_read_column_op(nand,
1009 mtd->writesize + oob_off,
1010 oob, ecc->bytes + 4, false);
1012 ret = nand_check_erased_ecc_chunk(data, ecc->size,
1013 oob, ecc->bytes + 4,
1015 ecc->strength);
1019 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
1024 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi,
1031 static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand,
1037 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1038 struct nand_ecc_ctrl *ecc = &nand->ecc;
1042 nand_change_write_column_op(nand, data_off, NULL, 0, false);
1044 sunxi_nfc_randomizer_write_buf(nand, data, ecc->size, false, page);
1046 if (data_off + ecc->size != oob_off)
1047 nand_change_write_column_op(nand, oob_off, NULL, 0, false);
1053 sunxi_nfc_randomizer_config(nand, page, false);
1054 sunxi_nfc_randomizer_enable(nand);
1055 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page);
1059 nfc->regs + NFC_REG_CMD);
1062 sunxi_nfc_randomizer_disable(nand);
1066 *cur_off = oob_off + ecc->bytes + 4;
1071 static void sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip *nand,
1075 struct mtd_info *mtd = nand_to_mtd(nand);
1076 struct nand_ecc_ctrl *ecc = &nand->ecc;
1077 int offset = ((ecc->bytes + 4) * ecc->steps);
1078 int len = mtd->oobsize - offset;
1084 nand_change_write_column_op(nand, offset + mtd->writesize,
1087 sunxi_nfc_randomizer_write_buf(nand, oob + offset, len, false, page);
1090 *cur_off = mtd->oobsize + mtd->writesize;
1093 static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *nand, uint8_t *buf,
1096 struct mtd_info *mtd = nand_to_mtd(nand);
1097 struct nand_ecc_ctrl *ecc = &nand->ecc;
1102 sunxi_nfc_select_chip(nand, nand->cur_cs);
1104 nand_read_page_op(nand, page, 0, NULL, 0);
1106 sunxi_nfc_hw_ecc_enable(nand);
1108 for (i = 0; i < ecc->steps; i++) {
1109 int data_off = i * ecc->size;
1110 int oob_off = i * (ecc->bytes + 4);
1112 u8 *oob = nand->oob_poi + oob_off;
1114 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, oob,
1115 oob_off + mtd->writesize,
1125 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi, &cur_off,
1128 sunxi_nfc_hw_ecc_disable(nand);
1133 static int sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip *nand, u8 *buf,
1138 sunxi_nfc_select_chip(nand, nand->cur_cs);
1140 nand_read_page_op(nand, page, 0, NULL, 0);
1142 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, oob_required, page,
1143 nand->ecc.steps);
1148 return sunxi_nfc_hw_ecc_read_page(nand, buf, oob_required, page);
1151 static int sunxi_nfc_hw_ecc_read_subpage(struct nand_chip *nand,
1155 struct mtd_info *mtd = nand_to_mtd(nand);
1156 struct nand_ecc_ctrl *ecc = &nand->ecc;
1160 sunxi_nfc_select_chip(nand, nand->cur_cs);
1162 nand_read_page_op(nand, page, 0, NULL, 0);
1164 sunxi_nfc_hw_ecc_enable(nand);
1166 for (i = data_offs / ecc->size;
1167 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1168 int data_off = i * ecc->size;
1169 int oob_off = i * (ecc->bytes + 4);
1171 u8 *oob = nand->oob_poi + oob_off;
1173 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off,
1175 oob_off + mtd->writesize,
1182 sunxi_nfc_hw_ecc_disable(nand);
1187 static int sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip *nand,
1191 int nchunks = DIV_ROUND_UP(data_offs + readlen, nand->ecc.size);
1194 sunxi_nfc_select_chip(nand, nand->cur_cs);
1196 nand_read_page_op(nand, page, 0, NULL, 0);
1198 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, false, page, nchunks);
1203 return sunxi_nfc_hw_ecc_read_subpage(nand, data_offs, readlen,
1207 static int sunxi_nfc_hw_ecc_write_page(struct nand_chip *nand,
1211 struct mtd_info *mtd = nand_to_mtd(nand);
1212 struct nand_ecc_ctrl *ecc = &nand->ecc;
1215 sunxi_nfc_select_chip(nand, nand->cur_cs);
1217 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1219 sunxi_nfc_hw_ecc_enable(nand);
1221 for (i = 0; i < ecc->steps; i++) {
1222 int data_off = i * ecc->size;
1223 int oob_off = i * (ecc->bytes + 4);
1225 const u8 *oob = nand->oob_poi + oob_off;
1227 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
1228 oob_off + mtd->writesize,
1234 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
1235 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
1238 sunxi_nfc_hw_ecc_disable(nand);
1240 return nand_prog_page_end_op(nand);
1243 static int sunxi_nfc_hw_ecc_write_subpage(struct nand_chip *nand,
1248 struct mtd_info *mtd = nand_to_mtd(nand);
1249 struct nand_ecc_ctrl *ecc = &nand->ecc;
1252 sunxi_nfc_select_chip(nand, nand->cur_cs);
1254 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1256 sunxi_nfc_hw_ecc_enable(nand);
1258 for (i = data_offs / ecc->size;
1259 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1260 int data_off = i * ecc->size;
1261 int oob_off = i * (ecc->bytes + 4);
1263 const u8 *oob = nand->oob_poi + oob_off;
1265 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
1266 oob_off + mtd->writesize,
1272 sunxi_nfc_hw_ecc_disable(nand);
1274 return nand_prog_page_end_op(nand);
1277 static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand,
1282 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1283 struct nand_ecc_ctrl *ecc = &nand->ecc;
1288 sunxi_nfc_select_chip(nand, nand->cur_cs);
1294 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps,
1299 for (i = 0; i < ecc->steps; i++) {
1300 const u8 *oob = nand->oob_poi + (i * (ecc->bytes + 4));
1302 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page);
1305 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1307 sunxi_nfc_hw_ecc_enable(nand);
1308 sunxi_nfc_randomizer_config(nand, page, false);
1309 sunxi_nfc_randomizer_enable(nand);
1312 nfc->regs + NFC_REG_WCMD_SET);
1316 if (nfc->caps->has_mdma)
1319 dma_async_issue_pending(nfc->dmac);
1323 nfc->regs + NFC_REG_CMD);
1326 if (ret && !nfc->caps->has_mdma)
1327 dmaengine_terminate_all(nfc->dmac);
1329 sunxi_nfc_randomizer_disable(nand);
1330 sunxi_nfc_hw_ecc_disable(nand);
1337 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
1339 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
1342 return nand_prog_page_end_op(nand);
1345 return sunxi_nfc_hw_ecc_write_page(nand, buf, oob_required, page);
1348 static int sunxi_nfc_hw_ecc_read_oob(struct nand_chip *nand, int page)
1350 u8 *buf = nand_get_data_buf(nand);
1352 return nand->ecc.read_page(nand, buf, 1, page);
1355 static int sunxi_nfc_hw_ecc_write_oob(struct nand_chip *nand, int page)
1357 struct mtd_info *mtd = nand_to_mtd(nand);
1358 u8 *buf = nand_get_data_buf(nand);
1361 memset(buf, 0xff, mtd->writesize);
1362 ret = nand->ecc.write_page(nand, buf, 1, page);
1367 return nand_prog_page_end_op(nand);
1385 return -EINVAL;
1391 static int sunxi_nfc_setup_interface(struct nand_chip *nand, int csline,
1394 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1395 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1403 return -ENOTSUPP;
1406 if (timings->tCLS_min > min_clk_period)
1407 min_clk_period = timings->tCLS_min;
1410 if (timings->tCLH_min > min_clk_period)
1411 min_clk_period = timings->tCLH_min;
1414 if (timings->tCS_min > min_clk_period)
1415 min_clk_period = timings->tCS_min;
1418 if (timings->tCH_min > min_clk_period)
1419 min_clk_period = timings->tCH_min;
1422 if (timings->tWP_min > min_clk_period)
1423 min_clk_period = timings->tWP_min;
1426 if (timings->tWH_min > min_clk_period)
1427 min_clk_period = timings->tWH_min;
1430 if (timings->tALS_min > min_clk_period)
1431 min_clk_period = timings->tALS_min;
1434 if (timings->tDS_min > min_clk_period)
1435 min_clk_period = timings->tDS_min;
1438 if (timings->tDH_min > min_clk_period)
1439 min_clk_period = timings->tDH_min;
1442 if (timings->tRR_min > (min_clk_period * 3))
1443 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1446 if (timings->tALH_min > min_clk_period)
1447 min_clk_period = timings->tALH_min;
1450 if (timings->tRP_min > min_clk_period)
1451 min_clk_period = timings->tRP_min;
1454 if (timings->tREH_min > min_clk_period)
1455 min_clk_period = timings->tREH_min;
1458 if (timings->tRC_min > (min_clk_period * 2))
1459 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1462 if (timings->tWC_min > (min_clk_period * 2))
1463 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1465 /* T16 - T19 + tCAD */
1466 if (timings->tWB_max > (min_clk_period * 20))
1467 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
1469 if (timings->tADL_min > (min_clk_period * 32))
1470 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
1472 if (timings->tWHR_min > (min_clk_period * 32))
1473 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
1475 if (timings->tRHW_min > (min_clk_period * 20))
1476 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
1479 * In non-EDO, tREA should be less than tRP to guarantee that the
1480 * controller does not sample the IO lines too early. Unfortunately,
1481 * the sunxi NAND controller does not allow us to have different
1487 * 2/ Use EDO mode (only works if timings->tRLOH > 0)
1489 if (timings->tREA_max > min_clk_period && !timings->tRLOH_min)
1490 min_clk_period = timings->tREA_max;
1492 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1495 dev_err(nfc->dev, "unsupported tWB\n");
1499 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1501 dev_err(nfc->dev, "unsupported tADL\n");
1502 return -EINVAL;
1505 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1507 dev_err(nfc->dev, "unsupported tWHR\n");
1508 return -EINVAL;
1511 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1514 dev_err(nfc->dev, "unsupported tRHW\n");
1522 * TODO: according to ONFI specs this value only applies for DDR NAND,
1528 sunxi_nand->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1539 sunxi_nand->clk_rate = NSEC_PER_SEC / min_clk_period;
1540 real_clk_rate = clk_round_rate(nfc->mod_clk, sunxi_nand->clk_rate);
1542 dev_err(nfc->dev, "Unable to round clk %lu\n",
1543 sunxi_nand->clk_rate);
1544 return -EINVAL;
1547 sunxi_nand->timing_ctl = 0;
1555 if (min_clk_period * 2 < 30 || min_clk_period * 1000 < timings->tREA_max)
1556 sunxi_nand->timing_ctl = NFC_TIMING_CTL_EDO;
1564 struct nand_chip *nand = mtd_to_nand(mtd);
1565 struct nand_ecc_ctrl *ecc = &nand->ecc;
1567 if (section >= ecc->steps)
1568 return -ERANGE;
1570 oobregion->offset = section * (ecc->bytes + 4) + 4;
1571 oobregion->length = ecc->bytes;
1579 struct nand_chip *nand = mtd_to_nand(mtd);
1580 struct nand_ecc_ctrl *ecc = &nand->ecc;
1582 if (section > ecc->steps)
1583 return -ERANGE;
1590 if (!section && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1591 oobregion->offset = 2;
1592 oobregion->length = 2;
1598 * The controller does not provide access to OOB bytes
1601 if (section == ecc->steps && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1602 return -ERANGE;
1604 oobregion->offset = section * (ecc->bytes + 4);
1606 if (section < ecc->steps)
1607 oobregion->length = 4;
1609 oobregion->length = mtd->oobsize - oobregion->offset;
1619 static int sunxi_nand_hw_ecc_ctrl_init(struct nand_chip *nand,
1624 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1625 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1626 struct mtd_info *mtd = nand_to_mtd(nand);
1631 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) {
1634 ecc->size = 1024;
1635 nsectors = mtd->writesize / ecc->size;
1638 bytes = (mtd->oobsize - 2) / nsectors;
1640 /* 4 non-ECC bytes are added before each ECC bytes section */
1641 bytes -= 4;
1645 bytes--;
1647 ecc->strength = bytes * 8 / fls(8 * ecc->size);
1650 if (strengths[i] > ecc->strength)
1655 ecc->strength = 0;
1657 ecc->strength = strengths[i - 1];
1660 if (ecc->size != 512 && ecc->size != 1024)
1661 return -EINVAL;
1664 if (ecc->size == 512 && mtd->writesize > 512) {
1665 ecc->size = 1024;
1666 ecc->strength *= 2;
1671 if (ecc->strength <= strengths[i]) {
1673 * Update ecc->strength value with the actual strength
1676 ecc->strength = strengths[i];
1682 dev_err(nfc->dev, "unsupported strength\n");
1683 return -ENOTSUPP;
1687 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1690 ecc->bytes = ALIGN(ecc->bytes, 2);
1692 nsectors = mtd->writesize / ecc->size;
1694 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors))
1695 return -EINVAL;
1697 ecc->read_oob = sunxi_nfc_hw_ecc_read_oob;
1698 ecc->write_oob = sunxi_nfc_hw_ecc_write_oob;
1701 if (nfc->dmac || nfc->caps->has_mdma) {
1702 ecc->read_page = sunxi_nfc_hw_ecc_read_page_dma;
1703 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage_dma;
1704 ecc->write_page = sunxi_nfc_hw_ecc_write_page_dma;
1705 nand->options |= NAND_USES_DMA;
1707 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1708 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1709 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1713 ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1714 ecc->read_oob_raw = nand_read_oob_std;
1715 ecc->write_oob_raw = nand_write_oob_std;
1717 sunxi_nand->ecc.ecc_ctl = NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION |
1720 if (ecc->size == 512)
1721 sunxi_nand->ecc.ecc_ctl |= NFC_ECC_BLOCK_512;
1726 static int sunxi_nand_attach_chip(struct nand_chip *nand)
1729 nanddev_get_ecc_requirements(&nand->base);
1730 struct nand_ecc_ctrl *ecc = &nand->ecc;
1731 struct device_node *np = nand_get_flash_node(nand);
1734 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1735 nand->bbt_options |= NAND_BBT_NO_OOB;
1737 if (nand->options & NAND_NEED_SCRAMBLING)
1738 nand->options |= NAND_NO_SUBPAGE_WRITE;
1740 nand->options |= NAND_SUBPAGE_READ;
1742 if (!ecc->size) {
1743 ecc->size = requirements->step_size;
1744 ecc->strength = requirements->strength;
1747 if (!ecc->size || !ecc->strength)
1748 return -EINVAL;
1750 switch (ecc->engine_type) {
1752 ret = sunxi_nand_hw_ecc_ctrl_init(nand, ecc, np);
1760 return -EINVAL;
1766 static int sunxi_nfc_exec_subop(struct nand_chip *nand,
1769 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1775 for (i = 0; i < subop->ninstrs; i++) {
1776 const struct nand_op_instr *instr = &subop->instrs[i];
1778 switch (instr->type) {
1782 return -EINVAL;
1785 extcmd |= instr->ctx.cmd.opcode;
1788 NFC_CMD(instr->ctx.cmd.opcode);
1796 u32 addr = instr->ctx.addr.addrs[j + start];
1813 if (instr->type == NAND_OP_DATA_OUT_INSTR) {
1815 memcpy_toio(nfc->regs + NFC_RAM0_BASE,
1816 instr->ctx.data.buf.out + start,
1819 inbuf = instr->ctx.data.buf.in + start;
1835 writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW);
1836 writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH);
1841 nfc->regs +
1846 writel(cnt, nfc->regs + NFC_REG_CNT);
1848 writel(cmd, nfc->regs + NFC_REG_CMD);
1857 memcpy_fromio(inbuf, nfc->regs + NFC_RAM0_BASE, cnt);
1862 static int sunxi_nfc_soft_waitrdy(struct nand_chip *nand,
1865 return nand_soft_waitrdy(nand,
1866 subop->instrs[0].ctx.waitrdy.timeout_ms);
1899 static int sunxi_nfc_exec_op(struct nand_chip *nand,
1902 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1906 sunxi_nfc_select_chip(nand, op->cs);
1908 if (sunxi_nand->sels[op->cs].rb >= 0)
1913 return nand_op_parser_exec_op(nand, parser, op, check_only);
1928 while (!list_empty(&nfc->chips)) {
1929 sunxi_nand = list_first_entry(&nfc->chips,
1932 chip = &sunxi_nand->nand;
1936 list_del(&sunxi_nand->node);
1945 struct nand_chip *nand;
1952 return -EINVAL;
1957 return -EINVAL;
1963 return -ENOMEM;
1965 sunxi_nand->nsels = nsels;
1979 return -EINVAL;
1982 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1984 return -EINVAL;
1987 sunxi_nand->sels[i].cs = tmp;
1991 sunxi_nand->sels[i].rb = tmp;
1993 sunxi_nand->sels[i].rb = -1;
1996 nand = &sunxi_nand->nand;
1998 nand->controller = &nfc->controller;
1999 nand->controller->ops = &sunxi_nand_controller_ops;
2005 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2006 nand_set_flash_node(nand, np);
2008 mtd = nand_to_mtd(nand);
2009 mtd->dev.parent = dev;
2011 ret = nand_scan(nand, nsels);
2018 nand_cleanup(nand);
2022 list_add_tail(&sunxi_nand->node, &nfc->chips);
2029 struct device_node *np = dev->of_node;
2047 if (nfc->caps->has_mdma)
2050 nfc->dmac = dma_request_chan(nfc->dev, "rxtx");
2051 if (IS_ERR(nfc->dmac)) {
2052 ret = PTR_ERR(nfc->dmac);
2053 if (ret == -EPROBE_DEFER)
2057 dev_warn(nfc->dev, "failed to request rxtx DMA channel: %d\n", ret);
2058 nfc->dmac = NULL;
2062 dmac_cfg.src_addr = r->start + nfc->caps->reg_io_data;
2066 dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
2067 dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
2068 dmaengine_slave_config(nfc->dmac, &dmac_cfg);
2075 struct device *dev = &pdev->dev;
2083 return -ENOMEM;
2085 nfc->dev = dev;
2086 nand_controller_init(&nfc->controller);
2087 INIT_LIST_HEAD(&nfc->chips);
2089 nfc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
2090 if (IS_ERR(nfc->regs))
2091 return PTR_ERR(nfc->regs);
2097 nfc->ahb_clk = devm_clk_get_enabled(dev, "ahb");
2098 if (IS_ERR(nfc->ahb_clk)) {
2100 return PTR_ERR(nfc->ahb_clk);
2103 nfc->mod_clk = devm_clk_get_enabled(dev, "mod");
2104 if (IS_ERR(nfc->mod_clk)) {
2106 return PTR_ERR(nfc->mod_clk);
2109 nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
2110 if (IS_ERR(nfc->reset))
2111 return PTR_ERR(nfc->reset);
2113 ret = reset_control_deassert(nfc->reset);
2119 nfc->caps = of_device_get_match_data(&pdev->dev);
2120 if (!nfc->caps) {
2121 ret = -EINVAL;
2129 writel(0, nfc->regs + NFC_REG_INT);
2131 0, "sunxi-nand", nfc);
2144 dev_err(dev, "failed to init nand chips\n");
2151 if (nfc->dmac)
2152 dma_release_channel(nfc->dmac);
2154 reset_control_assert(nfc->reset);
2165 reset_control_assert(nfc->reset);
2167 if (nfc->dmac)
2168 dma_release_channel(nfc->dmac);
2184 .compatible = "allwinner,sun4i-a10-nand",
2188 .compatible = "allwinner,sun8i-a23-nand-controller",
2207 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");