Lines Matching refs:TO_CYCLES64
191 #define TO_CYCLES64(ps, period_ns) ((unsigned int)DIV_ROUND_UP_ULL(div_u64(ps, 1000), \
917 TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) |
918 TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns));
920 TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) |
921 TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) |
922 TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) |
923 TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns));
925 TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) |
926 TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) |
927 TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns));
942 TIM_GEN_SEQ0_D0(TO_CYCLES64(cle - cyc, period_ns)) |
943 TIM_GEN_SEQ0_D1(TO_CYCLES64(cle - cyc, period_ns)) |
944 TIM_GEN_SEQ0_D2(TO_CYCLES64(bef_dly, period_ns)) |
945 TIM_GEN_SEQ0_D3(TO_CYCLES64(ca_to_data, period_ns));
954 TIM_GEN_SEQ1_D4(TO_CYCLES64(ale - cyc, period_ns)) |
955 TIM_GEN_SEQ1_D5(TO_CYCLES64(ale - cyc, period_ns)) |
956 TIM_GEN_SEQ1_D6(TO_CYCLES64(bef_dly, period_ns)) |
957 TIM_GEN_SEQ1_D7(TO_CYCLES64(ca_to_data, period_ns));
966 TIM_GEN_SEQ2_D8(TO_CYCLES64(sdr->tRR_min + sdr->tREA_max, period_ns)) |
967 TIM_GEN_SEQ2_D9(TO_CYCLES64(sdr->tRR_min, period_ns)) |
968 TIM_GEN_SEQ2_D10(TO_CYCLES64(cle - cyc, period_ns)) |
969 TIM_GEN_SEQ2_D11(TO_CYCLES64(bef_dly, period_ns));
973 TIM_GEN_SEQ3_D12(TO_CYCLES64(sdr->tCLH_min - sdr->tDH_min, period_ns));