Lines Matching +full:rzn1 +full:- +full:nandc
1 // SPDX-License-Identifier: GPL-2.0
3 * Evatronix/Renesas R-Car Gen3, RZ/N1D, RZ/N1S, RZ/N1L NAND controller driver
11 #include <linux/dma-mapping.h>
121 #define TIMINGS_ASYN_TRWP(x) FIELD_PREP(GENMASK(3, 0), max((x), 1U) - 1)
122 #define TIMINGS_ASYN_TRWH(x) FIELD_PREP(GENMASK(7, 4), max((x), 1U) - 1)
125 #define TIM_SEQ0_TCCS(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)
126 #define TIM_SEQ0_TADL(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)
127 #define TIM_SEQ0_TRHW(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)
128 #define TIM_SEQ0_TWHR(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)
131 #define TIM_SEQ1_TWB(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)
132 #define TIM_SEQ1_TRR(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)
133 #define TIM_SEQ1_TWW(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)
136 #define TIM_GEN_SEQ0_D0(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)
137 #define TIM_GEN_SEQ0_D1(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)
138 #define TIM_GEN_SEQ0_D2(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)
139 #define TIM_GEN_SEQ0_D3(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)
142 #define TIM_GEN_SEQ1_D4(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)
143 #define TIM_GEN_SEQ1_D5(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)
144 #define TIM_GEN_SEQ1_D6(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)
145 #define TIM_GEN_SEQ1_D7(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)
148 #define TIM_GEN_SEQ2_D8(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)
149 #define TIM_GEN_SEQ2_D9(x) FIELD_PREP(GENMASK(13, 8), max((x), 1U) - 1)
150 #define TIM_GEN_SEQ2_D10(x) FIELD_PREP(GENMASK(21, 16), max((x), 1U) - 1)
151 #define TIM_GEN_SEQ2_D11(x) FIELD_PREP(GENMASK(29, 24), max((x), 1U) - 1)
184 #define TIM_GEN_SEQ3_D12(x) FIELD_PREP(GENMASK(5, 0), max((x), 1U) - 1)
256 return nand->sels[nand->selected_die].cs;
263 control = readl_relaxed(rnandc->regs + CONTROL_REG);
265 writel_relaxed(control, rnandc->regs + CONTROL_REG);
272 control = readl_relaxed(rnandc->regs + CONTROL_REG);
274 writel_relaxed(control, rnandc->regs + CONTROL_REG);
279 writel_relaxed(0, rnandc->regs + INT_STATUS_REG);
280 writel_relaxed(0, rnandc->regs + ECC_STAT_REG);
281 writel_relaxed(0, rnandc->regs + ECC_CNT_REG);
286 writel_relaxed(0, rnandc->regs + INT_MASK_REG);
291 if (!rnandc->use_polling)
292 writel_relaxed(val, rnandc->regs + INT_MASK_REG);
297 writel_relaxed(FIFO_INIT, rnandc->regs + FIFO_INIT_REG);
303 struct rnandc *rnandc = to_rnandc(chip->controller);
304 unsigned int cs = rnand->sels[die_nr].cs;
306 if (chip == rnandc->selected_chip && die_nr == rnand->selected_die)
310 writel_relaxed(MEM_CTRL_CS(cs) | MEM_CTRL_DIS_WP(cs), rnandc->regs + MEM_CTRL_REG);
311 writel_relaxed(rnand->control, rnandc->regs + CONTROL_REG);
312 writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG);
313 writel_relaxed(rnand->timings_asyn, rnandc->regs + TIMINGS_ASYN_REG);
314 writel_relaxed(rnand->tim_seq0, rnandc->regs + TIM_SEQ0_REG);
315 writel_relaxed(rnand->tim_seq1, rnandc->regs + TIM_SEQ1_REG);
316 writel_relaxed(rnand->tim_gen_seq0, rnandc->regs + TIM_GEN_SEQ0_REG);
317 writel_relaxed(rnand->tim_gen_seq1, rnandc->regs + TIM_GEN_SEQ1_REG);
318 writel_relaxed(rnand->tim_gen_seq2, rnandc->regs + TIM_GEN_SEQ2_REG);
319 writel_relaxed(rnand->tim_gen_seq3, rnandc->regs + TIM_GEN_SEQ3_REG);
321 rnandc->selected_chip = chip;
322 rnand->selected_die = die_nr;
327 writel_relaxed(rop->addr0_col, rnandc->regs + ADDR0_COL_REG);
328 writel_relaxed(rop->addr0_row, rnandc->regs + ADDR0_ROW_REG);
329 writel_relaxed(rop->addr1_col, rnandc->regs + ADDR1_COL_REG);
330 writel_relaxed(rop->addr1_row, rnandc->regs + ADDR1_ROW_REG);
331 writel_relaxed(rop->ecc_offset, rnandc->regs + ECC_OFFSET_REG);
332 writel_relaxed(rop->gen_seq_ctrl, rnandc->regs + GEN_SEQ_CTRL_REG);
333 writel_relaxed(DATA_SIZE(rop->len), rnandc->regs + DATA_SIZE_REG);
334 writel_relaxed(rop->command, rnandc->regs + COMMAND_REG);
341 DMA_CTRL_START, rnandc->regs + DMA_CTRL_REG);
349 complete(&rnandc->complete);
362 ret = readl_poll_timeout(rnandc->regs + STATUS_REG, status,
366 dev_err(rnandc->dev, "Operation timed out, status: 0x%08x\n",
378 if (rnandc->use_polling) {
383 ret = readl_poll_timeout(rnandc->regs + INT_STATUS_REG, status,
388 ret = wait_for_completion_timeout(&rnandc->complete,
391 ret = -ETIMEDOUT;
402 struct rnandc *rnandc = to_rnandc(chip->controller);
411 .len = mtd->writesize,
412 .ecc_offset = ECC_OFFSET(mtd->writesize + 2),
420 rnandc_select_target(chip, chip->cur_cs);
422 reinit_completion(&rnandc->complete);
427 dma_addr = dma_map_single(rnandc->dev, rnandc->buf, mtd->writesize,
429 if (dma_mapping_error(rnandc->dev, dma_addr))
430 return -ENOMEM;
432 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
433 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
434 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
440 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_FROM_DEVICE);
443 dev_err(rnandc->dev, "Read page operation never ending\n");
447 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG);
450 ret = nand_change_read_column_op(chip, mtd->writesize,
451 chip->oob_poi, mtd->oobsize,
458 for (i = 0; i < chip->ecc.steps; i++) {
459 unsigned int off = i * chip->ecc.size;
460 unsigned int eccoff = i * chip->ecc.bytes;
462 bf = nand_check_erased_ecc_chunk(rnandc->buf + off,
463 chip->ecc.size,
464 chip->oob_poi + 2 + eccoff,
465 chip->ecc.bytes,
467 chip->ecc.strength);
469 mtd->ecc_stats.failed++;
471 mtd->ecc_stats.corrected += bf;
476 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG));
479 * that this controller does not provide per-chunk details but
482 mtd->ecc_stats.corrected += bf;
485 memcpy(buf, rnandc->buf, mtd->writesize);
493 struct rnandc *rnandc = to_rnandc(chip->controller);
497 unsigned int page_off = round_down(req_offset, chip->ecc.size);
498 unsigned int real_len = round_up(req_offset + req_len - page_off,
499 chip->ecc.size);
500 unsigned int start_chunk = page_off / chip->ecc.size;
501 unsigned int nchunks = real_len / chip->ecc.size;
502 unsigned int ecc_off = 2 + (start_chunk * chip->ecc.bytes);
510 .ecc_offset = ECC_OFFSET(mtd->writesize + ecc_off),
517 rnandc_select_target(chip, chip->cur_cs);
522 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
525 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
528 ioread32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off,
531 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) {
532 dev_err(rnandc->dev, "Clearing residual data in the read FIFO\n");
539 dev_err(rnandc->dev, "Read subpage operation never ending\n");
543 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG);
546 ret = nand_change_read_column_op(chip, mtd->writesize,
547 chip->oob_poi, mtd->oobsize,
553 unsigned int dataoff = i * chip->ecc.size;
554 unsigned int eccoff = 2 + (i * chip->ecc.bytes);
557 chip->ecc.size,
558 chip->oob_poi + eccoff,
559 chip->ecc.bytes,
561 chip->ecc.strength);
563 mtd->ecc_stats.failed++;
565 mtd->ecc_stats.corrected += bf;
570 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG));
573 * that this controller does not provide per-chunk details but
576 mtd->ecc_stats.corrected += bf;
585 struct rnandc *rnandc = to_rnandc(chip->controller);
594 .len = mtd->writesize,
595 .ecc_offset = ECC_OFFSET(mtd->writesize + 2),
600 memcpy(rnandc->buf, buf, mtd->writesize);
603 rnandc_select_target(chip, chip->cur_cs);
605 reinit_completion(&rnandc->complete);
610 dma_addr = dma_map_single(rnandc->dev, (void *)rnandc->buf, mtd->writesize,
612 if (dma_mapping_error(rnandc->dev, dma_addr))
613 return -ENOMEM;
615 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
616 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
617 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
623 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_TO_DEVICE);
626 dev_err(rnandc->dev, "Write page operation never ending\n");
633 return nand_change_write_column_op(chip, mtd->writesize, chip->oob_poi,
634 mtd->oobsize, false);
641 struct rnandc *rnandc = to_rnandc(chip->controller);
643 unsigned int page_off = round_down(req_offset, chip->ecc.size);
644 unsigned int real_len = round_up(req_offset + req_len - page_off,
645 chip->ecc.size);
646 unsigned int start_chunk = page_off / chip->ecc.size;
647 unsigned int ecc_off = 2 + (start_chunk * chip->ecc.bytes);
655 .ecc_offset = ECC_OFFSET(mtd->writesize + ecc_off),
660 rnandc_select_target(chip, chip->cur_cs);
665 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG)))
668 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off,
671 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
677 dev_err(rnandc->dev, "Write subpage operation never ending\n");
691 struct rnandc *rnandc = to_rnandc(chip->controller);
705 rnandc_select_target(chip, op->cs);
707 for (op_id = 0; op_id < op->ninstrs; op_id++) {
708 instr = &op->instrs[op_id];
712 switch (instr->type) {
716 rop.command |= COMMAND_0(instr->ctx.cmd.opcode);
720 rop.gen_seq_ctrl |= GEN_SEQ_COMMAND_3(instr->ctx.cmd.opcode);
726 rop.command |= COMMAND_2(instr->ctx.cmd.opcode);
732 rop.command |= COMMAND_1(instr->ctx.cmd.opcode);
742 return -EOPNOTSUPP;
747 addrs = instr->ctx.addr.addrs;
748 naddrs = instr->ctx.addr.naddrs;
750 return -EOPNOTSUPP;
753 row_addrs = naddrs > 2 ? naddrs - col_addrs : 0;
781 return -EOPNOTSUPP;
790 rop.buf = instr->ctx.data.buf.in;
791 rop.len = instr->ctx.data.len;
804 return -EOPNOTSUPP;
825 return -EOPNOTSUPP;
841 dev_err(rnandc->dev, "Cannot handle more than one wait delay\n");
842 return -EOPNOTSUPP;
853 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
856 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
859 ioread32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf, words);
861 last_bytes = readl_relaxed(rnandc->regs + FIFO_DATA_REG);
866 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) {
867 dev_warn(rnandc->dev,
872 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG)))
875 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf,
881 writel_relaxed(last_bytes, rnandc->regs + FIFO_DATA_REG);
884 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG)))
899 struct rnandc *rnandc = to_rnandc(chip->controller);
900 unsigned int period_ns = 1000000000 / rnandc->ext_clk_rate;
908 if (sdr->tRP_min != sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) {
909 dev_err(rnandc->dev, "Read and write hold times must be identical\n");
910 return -EINVAL;
916 rnand->timings_asyn =
917 TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) |
918 TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns));
919 rnand->tim_seq0 =
920 TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) |
921 TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) |
922 TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) |
923 TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns));
924 rnand->tim_seq1 =
925 TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) |
926 TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) |
927 TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns));
929 cyc = sdr->tDS_min + sdr->tDH_min;
930 cle = sdr->tCLH_min + sdr->tCLS_min;
931 ale = sdr->tALH_min + sdr->tALS_min;
932 bef_dly = sdr->tWB_max - sdr->tDH_min;
933 ca_to_data = sdr->tWHR_min + sdr->tREA_max - sdr->tDH_min;
936 * D0 = CMD -> ADDR = tCLH + tCLS - 1 cycle
937 * D1 = CMD -> CMD = tCLH + tCLS - 1 cycle
938 * D2 = CMD -> DLY = tWB - tDH
939 * D3 = CMD -> DATA = tWHR + tREA - tDH
941 rnand->tim_gen_seq0 =
942 TIM_GEN_SEQ0_D0(TO_CYCLES64(cle - cyc, period_ns)) |
943 TIM_GEN_SEQ0_D1(TO_CYCLES64(cle - cyc, period_ns)) |
948 * D4 = ADDR -> CMD = tALH + tALS - 1 cyle
949 * D5 = ADDR -> ADDR = tALH + tALS - 1 cyle
950 * D6 = ADDR -> DLY = tWB - tDH
951 * D7 = ADDR -> DATA = tWHR + tREA - tDH
953 rnand->tim_gen_seq1 =
954 TIM_GEN_SEQ1_D4(TO_CYCLES64(ale - cyc, period_ns)) |
955 TIM_GEN_SEQ1_D5(TO_CYCLES64(ale - cyc, period_ns)) |
960 * D8 = DLY -> DATA = tRR + tREA
961 * D9 = DLY -> CMD = tRR
962 * D10 = DATA -> CMD = tCLH + tCLS - 1 cycle
963 * D11 = DATA -> DLY = tWB - tDH
965 rnand->tim_gen_seq2 =
966 TIM_GEN_SEQ2_D8(TO_CYCLES64(sdr->tRR_min + sdr->tREA_max, period_ns)) |
967 TIM_GEN_SEQ2_D9(TO_CYCLES64(sdr->tRR_min, period_ns)) |
968 TIM_GEN_SEQ2_D10(TO_CYCLES64(cle - cyc, period_ns)) |
971 /* D12 = DATA -> END = tCLH - tDH */
972 rnand->tim_gen_seq3 =
973 TIM_GEN_SEQ3_D12(TO_CYCLES64(sdr->tCLH_min - sdr->tDH_min, period_ns));
982 unsigned int eccbytes = round_up(chip->ecc.bytes, 4) * chip->ecc.steps;
985 return -ERANGE;
987 oobregion->offset = 2;
988 oobregion->length = eccbytes;
997 unsigned int eccbytes = round_up(chip->ecc.bytes, 4) * chip->ecc.steps;
1000 return -ERANGE;
1002 oobregion->offset = 2 + eccbytes;
1003 oobregion->length = mtd->oobsize - oobregion->offset;
1017 struct rnandc *rnandc = to_rnandc(chip->controller);
1019 if (mtd->writesize > SZ_16K) {
1020 dev_err(rnandc->dev, "Unsupported page size\n");
1021 return -EINVAL;
1024 switch (chip->ecc.size) {
1026 rnand->control |= CONTROL_ECC_BLOCK_SIZE_256;
1029 rnand->control |= CONTROL_ECC_BLOCK_SIZE_512;
1032 rnand->control |= CONTROL_ECC_BLOCK_SIZE_1024;
1035 dev_err(rnandc->dev, "Unsupported ECC chunk size\n");
1036 return -EINVAL;
1039 switch (chip->ecc.strength) {
1041 chip->ecc.bytes = 4;
1042 rnand->ecc_ctrl |= ECC_CTRL_CAP_2B;
1045 chip->ecc.bytes = 7;
1046 rnand->ecc_ctrl |= ECC_CTRL_CAP_4B;
1049 chip->ecc.bytes = 14;
1050 rnand->ecc_ctrl |= ECC_CTRL_CAP_8B;
1053 chip->ecc.bytes = 28;
1054 rnand->ecc_ctrl |= ECC_CTRL_CAP_16B;
1057 chip->ecc.bytes = 42;
1058 rnand->ecc_ctrl |= ECC_CTRL_CAP_24B;
1061 chip->ecc.bytes = 56;
1062 rnand->ecc_ctrl |= ECC_CTRL_CAP_32B;
1065 dev_err(rnandc->dev, "Unsupported ECC strength\n");
1066 return -EINVAL;
1069 rnand->ecc_ctrl |= ECC_CTRL_ERR_THRESHOLD(chip->ecc.strength);
1072 chip->ecc.steps = mtd->writesize / chip->ecc.size;
1073 chip->ecc.read_page = rnandc_read_page_hw_ecc;
1074 chip->ecc.read_subpage = rnandc_read_subpage_hw_ecc;
1075 chip->ecc.write_page = rnandc_write_page_hw_ecc;
1076 chip->ecc.write_subpage = rnandc_write_subpage_hw_ecc;
1083 struct nand_ecc_ctrl *ecc = &chip->ecc;
1085 nanddev_get_ecc_requirements(&chip->base);
1086 struct rnandc *rnandc = to_rnandc(chip->controller);
1089 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
1090 (!ecc->size || !ecc->strength)) {
1091 if (requirements->step_size && requirements->strength) {
1092 ecc->size = requirements->step_size;
1093 ecc->strength = requirements->strength;
1095 dev_err(rnandc->dev, "No minimum ECC strength\n");
1096 return -EINVAL;
1100 switch (ecc->engine_type) {
1111 return -EINVAL;
1120 struct rnandc *rnandc = to_rnandc(chip->controller);
1122 struct nand_memory_organization *memorg = nanddev_get_memorg(&chip->base);
1126 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1127 chip->bbt_options |= NAND_BBT_NO_OOB;
1129 if (mtd->writesize <= 512) {
1130 dev_err(rnandc->dev, "Small page devices not supported\n");
1131 return -EINVAL;
1134 rnand->control |= CONTROL_CHECK_RB_LINE | CONTROL_INT_EN;
1136 switch (memorg->pages_per_eraseblock) {
1138 rnand->control |= CONTROL_BLOCK_SIZE_32P;
1141 rnand->control |= CONTROL_BLOCK_SIZE_64P;
1144 rnand->control |= CONTROL_BLOCK_SIZE_128P;
1147 rnand->control |= CONTROL_BLOCK_SIZE_256P;
1150 dev_err(rnandc->dev, "Unsupported memory organization\n");
1151 return -EINVAL;
1154 chip->options |= NAND_SUBPAGE_READ;
1158 dev_err(rnandc->dev, "ECC initialization failed (%d)\n", ret);
1163 rnand->selected_die = -1;
1177 unsigned int max_len = new_mtd->writesize + new_mtd->oobsize;
1182 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) {
1183 chip = &entry->chip;
1185 max_len = max(max_len, mtd->writesize + mtd->oobsize);
1188 if (rnandc->buf && rnandc->buf_sz < max_len) {
1189 devm_kfree(rnandc->dev, rnandc->buf);
1190 rnandc->buf = NULL;
1193 if (!rnandc->buf) {
1194 rnandc->buf_sz = max_len;
1195 rnandc->buf = devm_kmalloc(rnandc->dev, max_len,
1197 if (!rnandc->buf)
1198 return -ENOMEM;
1214 ret = (nsels < 0) ? nsels : -EINVAL;
1215 dev_err(rnandc->dev, "Invalid reg property (%d)\n", ret);
1220 rnand = devm_kzalloc(rnandc->dev, struct_size(rnand, sels, nsels),
1223 return -ENOMEM;
1225 rnand->nsels = nsels;
1226 rnand->selected_die = -1;
1231 dev_err(rnandc->dev, "Incomplete reg property (%d)\n", ret);
1236 dev_err(rnandc->dev, "Invalid reg property (%d)\n", cs);
1237 return -EINVAL;
1240 if (test_and_set_bit(cs, &rnandc->assigned_cs)) {
1241 dev_err(rnandc->dev, "CS %d already assigned\n", cs);
1242 return -EINVAL;
1249 rnand->sels[i].cs = cs;
1252 chip = &rnand->chip;
1253 chip->controller = &rnandc->controller;
1257 mtd->dev.parent = rnandc->dev;
1258 if (!mtd->name) {
1259 dev_err(rnandc->dev, "Missing MTD label\n");
1260 return -EINVAL;
1263 ret = nand_scan(chip, rnand->nsels);
1265 dev_err(rnandc->dev, "Failed to scan the NAND chip (%d)\n", ret);
1275 dev_err(rnandc->dev, "Failed to register MTD device (%d)\n", ret);
1279 list_add_tail(&rnand->node, &rnandc->chips);
1295 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) {
1296 chip = &entry->chip;
1300 list_del(&entry->node);
1308 for_each_child_of_node_scoped(rnandc->dev->of_node, np) {
1325 rnandc = devm_kzalloc(&pdev->dev, sizeof(*rnandc), GFP_KERNEL);
1327 return -ENOMEM;
1329 rnandc->dev = &pdev->dev;
1330 nand_controller_init(&rnandc->controller);
1331 rnandc->controller.ops = &rnandc_ops;
1332 INIT_LIST_HEAD(&rnandc->chips);
1333 init_completion(&rnandc->complete);
1335 rnandc->regs = devm_platform_ioremap_resource(pdev, 0);
1336 if (IS_ERR(rnandc->regs))
1337 return PTR_ERR(rnandc->regs);
1339 devm_pm_runtime_enable(&pdev->dev);
1340 ret = pm_runtime_resume_and_get(&pdev->dev);
1345 eclk = clk_get(&pdev->dev, "eclk");
1351 rnandc->ext_clk_rate = clk_get_rate(eclk);
1356 if (irq == -EPROBE_DEFER) {
1360 dev_info(&pdev->dev, "No IRQ found, fallback to polling\n");
1361 rnandc->use_polling = true;
1363 ret = devm_request_irq(&pdev->dev, irq, rnandc_irq_handler, 0,
1364 "renesas-nand-controller", rnandc);
1369 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1384 pm_runtime_put(&pdev->dev);
1395 pm_runtime_put(&pdev->dev);
1399 { .compatible = "renesas,rcar-gen3-nandc" },
1400 { .compatible = "renesas,rzn1-nandc" },
1407 .name = "renesas-nandc",
1416 MODULE_DESCRIPTION("Renesas R-Car Gen3 & RZ/N1 NAND controller driver");