Lines Matching +full:cmd +full:- +full:crci
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-qpic-common.h>
42 * @cmd_reg: CMD register value
82 * ecc/non-ecc mode for the current nand flash
132 ((u8 *)chip->controller - sizeof(struct qcom_nand_controller)); in get_qcom_nand_controller()
137 return ioread32(nandc->base + offset); in nandc_read()
143 iowrite32(val, nandc->base + offset); in nandc_write()
149 return cw == (ecc->steps - 1); in qcom_nandc_is_last_cw()
153 * nandc_set_read_loc_first() - to set read location first register
175 nandc->regs->read_location0 = locreg_val; in nandc_set_read_loc_first()
177 nandc->regs->read_location1 = locreg_val; in nandc_set_read_loc_first()
179 nandc->regs->read_location2 = locreg_val; in nandc_set_read_loc_first()
181 nandc->regs->read_location3 = locreg_val; in nandc_set_read_loc_first()
185 * nandc_set_read_loc_last - to set read location last register
207 nandc->regs->read_location_last0 = locreg_val; in nandc_set_read_loc_last()
209 nandc->regs->read_location_last1 = locreg_val; in nandc_set_read_loc_last()
211 nandc->regs->read_location_last2 = locreg_val; in nandc_set_read_loc_last()
213 nandc->regs->read_location_last3 = locreg_val; in nandc_set_read_loc_last()
221 struct nand_ecc_ctrl *ecc = &chip->ecc; in nandc_set_read_loc()
224 if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
229 if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
240 struct nand_chip *chip = &host->chip; in set_address()
243 if (chip->options & NAND_BUSWIDTH_16) in set_address()
246 nandc->regs->addr0 = cpu_to_le32(page << 16 | column); in set_address()
247 nandc->regs->addr1 = cpu_to_le32(page >> 16 & 0xff); in set_address()
260 struct nand_chip *chip = &host->chip; in update_rw_regs()
261 __le32 cmd, cfg0, cfg1, ecc_bch_cfg; in update_rw_regs() local
265 if (host->use_ecc) in update_rw_regs()
266 cmd = cpu_to_le32(OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE); in update_rw_regs()
268 cmd = cpu_to_le32(OP_PAGE_READ | PAGE_ACC | LAST_PAGE); in update_rw_regs()
270 cmd = cpu_to_le32(OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE); in update_rw_regs()
273 if (host->use_ecc) { in update_rw_regs()
274 cfg0 = cpu_to_le32((host->cfg0 & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
275 (num_cw - 1) << CW_PER_PAGE); in update_rw_regs()
277 cfg1 = cpu_to_le32(host->cfg1); in update_rw_regs()
278 ecc_bch_cfg = cpu_to_le32(host->ecc_bch_cfg); in update_rw_regs()
280 cfg0 = cpu_to_le32((host->cfg0_raw & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
281 (num_cw - 1) << CW_PER_PAGE); in update_rw_regs()
283 cfg1 = cpu_to_le32(host->cfg1_raw); in update_rw_regs()
287 nandc->regs->cmd = cmd; in update_rw_regs()
288 nandc->regs->cfg0 = cfg0; in update_rw_regs()
289 nandc->regs->cfg1 = cfg1; in update_rw_regs()
290 nandc->regs->ecc_bch_cfg = ecc_bch_cfg; in update_rw_regs()
292 if (!nandc->props->qpic_version2) in update_rw_regs()
293 nandc->regs->ecc_buf_cfg = cpu_to_le32(host->ecc_buf_cfg); in update_rw_regs()
295 nandc->regs->clrflashstatus = cpu_to_le32(host->clrflashstatus); in update_rw_regs()
296 nandc->regs->clrreadstatus = cpu_to_le32(host->clrreadstatus); in update_rw_regs()
297 nandc->regs->exec = cpu_to_le32(1); in update_rw_regs()
300 nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ? in update_rw_regs()
301 host->cw_data : host->cw_size, 1); in update_rw_regs()
312 qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); in config_nand_page_read()
313 qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in config_nand_page_read()
314 if (!nandc->props->qpic_version2) in config_nand_page_read()
315 qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0); in config_nand_page_read()
316 qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr, in config_nand_page_read()
318 qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set, in config_nand_page_read()
330 struct nand_ecc_ctrl *ecc = &chip->ecc; in config_nand_cw_read()
332 __le32 *reg = &nandc->regs->read_location0; in config_nand_cw_read()
334 if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
335 reg = &nandc->regs->read_location_last0; in config_nand_cw_read()
337 if (nandc->props->supports_bam) in config_nand_cw_read()
340 qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
341 qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
372 qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0); in config_nand_page_write()
373 qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in config_nand_page_write()
374 if (!nandc->props->qpic_version2) in config_nand_page_write()
375 qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, in config_nand_page_write()
387 qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
388 qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
392 qcom_write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0); in config_nand_cw_write()
393 qcom_write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1, in config_nand_cw_write()
454 struct nand_chip *chip = &host->chip; in check_flash_errors()
461 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
464 return -EIO; in check_flash_errors()
477 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_cw_raw()
483 nandc->buf_count = 0; in qcom_nandc_read_cw_raw()
484 nandc->buf_start = 0; in qcom_nandc_read_cw_raw()
486 host->use_ecc = false; in qcom_nandc_read_cw_raw()
488 if (nandc->props->qpic_version2) in qcom_nandc_read_cw_raw()
489 raw_cw = ecc->steps - 1; in qcom_nandc_read_cw_raw()
492 set_address(host, host->cw_size * cw, page); in qcom_nandc_read_cw_raw()
496 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_read_cw_raw()
497 oob_size1 = host->bbm_size; in qcom_nandc_read_cw_raw()
499 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in qcom_nandc_read_cw_raw()
500 data_size2 = ecc->size - data_size1 - in qcom_nandc_read_cw_raw()
501 ((ecc->steps - 1) * 4); in qcom_nandc_read_cw_raw()
502 oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + in qcom_nandc_read_cw_raw()
503 host->spare_bytes; in qcom_nandc_read_cw_raw()
505 data_size2 = host->cw_data - data_size1; in qcom_nandc_read_cw_raw()
506 oob_size2 = host->ecc_bytes_hw + host->spare_bytes; in qcom_nandc_read_cw_raw()
509 if (nandc->props->supports_bam) { in qcom_nandc_read_cw_raw()
537 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
548 * equal to the ecc->strength for each CW.
551 * top-level API can be called with only data buf or OOB buf so use
552 * chip->data_buf if data buf is null and chip->oob_poi if oob buf
564 struct nand_chip *chip = &host->chip; in check_for_erased_page()
566 struct nand_ecc_ctrl *ecc = &chip->ecc; in check_for_erased_page()
575 oob_buf = chip->oob_poi; in check_for_erased_page()
578 for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { in check_for_erased_page()
579 if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { in check_for_erased_page()
580 data_size = ecc->size - ((ecc->steps - 1) * 4); in check_for_erased_page()
581 oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; in check_for_erased_page()
583 data_size = host->cw_data; in check_for_erased_page()
584 oob_size = host->ecc_bytes_hw; in check_for_erased_page()
588 cw_data_buf = data_buf + (cw * host->cw_data); in check_for_erased_page()
589 cw_oob_buf = oob_buf + (cw * ecc->bytes); in check_for_erased_page()
598 * as not-erased by HW because of a few bitflips in check_for_erased_page()
601 cw_oob_buf + host->bbm_size, in check_for_erased_page()
603 0, ecc->strength); in check_for_erased_page()
605 mtd->ecc_stats.failed++; in check_for_erased_page()
607 mtd->ecc_stats.corrected += ret; in check_for_erased_page()
617 * errors. this is equivalent to what 'ecc->correct()' would do.
622 struct nand_chip *chip = &host->chip; in parse_read_errors()
625 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_read_errors()
632 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
635 for (i = 0; i < ecc->steps; i++, buf++) { in parse_read_errors()
640 data_len = ecc->size - ((ecc->steps - 1) << 2); in parse_read_errors()
641 oob_len = ecc->steps << 2; in parse_read_errors()
643 data_len = host->cw_data; in parse_read_errors()
647 flash = le32_to_cpu(buf->flash); in parse_read_errors()
648 buffer = le32_to_cpu(buf->buffer); in parse_read_errors()
649 erased_cw = le32_to_cpu(buf->erased_cw); in parse_read_errors()
664 if (host->bch_enabled) { in parse_read_errors()
697 mtd->ecc_stats.corrected += stat; in parse_read_errors()
704 oob_buf += oob_len + ecc->bytes; in parse_read_errors()
708 return -EIO; in parse_read_errors()
719 * helper to perform the actual page read operation, used by ecc->read_page(),
720 * ecc->read_oob()
725 struct nand_chip *chip = &host->chip; in read_page_ecc()
727 struct nand_ecc_ctrl *ecc = &chip->ecc; in read_page_ecc()
733 /* queue cmd descs for each codeword */ in read_page_ecc()
734 for (i = 0; i < ecc->steps; i++) { in read_page_ecc()
737 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in read_page_ecc()
738 data_size = ecc->size - ((ecc->steps - 1) << 2); in read_page_ecc()
739 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in read_page_ecc()
740 host->spare_bytes; in read_page_ecc()
742 data_size = host->cw_data; in read_page_ecc()
743 oob_size = host->ecc_bytes_hw + host->spare_bytes; in read_page_ecc()
746 if (nandc->props->supports_bam) { in read_page_ecc()
775 for (j = 0; j < host->bbm_size; j++) in read_page_ecc()
790 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
803 struct nand_chip *chip = &host->chip; in copy_last_cw()
805 struct nand_ecc_ctrl *ecc = &chip->ecc; in copy_last_cw()
811 size = host->use_ecc ? host->cw_data : host->cw_size; in copy_last_cw()
814 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
816 set_address(host, host->cw_size * (ecc->steps - 1), page); in copy_last_cw()
817 update_rw_regs(host, 1, true, ecc->steps - 1); in copy_last_cw()
819 config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1); in copy_last_cw()
821 qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
825 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
837 * Since the frequent access will be to the non-boot partitions like rootfs, in qcom_nandc_is_boot_partition()
845 boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1]; in qcom_nandc_is_boot_partition()
846 start = boot_partition->page_offset; in qcom_nandc_is_boot_partition()
847 end = start + boot_partition->page_size; in qcom_nandc_is_boot_partition()
857 /* Check the other boot partitions starting from the second-last partition */ in qcom_nandc_is_boot_partition()
858 for (i = host->nr_boot_partitions - 2; i >= 0; i--) { in qcom_nandc_is_boot_partition()
859 boot_partition = &host->boot_partitions[i]; in qcom_nandc_is_boot_partition()
860 start = boot_partition->page_offset; in qcom_nandc_is_boot_partition()
861 end = start + boot_partition->page_size; in qcom_nandc_is_boot_partition()
875 if (codeword_fixup == host->codeword_fixup) in qcom_nandc_codeword_fixup()
878 host->codeword_fixup = codeword_fixup; in qcom_nandc_codeword_fixup()
880 host->cw_data = codeword_fixup ? 512 : 516; in qcom_nandc_codeword_fixup()
881 host->spare_bytes = host->cw_size - host->ecc_bytes_hw - in qcom_nandc_codeword_fixup()
882 host->bbm_size - host->cw_data; in qcom_nandc_codeword_fixup()
884 host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); in qcom_nandc_codeword_fixup()
885 host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | in qcom_nandc_codeword_fixup()
886 host->cw_data << UD_SIZE_BYTES; in qcom_nandc_codeword_fixup()
888 host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; in qcom_nandc_codeword_fixup()
889 host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; in qcom_nandc_codeword_fixup()
890 host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS; in qcom_nandc_codeword_fixup()
893 /* implements ecc->read_page() */
899 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page()
902 if (host->nr_boot_partitions) in qcom_nandc_read_page()
906 nandc->buf_count = 0; in qcom_nandc_read_page()
907 nandc->buf_start = 0; in qcom_nandc_read_page()
908 host->use_ecc = true; in qcom_nandc_read_page()
911 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_read_page()
914 oob_buf = oob_required ? chip->oob_poi : NULL; in qcom_nandc_read_page()
921 /* implements ecc->read_page_raw() */
927 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page_raw()
929 u8 *data_buf = buf, *oob_buf = chip->oob_poi; in qcom_nandc_read_page_raw()
931 if (host->nr_boot_partitions) in qcom_nandc_read_page_raw()
934 for (cw = 0; cw < ecc->steps; cw++) { in qcom_nandc_read_page_raw()
940 data_buf += host->cw_data; in qcom_nandc_read_page_raw()
941 oob_buf += ecc->bytes; in qcom_nandc_read_page_raw()
947 /* implements ecc->read_oob() */
952 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_oob()
954 if (host->nr_boot_partitions) in qcom_nandc_read_oob()
960 host->use_ecc = true; in qcom_nandc_read_oob()
962 update_rw_regs(host, ecc->steps, true, 0); in qcom_nandc_read_oob()
964 return read_page_ecc(host, NULL, chip->oob_poi, page); in qcom_nandc_read_oob()
967 /* implements ecc->write_page() */
973 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page()
977 if (host->nr_boot_partitions) in qcom_nandc_write_page()
983 nandc->buf_count = 0; in qcom_nandc_write_page()
984 nandc->buf_start = 0; in qcom_nandc_write_page()
989 oob_buf = chip->oob_poi; in qcom_nandc_write_page()
991 host->use_ecc = true; in qcom_nandc_write_page()
992 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page()
995 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page()
998 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page()
999 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_page()
1000 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page()
1001 host->spare_bytes; in qcom_nandc_write_page()
1003 data_size = host->cw_data; in qcom_nandc_write_page()
1004 oob_size = ecc->bytes; in qcom_nandc_write_page()
1008 i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); in qcom_nandc_write_page()
1012 * to oob for the first n - 1 codewords since these oob regions in qcom_nandc_write_page()
1018 oob_buf += host->bbm_size; in qcom_nandc_write_page()
1032 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
1039 /* implements ecc->write_page_raw() */
1047 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page_raw()
1051 if (host->nr_boot_partitions) in qcom_nandc_write_page_raw()
1059 oob_buf = chip->oob_poi; in qcom_nandc_write_page_raw()
1061 host->use_ecc = false; in qcom_nandc_write_page_raw()
1062 update_rw_regs(host, ecc->steps, false, 0); in qcom_nandc_write_page_raw()
1065 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page_raw()
1069 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_write_page_raw()
1070 oob_size1 = host->bbm_size; in qcom_nandc_write_page_raw()
1072 if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { in qcom_nandc_write_page_raw()
1073 data_size2 = ecc->size - data_size1 - in qcom_nandc_write_page_raw()
1074 ((ecc->steps - 1) << 2); in qcom_nandc_write_page_raw()
1075 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page_raw()
1076 host->spare_bytes; in qcom_nandc_write_page_raw()
1078 data_size2 = host->cw_data - data_size1; in qcom_nandc_write_page_raw()
1079 oob_size2 = host->ecc_bytes_hw + host->spare_bytes; in qcom_nandc_write_page_raw()
1105 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
1113 * implements ecc->write_oob()
1117 * chip->oob_poi, and pad the data area with OxFF before writing.
1124 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_oob()
1125 u8 *oob = chip->oob_poi; in qcom_nandc_write_oob()
1129 if (host->nr_boot_partitions) in qcom_nandc_write_oob()
1132 host->use_ecc = true; in qcom_nandc_write_oob()
1136 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_oob()
1137 oob_size = mtd->oobavail; in qcom_nandc_write_oob()
1139 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
1141 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
1142 0, mtd->oobavail); in qcom_nandc_write_oob()
1144 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_write_oob()
1149 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
1154 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
1166 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_bad()
1169 page = (int)(ofs >> chip->page_shift) & chip->pagemask; in qcom_nandc_block_bad()
1177 host->use_ecc = false; in qcom_nandc_block_bad()
1185 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
1189 bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_block_bad()
1191 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
1193 if (chip->options & NAND_BUSWIDTH_16) in qcom_nandc_block_bad()
1194 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
1203 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_markbad()
1214 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
1216 page = (int)(ofs >> chip->page_shift) & chip->pagemask; in qcom_nandc_block_markbad()
1219 host->use_ecc = false; in qcom_nandc_block_markbad()
1220 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_block_markbad()
1221 update_rw_regs(host, 1, false, ecc->steps - 1); in qcom_nandc_block_markbad()
1225 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
1230 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
1242 * |----------------------| |---------------------------------|
1245 * | (516) xx.......yy| | (516-n*4) **(n*4)**xx.......yy|
1247 * |----------------------| |---------------------------------|
1248 * codeword 1,2..n-1 codeword n
1249 * <---(528/532 Bytes)--> <-------(528/532 Bytes)--------->
1265 * the first n - 1 codewords contains 516 bytes of user data, the remaining
1276 * |------------------------------| |---------------------------------------|
1281 * |------------------------------| |---------------------------------------|
1282 * codeword 1,2..n-1 codeword n
1283 * <-------(528/532 Bytes)------> <-----------(528/532 Bytes)----------->
1294 * width) is now accessible. For the first n - 1 codewords, these are dummy Bad
1300 * |-----------| |--------------------|
1305 * |-----------| |--------------------|
1306 * first n - 1 nth OOB region
1319 * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
1327 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_ecc()
1330 return -ERANGE; in qcom_nand_ooblayout_ecc()
1333 oobregion->length = (ecc->bytes * (ecc->steps - 1)) + in qcom_nand_ooblayout_ecc()
1334 host->bbm_size; in qcom_nand_ooblayout_ecc()
1335 oobregion->offset = 0; in qcom_nand_ooblayout_ecc()
1337 oobregion->length = host->ecc_bytes_hw + host->spare_bytes; in qcom_nand_ooblayout_ecc()
1338 oobregion->offset = mtd->oobsize - oobregion->length; in qcom_nand_ooblayout_ecc()
1349 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_free()
1352 return -ERANGE; in qcom_nand_ooblayout_free()
1354 oobregion->length = ecc->steps * 4; in qcom_nand_ooblayout_free()
1355 oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size; in qcom_nand_ooblayout_free()
1378 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_attach_chip()
1385 ecc->size = NANDC_STEP_SIZE; in qcom_nand_attach_chip()
1386 wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; in qcom_nand_attach_chip()
1387 cwperpage = mtd->writesize / NANDC_STEP_SIZE; in qcom_nand_attach_chip()
1394 mtd->oobsize - (cwperpage * 4)); in qcom_nand_attach_chip()
1396 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
1400 if (ecc->strength >= 8) { in qcom_nand_attach_chip()
1402 host->bch_enabled = true; in qcom_nand_attach_chip()
1406 host->ecc_bytes_hw = 14; in qcom_nand_attach_chip()
1407 host->spare_bytes = 0; in qcom_nand_attach_chip()
1408 host->bbm_size = 2; in qcom_nand_attach_chip()
1410 host->ecc_bytes_hw = 13; in qcom_nand_attach_chip()
1411 host->spare_bytes = 2; in qcom_nand_attach_chip()
1412 host->bbm_size = 1; in qcom_nand_attach_chip()
1420 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
1422 host->bch_enabled = true; in qcom_nand_attach_chip()
1426 host->ecc_bytes_hw = 8; in qcom_nand_attach_chip()
1427 host->spare_bytes = 2; in qcom_nand_attach_chip()
1428 host->bbm_size = 2; in qcom_nand_attach_chip()
1430 host->ecc_bytes_hw = 7; in qcom_nand_attach_chip()
1431 host->spare_bytes = 4; in qcom_nand_attach_chip()
1432 host->bbm_size = 1; in qcom_nand_attach_chip()
1436 host->ecc_bytes_hw = 10; in qcom_nand_attach_chip()
1439 host->spare_bytes = 0; in qcom_nand_attach_chip()
1440 host->bbm_size = 2; in qcom_nand_attach_chip()
1442 host->spare_bytes = 1; in qcom_nand_attach_chip()
1443 host->bbm_size = 1; in qcom_nand_attach_chip()
1449 * we consider ecc->bytes as the sum of all the non-data content in a in qcom_nand_attach_chip()
1454 ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size; in qcom_nand_attach_chip()
1456 ecc->read_page = qcom_nandc_read_page; in qcom_nand_attach_chip()
1457 ecc->read_page_raw = qcom_nandc_read_page_raw; in qcom_nand_attach_chip()
1458 ecc->read_oob = qcom_nandc_read_oob; in qcom_nand_attach_chip()
1459 ecc->write_page = qcom_nandc_write_page; in qcom_nand_attach_chip()
1460 ecc->write_page_raw = qcom_nandc_write_page_raw; in qcom_nand_attach_chip()
1461 ecc->write_oob = qcom_nandc_write_oob; in qcom_nand_attach_chip()
1463 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in qcom_nand_attach_chip()
1467 if (nandc->props->supports_bam) in qcom_nand_attach_chip()
1470 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
1474 if (nandc->props->supports_bam) { in qcom_nand_attach_chip()
1475 nandc->bam_txn = qcom_alloc_bam_transaction(nandc); in qcom_nand_attach_chip()
1476 if (!nandc->bam_txn) { in qcom_nand_attach_chip()
1477 dev_err(nandc->dev, in qcom_nand_attach_chip()
1479 return -ENOMEM; in qcom_nand_attach_chip()
1488 host->cw_data = 516; in qcom_nand_attach_chip()
1494 host->cw_size = host->cw_data + ecc->bytes; in qcom_nand_attach_chip()
1495 bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1; in qcom_nand_attach_chip()
1497 host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | in qcom_nand_attach_chip()
1498 FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_data) | in qcom_nand_attach_chip()
1501 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, host->ecc_bytes_hw) | in qcom_nand_attach_chip()
1504 FIELD_PREP(SPARE_SIZE_BYTES_MASK, host->spare_bytes); in qcom_nand_attach_chip()
1506 host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | in qcom_nand_attach_chip()
1511 FIELD_PREP(ENABLE_BCH_ECC, host->bch_enabled); in qcom_nand_attach_chip()
1513 host->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | in qcom_nand_attach_chip()
1514 FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_size) | in qcom_nand_attach_chip()
1518 host->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | in qcom_nand_attach_chip()
1526 host->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !host->bch_enabled) | in qcom_nand_attach_chip()
1528 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, host->cw_data) | in qcom_nand_attach_chip()
1531 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, host->ecc_bytes_hw); in qcom_nand_attach_chip()
1533 if (!nandc->props->qpic_version2) in qcom_nand_attach_chip()
1534 host->ecc_buf_cfg = 0x203 << NUM_STEPS; in qcom_nand_attach_chip()
1536 host->clrflashstatus = FS_READY_BSY_N; in qcom_nand_attach_chip()
1537 host->clrreadstatus = 0xc0; in qcom_nand_attach_chip()
1538 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
1540 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
1543 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
1545 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_attach_chip()
1546 host->cw_size, host->cw_data, ecc->strength, ecc->bytes, in qcom_nand_attach_chip()
1557 int cmd; in qcom_op_cmd_mapping() local
1561 cmd = OP_RESET_DEVICE; in qcom_op_cmd_mapping()
1564 cmd = OP_FETCH_ID; in qcom_op_cmd_mapping()
1567 if (nandc->props->qpic_version2) in qcom_op_cmd_mapping()
1568 cmd = OP_PAGE_READ_ONFI_READ; in qcom_op_cmd_mapping()
1570 cmd = OP_PAGE_READ; in qcom_op_cmd_mapping()
1574 cmd = OP_BLOCK_ERASE; in qcom_op_cmd_mapping()
1577 cmd = OP_CHECK_STATUS; in qcom_op_cmd_mapping()
1580 cmd = OP_PROGRAM_PAGE; in qcom_op_cmd_mapping()
1581 q_op->flag = OP_PROGRAM_PAGE; in qcom_op_cmd_mapping()
1582 nandc->exec_opwrite = true; in qcom_op_cmd_mapping()
1586 if (host->use_ecc) in qcom_op_cmd_mapping()
1587 cmd = OP_PAGE_READ_WITH_ECC; in qcom_op_cmd_mapping()
1589 cmd = OP_PAGE_READ; in qcom_op_cmd_mapping()
1592 dev_err(nandc->dev, "Opcode not supported: %u\n", opcode); in qcom_op_cmd_mapping()
1593 return -EOPNOTSUPP; in qcom_op_cmd_mapping()
1596 return cmd; in qcom_op_cmd_mapping()
1599 /* NAND framework ->exec_op() hooks and related helpers */
1608 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in qcom_parse_instructions()
1612 instr = &subop->instrs[op_id]; in qcom_parse_instructions()
1614 switch (instr->type) { in qcom_parse_instructions()
1616 ret = qcom_op_cmd_mapping(chip, instr->ctx.cmd.opcode, q_op); in qcom_parse_instructions()
1620 q_op->cmd_reg = cpu_to_le32(ret); in qcom_parse_instructions()
1621 q_op->rdy_delay_ns = instr->delay_ns; in qcom_parse_instructions()
1627 addrs = &instr->ctx.addr.addrs[offset]; in qcom_parse_instructions()
1630 q_op->addr1_reg |= cpu_to_le32(addrs[i] << (i * 8)); in qcom_parse_instructions()
1633 q_op->addr2_reg |= cpu_to_le32(addrs[4]); in qcom_parse_instructions()
1635 q_op->rdy_delay_ns = instr->delay_ns; in qcom_parse_instructions()
1639 q_op->data_instr = instr; in qcom_parse_instructions()
1640 q_op->data_instr_idx = op_id; in qcom_parse_instructions()
1641 q_op->rdy_delay_ns = instr->delay_ns; in qcom_parse_instructions()
1644 q_op->rdy_delay_ns = instr->delay_ns; in qcom_parse_instructions()
1648 q_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in qcom_parse_instructions()
1649 q_op->rdy_delay_ns = instr->delay_ns; in qcom_parse_instructions()
1677 flash = le32_to_cpu(nandc->reg_read_buf[0]); in qcom_wait_rdy_poll()
1683 dev_err(nandc->dev, "Timeout waiting for device to be ready:0x%08x\n", flash); in qcom_wait_rdy_poll()
1685 return -ETIMEDOUT; in qcom_wait_rdy_poll()
1693 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_read_status_exec()
1701 host->status = NAND_STATUS_READY | NAND_STATUS_WP; in qcom_read_status_exec()
1707 num_cw = nandc->exec_opwrite ? ecc->steps : 1; in qcom_read_status_exec()
1708 nandc->exec_opwrite = false; in qcom_read_status_exec()
1710 nandc->buf_count = 0; in qcom_read_status_exec()
1711 nandc->buf_start = 0; in qcom_read_status_exec()
1712 host->use_ecc = false; in qcom_read_status_exec()
1717 nandc->regs->cmd = q_op.cmd_reg; in qcom_read_status_exec()
1718 nandc->regs->exec = cpu_to_le32(1); in qcom_read_status_exec()
1720 qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_read_status_exec()
1721 qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_read_status_exec()
1726 dev_err(nandc->dev, "failure in submitting status descriptor\n"); in qcom_read_status_exec()
1733 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in qcom_read_status_exec()
1736 host->status &= ~NAND_STATUS_WP; in qcom_read_status_exec()
1739 (i == (num_cw - 1) && (flash_status & FS_DEVICE_STS_ERR))) in qcom_read_status_exec()
1740 host->status |= NAND_STATUS_FAIL; in qcom_read_status_exec()
1743 flash_status = host->status; in qcom_read_status_exec()
1747 memcpy(instr->ctx.data.buf.in, &flash_status, len); in qcom_read_status_exec()
1767 nandc->buf_count = 0; in qcom_read_id_type_exec()
1768 nandc->buf_start = 0; in qcom_read_id_type_exec()
1769 host->use_ecc = false; in qcom_read_id_type_exec()
1774 nandc->regs->cmd = q_op.cmd_reg; in qcom_read_id_type_exec()
1775 nandc->regs->addr0 = q_op.addr1_reg; in qcom_read_id_type_exec()
1776 nandc->regs->addr1 = q_op.addr2_reg; in qcom_read_id_type_exec()
1777 nandc->regs->chip_sel = cpu_to_le32(nandc->props->supports_bam ? 0 : DM_EN); in qcom_read_id_type_exec()
1778 nandc->regs->exec = cpu_to_le32(1); in qcom_read_id_type_exec()
1780 qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); in qcom_read_id_type_exec()
1781 qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_read_id_type_exec()
1787 dev_err(nandc->dev, "failure in submitting read id descriptor\n"); in qcom_read_id_type_exec()
1796 memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len); in qcom_read_id_type_exec()
1818 nandc->regs->addr0 = q_op.addr1_reg; in qcom_misc_cmd_type_exec()
1819 nandc->regs->addr1 = q_op.addr2_reg; in qcom_misc_cmd_type_exec()
1820 nandc->regs->cfg0 = cpu_to_le32(host->cfg0_raw & ~(7 << CW_PER_PAGE)); in qcom_misc_cmd_type_exec()
1821 nandc->regs->cfg1 = cpu_to_le32(host->cfg1_raw); in qcom_misc_cmd_type_exec()
1827 nandc->buf_count = 0; in qcom_misc_cmd_type_exec()
1828 nandc->buf_start = 0; in qcom_misc_cmd_type_exec()
1829 host->use_ecc = false; in qcom_misc_cmd_type_exec()
1834 nandc->regs->cmd = q_op.cmd_reg; in qcom_misc_cmd_type_exec()
1835 nandc->regs->exec = cpu_to_le32(1); in qcom_misc_cmd_type_exec()
1837 qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
1839 qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
1841 qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
1846 dev_err(nandc->dev, "failure in submitting misc descriptor\n"); in qcom_misc_cmd_type_exec()
1874 nandc->buf_count = 0; in qcom_param_page_type_exec()
1875 nandc->buf_start = 0; in qcom_param_page_type_exec()
1876 host->use_ecc = false; in qcom_param_page_type_exec()
1880 nandc->regs->cmd = q_op.cmd_reg; in qcom_param_page_type_exec()
1881 nandc->regs->addr0 = 0; in qcom_param_page_type_exec()
1882 nandc->regs->addr1 = 0; in qcom_param_page_type_exec()
1884 nandc->regs->cfg0 = cpu_to_le32(FIELD_PREP(CW_PER_PAGE_MASK, 0) | in qcom_param_page_type_exec()
1889 nandc->regs->cfg1 = cpu_to_le32(FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | in qcom_param_page_type_exec()
1897 if (!nandc->props->qpic_version2) in qcom_param_page_type_exec()
1898 nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE); in qcom_param_page_type_exec()
1901 if (!nandc->props->qpic_version2) { in qcom_param_page_type_exec()
1902 nandc->regs->vld = cpu_to_le32((nandc->vld & ~READ_START_VLD)); in qcom_param_page_type_exec()
1903 nandc->regs->cmd1 = cpu_to_le32((nandc->cmd1 & ~(0xFF << READ_ADDR)) in qcom_param_page_type_exec()
1907 nandc->regs->exec = cpu_to_le32(1); in qcom_param_page_type_exec()
1909 if (!nandc->props->qpic_version2) { in qcom_param_page_type_exec()
1910 nandc->regs->orig_cmd1 = cpu_to_le32(nandc->cmd1); in qcom_param_page_type_exec()
1911 nandc->regs->orig_vld = cpu_to_le32(nandc->vld); in qcom_param_page_type_exec()
1920 if (!nandc->props->qpic_version2) { in qcom_param_page_type_exec()
1921 qcom_write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0); in qcom_param_page_type_exec()
1922 qcom_write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); in qcom_param_page_type_exec()
1925 nandc->buf_count = len; in qcom_param_page_type_exec()
1926 memset(nandc->data_buffer, 0xff, nandc->buf_count); in qcom_param_page_type_exec()
1930 qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in qcom_param_page_type_exec()
1931 nandc->buf_count, 0); in qcom_param_page_type_exec()
1934 if (!nandc->props->qpic_version2) { in qcom_param_page_type_exec()
1935 qcom_write_reg_dma(nandc, &nandc->regs->orig_cmd1, NAND_DEV_CMD1_RESTORE, 1, 0); in qcom_param_page_type_exec()
1936 qcom_write_reg_dma(nandc, &nandc->regs->orig_vld, NAND_DEV_CMD_VLD_RESTORE, 1, in qcom_param_page_type_exec()
1942 dev_err(nandc->dev, "failure in submitting param page descriptor\n"); in qcom_param_page_type_exec()
1950 memcpy(instr->ctx.data.buf.in, nandc->data_buffer, len); in qcom_param_page_type_exec()
1986 for (op_id = 0; op_id < op->ninstrs; op_id++) { in qcom_check_op()
1987 instr = &op->instrs[op_id]; in qcom_check_op()
1989 switch (instr->type) { in qcom_check_op()
1991 if (instr->ctx.cmd.opcode != NAND_CMD_RESET && in qcom_check_op()
1992 instr->ctx.cmd.opcode != NAND_CMD_READID && in qcom_check_op()
1993 instr->ctx.cmd.opcode != NAND_CMD_PARAM && in qcom_check_op()
1994 instr->ctx.cmd.opcode != NAND_CMD_ERASE1 && in qcom_check_op()
1995 instr->ctx.cmd.opcode != NAND_CMD_ERASE2 && in qcom_check_op()
1996 instr->ctx.cmd.opcode != NAND_CMD_STATUS && in qcom_check_op()
1997 instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG && in qcom_check_op()
1998 instr->ctx.cmd.opcode != NAND_CMD_READ0 && in qcom_check_op()
1999 instr->ctx.cmd.opcode != NAND_CMD_READSTART) in qcom_check_op()
2000 return -EOPNOTSUPP; in qcom_check_op()
2029 nand_controller_init(nandc->controller); in qcom_nandc_setup()
2030 nandc->controller->ops = &qcom_nandc_ops; in qcom_nandc_setup()
2033 if (!nandc->props->nandc_part_of_qpic) in qcom_nandc_setup()
2036 if (!nandc->props->qpic_version2) in qcom_nandc_setup()
2041 if (nandc->props->supports_bam) { in qcom_nandc_setup()
2058 if (!nandc->props->qpic_version2) { in qcom_nandc_setup()
2059 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
2060 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
2072 struct nand_chip *chip = &host->chip; in qcom_nand_host_parse_boot_partitions()
2075 struct device *dev = nandc->dev; in qcom_nand_host_parse_boot_partitions()
2078 if (!of_property_present(dn, "qcom,boot-partitions")) in qcom_nand_host_parse_boot_partitions()
2081 partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); in qcom_nand_host_parse_boot_partitions()
2084 return partitions_count ? partitions_count : -EINVAL; in qcom_nand_host_parse_boot_partitions()
2087 host->nr_boot_partitions = partitions_count / 2; in qcom_nand_host_parse_boot_partitions()
2088 host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, in qcom_nand_host_parse_boot_partitions()
2089 sizeof(*host->boot_partitions), GFP_KERNEL); in qcom_nand_host_parse_boot_partitions()
2090 if (!host->boot_partitions) { in qcom_nand_host_parse_boot_partitions()
2091 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
2092 return -ENOMEM; in qcom_nand_host_parse_boot_partitions()
2095 for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { in qcom_nand_host_parse_boot_partitions()
2096 boot_partition = &host->boot_partitions[i]; in qcom_nand_host_parse_boot_partitions()
2098 ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, in qcom_nand_host_parse_boot_partitions()
2099 &boot_partition->page_offset); in qcom_nand_host_parse_boot_partitions()
2102 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
2106 if (boot_partition->page_offset % mtd->writesize) { in qcom_nand_host_parse_boot_partitions()
2109 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
2110 return -EINVAL; in qcom_nand_host_parse_boot_partitions()
2113 boot_partition->page_offset /= mtd->writesize; in qcom_nand_host_parse_boot_partitions()
2115 ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, in qcom_nand_host_parse_boot_partitions()
2116 &boot_partition->page_size); in qcom_nand_host_parse_boot_partitions()
2119 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
2123 if (boot_partition->page_size % mtd->writesize) { in qcom_nand_host_parse_boot_partitions()
2126 host->nr_boot_partitions = 0; in qcom_nand_host_parse_boot_partitions()
2127 return -EINVAL; in qcom_nand_host_parse_boot_partitions()
2130 boot_partition->page_size /= mtd->writesize; in qcom_nand_host_parse_boot_partitions()
2140 struct nand_chip *chip = &host->chip; in qcom_nand_host_init_and_register()
2142 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
2145 ret = of_property_read_u32(dn, "reg", &host->cs); in qcom_nand_host_init_and_register()
2147 dev_err(dev, "can't get chip-select\n"); in qcom_nand_host_init_and_register()
2148 return -ENXIO; in qcom_nand_host_init_and_register()
2152 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs); in qcom_nand_host_init_and_register()
2153 if (!mtd->name) in qcom_nand_host_init_and_register()
2154 return -ENOMEM; in qcom_nand_host_init_and_register()
2156 mtd->owner = THIS_MODULE; in qcom_nand_host_init_and_register()
2157 mtd->dev.parent = dev; in qcom_nand_host_init_and_register()
2167 chip->legacy.block_bad = qcom_nandc_block_bad; in qcom_nand_host_init_and_register()
2168 chip->legacy.block_markbad = qcom_nandc_block_markbad; in qcom_nand_host_init_and_register()
2170 chip->controller = nandc->controller; in qcom_nand_host_init_and_register()
2171 chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA | in qcom_nand_host_init_and_register()
2175 host->status = NAND_STATUS_READY | NAND_STATUS_WP; in qcom_nand_host_init_and_register()
2185 if (nandc->props->use_codeword_fixup) { in qcom_nand_host_init_and_register()
2200 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
2201 struct device_node *dn = dev->of_node, *child; in qcom_probe_nand_devices()
2203 int ret = -ENODEV; in qcom_probe_nand_devices()
2209 return -ENOMEM; in qcom_probe_nand_devices()
2218 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
2228 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
2231 if (!nandc->props->supports_bam) { in qcom_nandc_parse_dt()
2232 ret = of_property_read_u32(np, "qcom,cmd-crci", in qcom_nandc_parse_dt()
2233 &nandc->cmd_crci); in qcom_nandc_parse_dt()
2235 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
2239 ret = of_property_read_u32(np, "qcom,data-crci", in qcom_nandc_parse_dt()
2240 &nandc->data_crci); in qcom_nandc_parse_dt()
2242 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
2255 struct device *dev = &pdev->dev; in qcom_nandc_probe()
2259 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc) + sizeof(*controller), in qcom_nandc_probe()
2262 return -ENOMEM; in qcom_nandc_probe()
2266 nandc->dev = dev; in qcom_nandc_probe()
2267 nandc->controller = controller; in qcom_nandc_probe()
2271 dev_err(&pdev->dev, "failed to get device data\n"); in qcom_nandc_probe()
2272 return -ENODEV; in qcom_nandc_probe()
2275 nandc->props = dev_data; in qcom_nandc_probe()
2277 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
2278 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
2279 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
2281 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
2282 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
2283 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
2289 nandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in qcom_nandc_probe()
2290 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
2291 return PTR_ERR(nandc->base); in qcom_nandc_probe()
2293 nandc->base_phys = res->start; in qcom_nandc_probe()
2294 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
2297 if (dma_mapping_error(dev, nandc->base_dma)) in qcom_nandc_probe()
2298 return -ENXIO; in qcom_nandc_probe()
2300 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
2304 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
2325 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
2327 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
2329 dma_unmap_resource(dev, nandc->base_dma, resource_size(res), in qcom_nandc_probe()
2342 list_for_each_entry(host, &nandc->host_list, node) { in qcom_nandc_remove()
2343 chip = &host->chip; in qcom_nandc_remove()
2351 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
2352 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
2354 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()
2393 .compatible = "qcom,ipq806x-nand",
2397 .compatible = "qcom,ipq4019-nand",
2401 .compatible = "qcom,ipq6018-nand",
2405 .compatible = "qcom,ipq8074-nand",
2409 .compatible = "qcom,sdx55-nand",
2418 .name = "qcom-nandc",