Lines Matching full:sdr
595 const struct nand_sdr_timings *sdr = in pl35x_nand_read_page_hwecc() local
631 ndelay(PSEC_TO_NSEC(sdr->tRR_min)); in pl35x_nand_read_page_hwecc()
790 const struct nand_sdr_timings *sdr; in pl35x_nfc_setup_interface() local
794 sdr = nand_get_sdr_timings(conf); in pl35x_nfc_setup_interface()
795 if (IS_ERR(sdr)) in pl35x_nfc_setup_interface()
796 return PTR_ERR(sdr); in pl35x_nfc_setup_interface()
805 * SDR timings are given in pico-seconds while NFC timings must be in pl35x_nfc_setup_interface()
812 * PL35X SMC needs one extra read cycle in SDR Mode 5. This is not in pl35x_nfc_setup_interface()
815 val = TO_CYCLES(sdr->tRC_min, period_ns); in pl35x_nfc_setup_interface()
816 if (sdr->tRC_min <= 20000) in pl35x_nfc_setup_interface()
823 val = TO_CYCLES(sdr->tWC_min, period_ns); in pl35x_nfc_setup_interface()
829 * For all SDR modes, PL35X SMC needs tREA_max being 1, in pl35x_nfc_setup_interface()
834 val = TO_CYCLES(sdr->tWP_min, period_ns); in pl35x_nfc_setup_interface()
839 val = TO_CYCLES(sdr->tCLR_min, period_ns); in pl35x_nfc_setup_interface()
844 val = TO_CYCLES(sdr->tAR_min, period_ns); in pl35x_nfc_setup_interface()
849 val = TO_CYCLES(sdr->tRR_min, period_ns); in pl35x_nfc_setup_interface()