Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
123 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
129 /* GPMC ecc engine settings for write */
130 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
145 struct nand_chip nand; member
170 /* fields specific for BCHx_HW ECC scheme */
172 /* NAND ready gpio */
187 return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand); in mtd_to_omap()
198 * omap_prefetch_enable - configures and starts prefetch transfer
201 * @dma_mode: dma mode enable (1) or disable (0)
203 * @is_write: prefetch read(0) or write post(1) mode
204 * @info: NAND device structure containing platform data
212 return -1; in omap_prefetch_enable()
214 if (readl(info->reg.gpmc_prefetch_control)) in omap_prefetch_enable()
215 return -EBUSY; in omap_prefetch_enable()
218 writel(u32_count, info->reg.gpmc_prefetch_config2); in omap_prefetch_enable()
220 /* Set dma/mpu mode, the prefetch read / post write and in omap_prefetch_enable()
226 writel(val, info->reg.gpmc_prefetch_config1); in omap_prefetch_enable()
229 writel(0x1, info->reg.gpmc_prefetch_control); in omap_prefetch_enable()
235 * omap_prefetch_reset - disables and stops the prefetch engine
242 config1 = readl(info->reg.gpmc_prefetch_config1); in omap_prefetch_reset()
244 return -EINVAL; in omap_prefetch_reset()
247 writel(0x0, info->reg.gpmc_prefetch_control); in omap_prefetch_reset()
250 writel(0x0, info->reg.gpmc_prefetch_config1); in omap_prefetch_reset()
256 * omap_nand_data_in_pref - NAND data in using prefetch engine
257 * @chip: NAND chip
258 * @buf: output buffer where NAND data is placed into
260 * @force_8bit: force 8-bit transfers
276 /* read 32-bit words using prefetch and remaining bytes normally */ in omap_nand_data_in_pref()
279 pref_len = len - (len & 3); in omap_nand_data_in_pref()
280 ret = omap_prefetch_enable(info->gpmc_cs, in omap_nand_data_in_pref()
287 r_count = readl(info->reg.gpmc_prefetch_status); in omap_nand_data_in_pref()
290 ioread32_rep(info->fifo, p, r_count); in omap_nand_data_in_pref()
292 pref_len -= r_count << 2; in omap_nand_data_in_pref()
295 omap_prefetch_reset(info->gpmc_cs, info); in omap_nand_data_in_pref()
303 * omap_nand_data_out_pref - NAND data out using Write Posting engine
304 * @chip: NAND chip
305 * @buf: input buffer that is sent to NAND
307 * @force_8bit: force 8-bit transfers
327 writeb(*(u8 *)buf, info->fifo); in omap_nand_data_out_pref()
329 len--; in omap_nand_data_out_pref()
333 ret = omap_prefetch_enable(info->gpmc_cs, in omap_nand_data_out_pref()
340 w_count = readl(info->reg.gpmc_prefetch_status); in omap_nand_data_out_pref()
343 for (i = 0; (i < w_count) && len; i++, len -= 2) in omap_nand_data_out_pref()
344 iowrite16(*p++, info->fifo); in omap_nand_data_out_pref()
346 /* wait for data to flushed-out before reset the prefetch */ in omap_nand_data_out_pref()
352 val = readl(info->reg.gpmc_prefetch_status); in omap_nand_data_out_pref()
357 omap_prefetch_reset(info->gpmc_cs, info); in omap_nand_data_out_pref()
372 * @chip: nand chip structure
395 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); in omap_nand_dma_transfer()
397 dev_err(&info->pdev->dev, in omap_nand_dma_transfer()
402 tx = dmaengine_prep_slave_sg(info->dma, &sg, n, in omap_nand_dma_transfer()
408 tx->callback = omap_nand_dma_callback; in omap_nand_dma_transfer()
409 tx->callback_param = &info->comp; in omap_nand_dma_transfer()
412 init_completion(&info->comp); in omap_nand_dma_transfer()
415 dma_async_issue_pending(info->dma); in omap_nand_dma_transfer()
418 ret = omap_prefetch_enable(info->gpmc_cs, in omap_nand_dma_transfer()
424 wait_for_completion(&info->comp); in omap_nand_dma_transfer()
430 val = readl(info->reg.gpmc_prefetch_status); in omap_nand_dma_transfer()
435 omap_prefetch_reset(info->gpmc_cs, info); in omap_nand_dma_transfer()
437 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); in omap_nand_dma_transfer()
441 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); in omap_nand_dma_transfer()
450 * omap_nand_data_in_dma_pref - NAND data in using DMA and Prefetch
451 * @chip: NAND chip
452 * @buf: output buffer where NAND data is placed into
454 * @force_8bit: force 8-bit transfers
466 if (len <= mtd->oobsize) in omap_nand_data_in_dma_pref()
469 /* start transfer in DMA mode */ in omap_nand_data_in_dma_pref()
474 * omap_nand_data_out_dma_pref - NAND data out using DMA and write posting
475 * @chip: NAND chip
476 * @buf: input buffer that is sent to NAND
478 * @force_8bit: force 8-bit transfers
491 if (len <= mtd->oobsize) in omap_nand_data_out_dma_pref()
494 /* start transfer in DMA mode */ in omap_nand_data_out_dma_pref()
499 * omap_nand_irq - GPMC irq handler
508 bytes = readl(info->reg.gpmc_prefetch_status); in omap_nand_irq()
511 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ in omap_nand_irq()
512 if (this_irq == info->gpmc_irq_count) in omap_nand_irq()
515 if (info->buf_len && (info->buf_len < bytes)) in omap_nand_irq()
516 bytes = info->buf_len; in omap_nand_irq()
517 else if (!info->buf_len) in omap_nand_irq()
519 iowrite32_rep(info->fifo, (u32 *)info->buf, in omap_nand_irq()
521 info->buf = info->buf + bytes; in omap_nand_irq()
522 info->buf_len -= bytes; in omap_nand_irq()
525 ioread32_rep(info->fifo, (u32 *)info->buf, in omap_nand_irq()
527 info->buf = info->buf + bytes; in omap_nand_irq()
529 if (this_irq == info->gpmc_irq_count) in omap_nand_irq()
536 complete(&info->comp); in omap_nand_irq()
538 disable_irq_nosync(info->gpmc_irq_fifo); in omap_nand_irq()
539 disable_irq_nosync(info->gpmc_irq_count); in omap_nand_irq()
545 * omap_nand_data_in_irq_pref - NAND data in using Prefetch and IRQ
551 struct mtd_info *mtd = nand_to_mtd(&info->nand); in omap_nand_data_in_irq_pref()
554 if (len <= mtd->oobsize || force_8bit) { in omap_nand_data_in_irq_pref()
559 info->iomode = OMAP_NAND_IO_READ; in omap_nand_data_in_irq_pref()
560 info->buf = buf; in omap_nand_data_in_irq_pref()
561 init_completion(&info->comp); in omap_nand_data_in_irq_pref()
564 ret = omap_prefetch_enable(info->gpmc_cs, in omap_nand_data_in_irq_pref()
572 info->buf_len = len; in omap_nand_data_in_irq_pref()
574 enable_irq(info->gpmc_irq_count); in omap_nand_data_in_irq_pref()
575 enable_irq(info->gpmc_irq_fifo); in omap_nand_data_in_irq_pref()
578 wait_for_completion(&info->comp); in omap_nand_data_in_irq_pref()
581 omap_prefetch_reset(info->gpmc_cs, info); in omap_nand_data_in_irq_pref()
586 * omap_nand_data_out_irq_pref - NAND out using write posting and IRQ
593 struct mtd_info *mtd = nand_to_mtd(&info->nand); in omap_nand_data_out_irq_pref()
598 if (len <= mtd->oobsize || force_8bit) { in omap_nand_data_out_irq_pref()
603 info->iomode = OMAP_NAND_IO_WRITE; in omap_nand_data_out_irq_pref()
604 info->buf = (u_char *) buf; in omap_nand_data_out_irq_pref()
605 init_completion(&info->comp); in omap_nand_data_out_irq_pref()
608 ret = omap_prefetch_enable(info->gpmc_cs, in omap_nand_data_out_irq_pref()
616 info->buf_len = len; in omap_nand_data_out_irq_pref()
618 enable_irq(info->gpmc_irq_count); in omap_nand_data_out_irq_pref()
619 enable_irq(info->gpmc_irq_fifo); in omap_nand_data_out_irq_pref()
622 wait_for_completion(&info->comp); in omap_nand_data_out_irq_pref()
624 /* wait for data to flushed-out before reset the prefetch */ in omap_nand_data_out_irq_pref()
628 val = readl(info->reg.gpmc_prefetch_status); in omap_nand_data_out_irq_pref()
634 omap_prefetch_reset(info->gpmc_cs, info); in omap_nand_data_out_irq_pref()
639 * gen_true_ecc - This function will generate true ECC value
640 * @ecc_buf: buffer to store ecc code
642 * This generated true ECC value can be used when correcting
643 * data read from NAND flash memory core
659 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
660 * @ecc_data1: ecc code from nand spare area
661 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
664 * This function compares two ECC's and indicates if there is an error.
667 * was corrected, %1 is returned. Otherwise, %-1 is returned.
669 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ in omap_compare_ecc()
740 * ECC values are equal in omap_compare_ecc()
746 pr_debug("ECC UNCORRECTED_ERROR 1\n"); in omap_compare_ecc()
747 return -EBADMSG; in omap_compare_ecc()
750 /* UN-Correctable error */ in omap_compare_ecc()
751 pr_debug("ECC UNCORRECTED_ERROR B\n"); in omap_compare_ecc()
752 return -EBADMSG; in omap_compare_ecc()
768 pr_debug("Correcting single bit ECC error at offset: " in omap_compare_ecc()
782 return -EBADMSG; in omap_compare_ecc()
787 * omap_correct_data - Compares the ECC read with HW generated ECC
788 * @chip: NAND chip object
790 * @read_ecc: ecc read from nand flash
791 * @calc_ecc: ecc read from HW ECC registers
793 * Compares the ecc read from nand spare area with ECC registers values
794 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
797 * corrected errors is returned. If uncorrectable errors exist, %-1 is
808 if (info->nand.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST && in omap_correct_data()
809 info->nand.ecc.size == 2048) in omap_correct_data()
830 * omap_calculate_ecc - Generate non-inverted ECC bytes.
831 * @chip: NAND chip object
832 * @dat: The pointer to data on which ecc is computed
835 * Using noninverted ECC can be considered ugly since writing a blank
836 * page ie. padding will clear the ECC bytes. This is no problem as long
838 * an erased page will produce an ECC mismatch between generated and read
839 * ECC bytes that has to be dealt with separately.
847 val = readl(info->reg.gpmc_ecc_config); in omap_calculate_ecc()
848 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) in omap_calculate_ecc()
849 return -EINVAL; in omap_calculate_ecc()
851 /* read ecc result */ in omap_calculate_ecc()
852 val = readl(info->reg.gpmc_ecc1_result); in omap_calculate_ecc()
862 * omap_enable_hwecc - This function enables the hardware ecc functionality
863 * @chip: NAND chip object
864 * @mode: Read/Write mode
866 static void omap_enable_hwecc(struct nand_chip *chip, int mode) in omap_enable_hwecc() argument
869 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; in omap_enable_hwecc()
872 /* clear ecc and enable bits */ in omap_enable_hwecc()
874 writel(val, info->reg.gpmc_ecc_control); in omap_enable_hwecc()
876 /* program ecc and result sizes */ in omap_enable_hwecc()
877 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | in omap_enable_hwecc()
879 writel(val, info->reg.gpmc_ecc_size_config); in omap_enable_hwecc()
881 switch (mode) { in omap_enable_hwecc()
884 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); in omap_enable_hwecc()
887 writel(ECCCLEAR, info->reg.gpmc_ecc_control); in omap_enable_hwecc()
890 dev_info(&info->pdev->dev, in omap_enable_hwecc()
891 "error: unrecognized Mode[%d]!\n", mode); in omap_enable_hwecc()
895 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ in omap_enable_hwecc()
896 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); in omap_enable_hwecc()
897 writel(val, info->reg.gpmc_ecc_config); in omap_enable_hwecc()
901 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
902 * @chip: NAND chip object
903 * @mode: Read/Write mode
906 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
912 int mode) in omap_enable_hwecc_bch() argument
917 enum omap_ecc ecc_opt = info->ecc_opt; in omap_enable_hwecc_bch()
921 /* GPMC configurations for calculating ECC */ in omap_enable_hwecc_bch()
932 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
933 if (mode == NAND_ECC_READ) { in omap_enable_hwecc_bch()
952 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
953 if (mode == NAND_ECC_READ) { in omap_enable_hwecc_bch()
965 nsectors = chip->ecc.steps; in omap_enable_hwecc_bch()
966 if (mode == NAND_ECC_READ) { in omap_enable_hwecc_bch()
968 ecc_size0 = 52; /* ECC bits in nibbles per sector */ in omap_enable_hwecc_bch()
969 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ in omap_enable_hwecc_bch()
980 writel(ECC1, info->reg.gpmc_ecc_control); in omap_enable_hwecc_bch()
982 /* Configure ecc size for BCH */ in omap_enable_hwecc_bch()
984 writel(val, info->reg.gpmc_ecc_size_config); in omap_enable_hwecc_bch()
986 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; in omap_enable_hwecc_bch()
991 (wr_mode << 8) | /* wrap mode */ in omap_enable_hwecc_bch()
993 (((nsectors-1) & 0x7) << 4) | /* number of sectors */ in omap_enable_hwecc_bch()
994 (info->gpmc_cs << 1) | /* ECC CS */ in omap_enable_hwecc_bch()
995 (0x1)); /* enable ECC */ in omap_enable_hwecc_bch()
997 writel(val, info->reg.gpmc_ecc_config); in omap_enable_hwecc_bch()
999 /* Clear ecc and enable bits */ in omap_enable_hwecc_bch()
1000 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); in omap_enable_hwecc_bch()
1008 * _omap_calculate_ecc_bch - Generate ECC bytes for one sector
1010 * @dat: The pointer to data on which ecc is computed
1014 * Support calculating of BCH4/8/16 ECC vectors for one sector
1021 int eccbytes = info->nand.ecc.bytes; in _omap_calculate_ecc_bch()
1022 struct gpmc_nand_regs *gpmc_regs = &info->reg; in _omap_calculate_ecc_bch()
1029 switch (info->ecc_opt) { in _omap_calculate_ecc_bch()
1032 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); in _omap_calculate_ecc_bch()
1033 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); in _omap_calculate_ecc_bch()
1034 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]); in _omap_calculate_ecc_bch()
1035 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]); in _omap_calculate_ecc_bch()
1052 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); in _omap_calculate_ecc_bch()
1053 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); in _omap_calculate_ecc_bch()
1064 val = readl(gpmc_regs->gpmc_bch_result6[i]); in _omap_calculate_ecc_bch()
1067 val = readl(gpmc_regs->gpmc_bch_result5[i]); in _omap_calculate_ecc_bch()
1072 val = readl(gpmc_regs->gpmc_bch_result4[i]); in _omap_calculate_ecc_bch()
1077 val = readl(gpmc_regs->gpmc_bch_result3[i]); in _omap_calculate_ecc_bch()
1082 val = readl(gpmc_regs->gpmc_bch_result2[i]); in _omap_calculate_ecc_bch()
1087 val = readl(gpmc_regs->gpmc_bch_result1[i]); in _omap_calculate_ecc_bch()
1092 val = readl(gpmc_regs->gpmc_bch_result0[i]); in _omap_calculate_ecc_bch()
1099 return -EINVAL; in _omap_calculate_ecc_bch()
1102 /* ECC scheme specific syndrome customizations */ in _omap_calculate_ecc_bch()
1103 switch (info->ecc_opt) { in _omap_calculate_ecc_bch()
1106 * ECC of blank pages results in 0x0 on reading back in _omap_calculate_ecc_bch()
1112 /* Set 8th ECC byte as 0x0 for ROM compatibility */ in _omap_calculate_ecc_bch()
1113 ecc_calc[eccbytes - 1] = 0x0; in _omap_calculate_ecc_bch()
1117 * ECC of blank pages results in 0x0 on reading back in _omap_calculate_ecc_bch()
1123 /* Set 14th ECC byte as 0x0 for ROM compatibility */ in _omap_calculate_ecc_bch()
1124 ecc_calc[eccbytes - 1] = 0x0; in _omap_calculate_ecc_bch()
1129 return -EINVAL; in _omap_calculate_ecc_bch()
1136 * omap_calculate_ecc_bch_sw - ECC generator for sector for SW based correction
1137 * @chip: NAND chip object
1138 * @dat: The pointer to data on which ecc is computed
1139 * @ecc_calc: Buffer storing the calculated ECC bytes
1141 * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
1142 * when SW based correction is required as ECC is required for one sector
1152 * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
1154 * @dat: The pointer to data on which ecc is computed
1155 * @ecc_calc: Buffer storing the calculated ECC bytes
1157 * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
1163 int eccbytes = info->nand.ecc.bytes; in omap_calculate_ecc_bch_multi()
1167 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; in omap_calculate_ecc_bch_multi()
1180 * erased_sector_bitflips - count bit flips
1194 for (i = 0; i < info->nand.ecc.size; i++) { in erased_sector_bitflips()
1196 if (flip_bits > info->nand.ecc.strength) in erased_sector_bitflips()
1200 for (i = 0; i < info->nand.ecc.bytes - 1; i++) { in erased_sector_bitflips()
1202 if (flip_bits > info->nand.ecc.strength) in erased_sector_bitflips()
1211 memset(data, 0xFF, info->nand.ecc.size); in erased_sector_bitflips()
1212 memset(oob, 0xFF, info->nand.ecc.bytes); in erased_sector_bitflips()
1219 * omap_elm_correct_data - corrects page data area in case error reported
1220 * @chip: NAND chip object
1222 * @read_ecc: ecc read from nand flash
1223 * @calc_ecc: ecc read from HW ECC registers
1225 * Calculated ecc vector reported as zero in case of non-error pages.
1226 * In case of non-zero ecc vector, first filter out erased-pages, and
1227 * then process data via ELM to detect bit-flips.
1233 struct nand_ecc_ctrl *ecc = &info->nand.ecc; in omap_elm_correct_data() local
1234 int eccsteps = info->nsteps_per_eccpg; in omap_elm_correct_data()
1247 switch (info->ecc_opt) { in omap_elm_correct_data()
1249 /* omit 7th ECC byte reserved for ROM code compatibility */ in omap_elm_correct_data()
1250 actual_eccbytes = ecc->bytes - 1; in omap_elm_correct_data()
1254 /* omit 14th ECC byte reserved for ROM code compatibility */ in omap_elm_correct_data()
1255 actual_eccbytes = ecc->bytes - 1; in omap_elm_correct_data()
1259 actual_eccbytes = ecc->bytes; in omap_elm_correct_data()
1263 dev_err(&info->pdev->dev, "invalid driver configuration\n"); in omap_elm_correct_data()
1264 return -EINVAL; in omap_elm_correct_data()
1275 * In case of error, non zero ecc reported. in omap_elm_correct_data()
1279 eccflag = 1; /* non zero ecc, error present */ in omap_elm_correct_data()
1288 * calc_ecc[] matches pattern for ECC(all 0xff) in omap_elm_correct_data()
1289 * so this is definitely an erased-page in omap_elm_correct_data()
1292 buf = &data[info->nand.ecc.size * i]; in omap_elm_correct_data()
1294 * count number of 0-bits in read_buf. in omap_elm_correct_data()
1296 * check is introduced in generic NAND driver in omap_elm_correct_data()
1302 * number of 0-bits within ECC limits in omap_elm_correct_data()
1303 * So this may be an erased-page in omap_elm_correct_data()
1308 * Too many 0-bits. It may be a in omap_elm_correct_data()
1309 * - programmed-page, OR in omap_elm_correct_data()
1310 * - erased-page with many bit-flips in omap_elm_correct_data()
1319 /* Update the ecc vector */ in omap_elm_correct_data()
1320 calc_ecc += ecc->bytes; in omap_elm_correct_data()
1321 read_ecc += ecc->bytes; in omap_elm_correct_data()
1329 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); in omap_elm_correct_data()
1334 dev_err(&info->pdev->dev, in omap_elm_correct_data()
1335 "uncorrectable bit-flips found\n"); in omap_elm_correct_data()
1336 err = -EBADMSG; in omap_elm_correct_data()
1339 switch (info->ecc_opt) { in omap_elm_correct_data()
1350 return -EINVAL; in omap_elm_correct_data()
1352 error_max = (ecc->size + actual_eccbytes) * 8; in omap_elm_correct_data()
1357 byte_pos = (error_max - pos - 1) / 8; in omap_elm_correct_data()
1366 (byte_pos - 512), in omap_elm_correct_data()
1367 spare_ecc[byte_pos - 512]); in omap_elm_correct_data()
1368 spare_ecc[byte_pos - 512] ^= in omap_elm_correct_data()
1372 dev_err(&info->pdev->dev, in omap_elm_correct_data()
1373 "invalid bit-flip @ %d:%d\n", in omap_elm_correct_data()
1375 err = -EBADMSG; in omap_elm_correct_data()
1384 data += ecc->size; in omap_elm_correct_data()
1385 spare_ecc += ecc->bytes; in omap_elm_correct_data()
1392 * omap_write_page_bch - BCH ecc based write page function for entire page
1393 * @chip: nand chip info structure
1395 * @oob_required: must write chip->oob_poi to OOB
1405 uint8_t *ecc_calc = chip->ecc.calc_buf; in omap_write_page_bch()
1413 for (eccpg = 0; eccpg < info->neccpg; eccpg++) { in omap_write_page_bch()
1414 /* Enable GPMC ecc engine */ in omap_write_page_bch()
1415 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in omap_write_page_bch()
1418 info->data_out(chip, buf + (eccpg * info->eccpg_size), in omap_write_page_bch()
1419 info->eccpg_size, false); in omap_write_page_bch()
1421 /* Update ecc vector from GPMC result registers */ in omap_write_page_bch()
1423 buf + (eccpg * info->eccpg_size), in omap_write_page_bch()
1429 chip->oob_poi, in omap_write_page_bch()
1430 eccpg * info->eccpg_bytes, in omap_write_page_bch()
1431 info->eccpg_bytes); in omap_write_page_bch()
1436 /* Write ecc vector to OOB area */ in omap_write_page_bch()
1437 info->data_out(chip, chip->oob_poi, mtd->oobsize, false); in omap_write_page_bch()
1443 * omap_write_subpage_bch - BCH hardware ECC based subpage write
1444 * @chip: nand chip info structure
1448 * @oob_required: must write chip->oob_poi to OOB
1459 u8 *ecc_calc = chip->ecc.calc_buf; in omap_write_subpage_bch()
1460 int ecc_size = chip->ecc.size; in omap_write_subpage_bch()
1461 int ecc_bytes = chip->ecc.bytes; in omap_write_subpage_bch()
1463 u32 end_step = (offset + data_len - 1) / ecc_size; in omap_write_subpage_bch()
1469 * as ECC is calculated by hardware. in omap_write_subpage_bch()
1470 * ECC is calculated for all subpages but we choose in omap_write_subpage_bch()
1477 for (eccpg = 0; eccpg < info->neccpg; eccpg++) { in omap_write_subpage_bch()
1478 /* Enable GPMC ECC engine */ in omap_write_subpage_bch()
1479 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in omap_write_subpage_bch()
1482 info->data_out(chip, buf + (eccpg * info->eccpg_size), in omap_write_subpage_bch()
1483 info->eccpg_size, false); in omap_write_subpage_bch()
1485 for (step = 0; step < info->nsteps_per_eccpg; step++) { in omap_write_subpage_bch()
1486 unsigned int base_step = eccpg * info->nsteps_per_eccpg; in omap_write_subpage_bch()
1487 const u8 *bufoffs = buf + (eccpg * info->eccpg_size); in omap_write_subpage_bch()
1489 /* Mask ECC of un-touched subpages with 0xFFs */ in omap_write_subpage_bch()
1505 * Copy the calculated ECC for the whole page including the in omap_write_subpage_bch()
1508 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, in omap_write_subpage_bch()
1509 eccpg * info->eccpg_bytes, in omap_write_subpage_bch()
1510 info->eccpg_bytes); in omap_write_subpage_bch()
1515 /* write OOB buffer to NAND device */ in omap_write_subpage_bch()
1516 info->data_out(chip, chip->oob_poi, mtd->oobsize, false); in omap_write_subpage_bch()
1522 * omap_read_page_bch - BCH ecc based page read function for entire page
1523 * @chip: nand chip info structure
1525 * @oob_required: caller requires OOB data read to chip->oob_poi
1528 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1532 * ecc engine enabled. ecc vector updated after read of OOB data.
1533 * For non error pages ecc vector reported as zero.
1540 uint8_t *ecc_calc = chip->ecc.calc_buf; in omap_read_page_bch()
1541 uint8_t *ecc_code = chip->ecc.code_buf; in omap_read_page_bch()
1549 for (eccpg = 0; eccpg < info->neccpg; eccpg++) { in omap_read_page_bch()
1550 /* Enable GPMC ecc engine */ in omap_read_page_bch()
1551 chip->ecc.hwctl(chip, NAND_ECC_READ); in omap_read_page_bch()
1554 ret = nand_change_read_column_op(chip, eccpg * info->eccpg_size, in omap_read_page_bch()
1555 buf + (eccpg * info->eccpg_size), in omap_read_page_bch()
1556 info->eccpg_size, false); in omap_read_page_bch()
1562 mtd->writesize + BBM_LEN + in omap_read_page_bch()
1563 (eccpg * info->eccpg_bytes), in omap_read_page_bch()
1564 chip->oob_poi + BBM_LEN + in omap_read_page_bch()
1565 (eccpg * info->eccpg_bytes), in omap_read_page_bch()
1566 info->eccpg_bytes, false); in omap_read_page_bch()
1570 /* Calculate ecc bytes */ in omap_read_page_bch()
1572 buf + (eccpg * info->eccpg_size), in omap_read_page_bch()
1578 chip->oob_poi, in omap_read_page_bch()
1579 eccpg * info->eccpg_bytes, in omap_read_page_bch()
1580 info->eccpg_bytes); in omap_read_page_bch()
1584 stat = chip->ecc.correct(chip, in omap_read_page_bch()
1585 buf + (eccpg * info->eccpg_size), in omap_read_page_bch()
1588 mtd->ecc_stats.failed++; in omap_read_page_bch()
1590 mtd->ecc_stats.corrected += stat; in omap_read_page_bch()
1599 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1600 * @info: NAND device structure containing platform data
1608 /* check whether elm-id is passed via DT */ in is_elm_present()
1610 dev_err(&info->pdev->dev, "ELM devicetree node not found\n"); in is_elm_present()
1616 dev_err(&info->pdev->dev, "ELM device not found\n"); in is_elm_present()
1620 info->elm_dev = &pdev->dev; in is_elm_present()
1628 switch (info->ecc_opt) { in omap2_nand_ecc_check()
1650 dev_err(&info->pdev->dev, in omap2_nand_ecc_check()
1655 dev_err(&info->pdev->dev, in omap2_nand_ecc_check()
1659 if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) { in omap2_nand_ecc_check()
1660 dev_err(&info->pdev->dev, "ELM not available\n"); in omap2_nand_ecc_check()
1668 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1670 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1671 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1676 struct device_node *child = dev->of_node; in omap_get_dt_info()
1683 return -EINVAL; in omap_get_dt_info()
1686 info->gpmc_cs = cs; in omap_get_dt_info()
1688 /* detect availability of ELM module. Won't be present pre-OMAP4 */ in omap_get_dt_info()
1689 info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); in omap_get_dt_info()
1690 if (!info->elm_of_node) { in omap_get_dt_info()
1691 info->elm_of_node = of_parse_phandle(child, "elm_id", 0); in omap_get_dt_info()
1692 if (!info->elm_of_node) in omap_get_dt_info()
1693 dev_dbg(dev, "ti,elm-id not in DT\n"); in omap_get_dt_info()
1696 /* select ecc-scheme for NAND */ in omap_get_dt_info()
1697 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { in omap_get_dt_info()
1698 dev_err(dev, "ti,nand-ecc-opt not found\n"); in omap_get_dt_info()
1699 return -EINVAL; in omap_get_dt_info()
1703 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW; in omap_get_dt_info()
1705 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) { in omap_get_dt_info()
1706 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW; in omap_get_dt_info()
1708 if (info->elm_of_node) in omap_get_dt_info()
1709 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW; in omap_get_dt_info()
1711 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; in omap_get_dt_info()
1713 if (info->elm_of_node) in omap_get_dt_info()
1714 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW; in omap_get_dt_info()
1716 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; in omap_get_dt_info()
1718 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW; in omap_get_dt_info()
1720 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n"); in omap_get_dt_info()
1721 return -EINVAL; in omap_get_dt_info()
1724 /* select data transfer mode */ in omap_get_dt_info()
1725 if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) { in omap_get_dt_info()
1728 info->xfer_type = i; in omap_get_dt_info()
1733 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n"); in omap_get_dt_info()
1734 return -EINVAL; in omap_get_dt_info()
1744 struct nand_chip *chip = &info->nand; in omap_ooblayout_ecc()
1747 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && in omap_ooblayout_ecc()
1748 !(chip->options & NAND_BUSWIDTH_16)) in omap_ooblayout_ecc()
1752 return -ERANGE; in omap_ooblayout_ecc()
1754 oobregion->offset = off; in omap_ooblayout_ecc()
1755 oobregion->length = chip->ecc.total; in omap_ooblayout_ecc()
1764 struct nand_chip *chip = &info->nand; in omap_ooblayout_free()
1767 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && in omap_ooblayout_free()
1768 !(chip->options & NAND_BUSWIDTH_16)) in omap_ooblayout_free()
1772 return -ERANGE; in omap_ooblayout_free()
1774 off += chip->ecc.total; in omap_ooblayout_free()
1775 if (off >= mtd->oobsize) in omap_ooblayout_free()
1776 return -ERANGE; in omap_ooblayout_free()
1778 oobregion->offset = off; in omap_ooblayout_free()
1779 oobregion->length = mtd->oobsize - off; in omap_ooblayout_free()
1785 .ecc = omap_ooblayout_ecc,
1792 struct nand_device *nand = mtd_to_nanddev(mtd); in omap_sw_ooblayout_ecc() local
1793 unsigned int nsteps = nanddev_get_ecc_nsteps(nand); in omap_sw_ooblayout_ecc()
1794 unsigned int ecc_bytes = nanddev_get_ecc_bytes_per_step(nand); in omap_sw_ooblayout_ecc()
1798 return -ERANGE; in omap_sw_ooblayout_ecc()
1802 * reserved after each ECC step. in omap_sw_ooblayout_ecc()
1804 oobregion->offset = off + (section * (ecc_bytes + 1)); in omap_sw_ooblayout_ecc()
1805 oobregion->length = ecc_bytes; in omap_sw_ooblayout_ecc()
1813 struct nand_device *nand = mtd_to_nanddev(mtd); in omap_sw_ooblayout_free() local
1814 unsigned int nsteps = nanddev_get_ecc_nsteps(nand); in omap_sw_ooblayout_free()
1815 unsigned int ecc_bytes = nanddev_get_ecc_bytes_per_step(nand); in omap_sw_ooblayout_free()
1819 return -ERANGE; in omap_sw_ooblayout_free()
1823 * reserved after each ECC step. in omap_sw_ooblayout_free()
1826 if (off >= mtd->oobsize) in omap_sw_ooblayout_free()
1827 return -ERANGE; in omap_sw_ooblayout_free()
1829 oobregion->offset = off; in omap_sw_ooblayout_free()
1830 oobregion->length = mtd->oobsize - off; in omap_sw_ooblayout_free()
1836 .ecc = omap_sw_ooblayout_ecc,
1844 struct device *dev = &info->pdev->dev; in omap_nand_attach_chip()
1846 int elm_bch_strength = -1; in omap_nand_attach_chip()
1851 if (chip->bbt_options & NAND_BBT_USE_FLASH) in omap_nand_attach_chip()
1852 chip->bbt_options |= NAND_BBT_NO_OOB; in omap_nand_attach_chip()
1854 chip->options |= NAND_SKIP_BBTSCAN; in omap_nand_attach_chip()
1856 /* Re-populate low-level callbacks based on xfer modes */ in omap_nand_attach_chip()
1857 switch (info->xfer_type) { in omap_nand_attach_chip()
1859 info->data_in = omap_nand_data_in_pref; in omap_nand_attach_chip()
1860 info->data_out = omap_nand_data_out_pref; in omap_nand_attach_chip()
1870 info->dma = dma_request_chan(dev->parent, "rxtx"); in omap_nand_attach_chip()
1872 if (IS_ERR(info->dma)) { in omap_nand_attach_chip()
1874 return PTR_ERR(info->dma); in omap_nand_attach_chip()
1879 cfg.src_addr = info->phys_base; in omap_nand_attach_chip()
1880 cfg.dst_addr = info->phys_base; in omap_nand_attach_chip()
1885 err = dmaengine_slave_config(info->dma, &cfg); in omap_nand_attach_chip()
1893 info->data_in = omap_nand_data_in_dma_pref; in omap_nand_attach_chip()
1894 info->data_out = omap_nand_data_out_dma_pref; in omap_nand_attach_chip()
1899 info->gpmc_irq_fifo = platform_get_irq(info->pdev, 0); in omap_nand_attach_chip()
1900 if (info->gpmc_irq_fifo < 0) in omap_nand_attach_chip()
1901 return info->gpmc_irq_fifo; in omap_nand_attach_chip()
1902 err = devm_request_irq(dev, info->gpmc_irq_fifo, in omap_nand_attach_chip()
1904 "gpmc-nand-fifo", info); in omap_nand_attach_chip()
1907 info->gpmc_irq_fifo, err); in omap_nand_attach_chip()
1908 info->gpmc_irq_fifo = 0; in omap_nand_attach_chip()
1912 info->gpmc_irq_count = platform_get_irq(info->pdev, 1); in omap_nand_attach_chip()
1913 if (info->gpmc_irq_count < 0) in omap_nand_attach_chip()
1914 return info->gpmc_irq_count; in omap_nand_attach_chip()
1915 err = devm_request_irq(dev, info->gpmc_irq_count, in omap_nand_attach_chip()
1917 "gpmc-nand-count", info); in omap_nand_attach_chip()
1920 info->gpmc_irq_count, err); in omap_nand_attach_chip()
1921 info->gpmc_irq_count = 0; in omap_nand_attach_chip()
1925 info->data_in = omap_nand_data_in_irq_pref; in omap_nand_attach_chip()
1926 info->data_out = omap_nand_data_out_irq_pref; in omap_nand_attach_chip()
1930 dev_err(dev, "xfer_type %d not supported!\n", info->xfer_type); in omap_nand_attach_chip()
1931 return -EINVAL; in omap_nand_attach_chip()
1935 return -EINVAL; in omap_nand_attach_chip()
1941 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) { in omap_nand_attach_chip()
1942 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in omap_nand_attach_chip()
1943 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in omap_nand_attach_chip()
1947 /* Populate MTD interface based on ECC scheme */ in omap_nand_attach_chip()
1948 switch (info->ecc_opt) { in omap_nand_attach_chip()
1950 dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n"); in omap_nand_attach_chip()
1951 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in omap_nand_attach_chip()
1952 chip->ecc.bytes = 3; in omap_nand_attach_chip()
1953 chip->ecc.size = 512; in omap_nand_attach_chip()
1954 chip->ecc.strength = 1; in omap_nand_attach_chip()
1955 chip->ecc.calculate = omap_calculate_ecc; in omap_nand_attach_chip()
1956 chip->ecc.hwctl = omap_enable_hwecc; in omap_nand_attach_chip()
1957 chip->ecc.correct = omap_correct_data; in omap_nand_attach_chip()
1959 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
1961 if (!(chip->options & NAND_BUSWIDTH_16)) in omap_nand_attach_chip()
1967 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); in omap_nand_attach_chip()
1968 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in omap_nand_attach_chip()
1969 chip->ecc.size = 512; in omap_nand_attach_chip()
1970 chip->ecc.bytes = 7; in omap_nand_attach_chip()
1971 chip->ecc.strength = 4; in omap_nand_attach_chip()
1972 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
1973 chip->ecc.correct = rawnand_sw_bch_correct; in omap_nand_attach_chip()
1974 chip->ecc.calculate = omap_calculate_ecc_bch_sw; in omap_nand_attach_chip()
1977 oobbytes_per_step = chip->ecc.bytes + 1; in omap_nand_attach_chip()
1987 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); in omap_nand_attach_chip()
1988 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in omap_nand_attach_chip()
1989 chip->ecc.size = 512; in omap_nand_attach_chip()
1990 /* 14th bit is kept reserved for ROM-code compatibility */ in omap_nand_attach_chip()
1991 chip->ecc.bytes = 7 + 1; in omap_nand_attach_chip()
1992 chip->ecc.strength = 4; in omap_nand_attach_chip()
1993 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
1994 chip->ecc.correct = omap_elm_correct_data; in omap_nand_attach_chip()
1995 chip->ecc.read_page = omap_read_page_bch; in omap_nand_attach_chip()
1996 chip->ecc.write_page = omap_write_page_bch; in omap_nand_attach_chip()
1997 chip->ecc.write_subpage = omap_write_subpage_bch; in omap_nand_attach_chip()
1999 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
2004 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); in omap_nand_attach_chip()
2005 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in omap_nand_attach_chip()
2006 chip->ecc.size = 512; in omap_nand_attach_chip()
2007 chip->ecc.bytes = 13; in omap_nand_attach_chip()
2008 chip->ecc.strength = 8; in omap_nand_attach_chip()
2009 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2010 chip->ecc.correct = rawnand_sw_bch_correct; in omap_nand_attach_chip()
2011 chip->ecc.calculate = omap_calculate_ecc_bch_sw; in omap_nand_attach_chip()
2014 oobbytes_per_step = chip->ecc.bytes + 1; in omap_nand_attach_chip()
2024 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); in omap_nand_attach_chip()
2025 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in omap_nand_attach_chip()
2026 chip->ecc.size = 512; in omap_nand_attach_chip()
2027 /* 14th bit is kept reserved for ROM-code compatibility */ in omap_nand_attach_chip()
2028 chip->ecc.bytes = 13 + 1; in omap_nand_attach_chip()
2029 chip->ecc.strength = 8; in omap_nand_attach_chip()
2030 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2031 chip->ecc.correct = omap_elm_correct_data; in omap_nand_attach_chip()
2032 chip->ecc.read_page = omap_read_page_bch; in omap_nand_attach_chip()
2033 chip->ecc.write_page = omap_write_page_bch; in omap_nand_attach_chip()
2034 chip->ecc.write_subpage = omap_write_subpage_bch; in omap_nand_attach_chip()
2036 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
2041 pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); in omap_nand_attach_chip()
2042 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in omap_nand_attach_chip()
2043 chip->ecc.size = 512; in omap_nand_attach_chip()
2044 chip->ecc.bytes = 26; in omap_nand_attach_chip()
2045 chip->ecc.strength = 16; in omap_nand_attach_chip()
2046 chip->ecc.hwctl = omap_enable_hwecc_bch; in omap_nand_attach_chip()
2047 chip->ecc.correct = omap_elm_correct_data; in omap_nand_attach_chip()
2048 chip->ecc.read_page = omap_read_page_bch; in omap_nand_attach_chip()
2049 chip->ecc.write_page = omap_write_page_bch; in omap_nand_attach_chip()
2050 chip->ecc.write_subpage = omap_write_subpage_bch; in omap_nand_attach_chip()
2052 oobbytes_per_step = chip->ecc.bytes; in omap_nand_attach_chip()
2056 dev_err(dev, "Invalid or unsupported ECC scheme\n"); in omap_nand_attach_chip()
2057 return -EINVAL; in omap_nand_attach_chip()
2061 chip->ecc.steps = mtd->writesize / chip->ecc.size; in omap_nand_attach_chip()
2062 info->neccpg = chip->ecc.steps / ERROR_VECTOR_MAX; in omap_nand_attach_chip()
2063 if (info->neccpg) { in omap_nand_attach_chip()
2064 info->nsteps_per_eccpg = ERROR_VECTOR_MAX; in omap_nand_attach_chip()
2066 info->neccpg = 1; in omap_nand_attach_chip()
2067 info->nsteps_per_eccpg = chip->ecc.steps; in omap_nand_attach_chip()
2069 info->eccpg_size = info->nsteps_per_eccpg * chip->ecc.size; in omap_nand_attach_chip()
2070 info->eccpg_bytes = info->nsteps_per_eccpg * chip->ecc.bytes; in omap_nand_attach_chip()
2072 err = elm_config(info->elm_dev, elm_bch_strength, in omap_nand_attach_chip()
2073 info->nsteps_per_eccpg, chip->ecc.size, in omap_nand_attach_chip()
2074 chip->ecc.bytes); in omap_nand_attach_chip()
2079 /* Check if NAND device's OOB is enough to store ECC signatures */ in omap_nand_attach_chip()
2081 (mtd->writesize / chip->ecc.size)); in omap_nand_attach_chip()
2082 if (mtd->oobsize < min_oobbytes) { in omap_nand_attach_chip()
2085 min_oobbytes, mtd->oobsize); in omap_nand_attach_chip()
2086 return -EINVAL; in omap_nand_attach_chip()
2099 ioread8_rep(info->fifo, buf, len); in omap_nand_data_in()
2101 ioread16_rep(info->fifo, buf, len >> 1); in omap_nand_data_in()
2103 ioread32_rep(info->fifo, buf, len >> 2); in omap_nand_data_in()
2114 iowrite8_rep(info->fifo, buf, len); in omap_nand_data_out()
2116 iowrite16_rep(info->fifo, buf, len >> 1); in omap_nand_data_out()
2118 iowrite32_rep(info->fifo, buf, len >> 2); in omap_nand_data_out()
2128 switch (instr->type) { in omap_nand_exec_instr()
2130 iowrite8(instr->ctx.cmd.opcode, in omap_nand_exec_instr()
2131 info->reg.gpmc_nand_command); in omap_nand_exec_instr()
2135 for (i = 0; i < instr->ctx.addr.naddrs; i++) { in omap_nand_exec_instr()
2136 iowrite8(instr->ctx.addr.addrs[i], in omap_nand_exec_instr()
2137 info->reg.gpmc_nand_address); in omap_nand_exec_instr()
2142 info->data_in(chip, instr->ctx.data.buf.in, in omap_nand_exec_instr()
2143 instr->ctx.data.len, in omap_nand_exec_instr()
2144 instr->ctx.data.force_8bit); in omap_nand_exec_instr()
2148 info->data_out(chip, instr->ctx.data.buf.out, in omap_nand_exec_instr()
2149 instr->ctx.data.len, in omap_nand_exec_instr()
2150 instr->ctx.data.force_8bit); in omap_nand_exec_instr()
2154 ret = info->ready_gpiod ? in omap_nand_exec_instr()
2155 nand_gpio_waitrdy(chip, info->ready_gpiod, instr->ctx.waitrdy.timeout_ms) : in omap_nand_exec_instr()
2156 nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms); in omap_nand_exec_instr()
2162 if (instr->delay_ns) in omap_nand_exec_instr()
2163 ndelay(instr->delay_ns); in omap_nand_exec_instr()
2177 for (i = 0; i < op->ninstrs; i++) { in omap_nand_exec_op()
2180 ret = omap_nand_exec_instr(chip, &op->instrs[i]); in omap_nand_exec_op()
2193 /* Shared among all NAND instances to synchronize access to the ECC Engine */
2204 struct device *dev = &pdev->dev; in omap_nand_probe()
2207 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), in omap_nand_probe()
2210 return -ENOMEM; in omap_nand_probe()
2212 info->pdev = pdev; in omap_nand_probe()
2218 info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs); in omap_nand_probe()
2219 if (!info->ops) { in omap_nand_probe()
2220 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n"); in omap_nand_probe()
2221 return -ENODEV; in omap_nand_probe()
2224 nand_chip = &info->nand; in omap_nand_probe()
2226 mtd->dev.parent = &pdev->dev; in omap_nand_probe()
2227 nand_set_flash_node(nand_chip, dev->of_node); in omap_nand_probe()
2229 if (!mtd->name) { in omap_nand_probe()
2230 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, in omap_nand_probe()
2231 "omap2-nand.%d", info->gpmc_cs); in omap_nand_probe()
2232 if (!mtd->name) { in omap_nand_probe()
2233 dev_err(&pdev->dev, "Failed to set MTD name\n"); in omap_nand_probe()
2234 return -ENOMEM; in omap_nand_probe()
2242 info->fifo = vaddr; in omap_nand_probe()
2243 info->phys_base = res->start; in omap_nand_probe()
2251 nand_chip->controller = &omap_gpmc_controller; in omap_nand_probe()
2253 info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb", in omap_nand_probe()
2255 if (IS_ERR(info->ready_gpiod)) { in omap_nand_probe()
2257 return PTR_ERR(info->ready_gpiod); in omap_nand_probe()
2260 if (info->flash_bbt) in omap_nand_probe()
2261 nand_chip->bbt_options |= NAND_BBT_USE_FLASH; in omap_nand_probe()
2264 info->data_in = omap_nand_data_in; in omap_nand_probe()
2265 info->data_out = omap_nand_data_out; in omap_nand_probe()
2283 if (!IS_ERR_OR_NULL(info->dma)) in omap_nand_probe()
2284 dma_release_channel(info->dma); in omap_nand_probe()
2299 if (info->dma) in omap_nand_remove()
2300 dma_release_channel(info->dma); in omap_nand_remove()
2305 /* omap_nand_ids defined in linux/platform_data/mtd-nand-omap2.h */
2321 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");