Lines Matching +full:nand +full:- +full:ecc +full:- +full:algo
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
17 #include <linux/memory/ti-aemif.h>
30 /* 4-bit ECC syndrome registers */
42 * for ALE/CLE unless they support booting from NAND.
56 * 0-indexed chip-select number of the asynchronous
57 * interface to which the NAND device has been connected.
59 * So, if you have NAND connected to CS3 of DA850, you
74 * on-die == NAND_ECC_ENGINE_TYPE_ON_DIE
77 * All DaVinci-family chips support 1-bit hardware ECC.
78 * Newer ones also support 4-bit ECC, but are awkward
96 * This is a device driver for the NAND flash controller found on the
101 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
102 * available on chips like the DM355 and OMAP-L137 and needed with the
103 * more error-prone MLC NAND chips.
105 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
106 * outputs in a "wire-AND" configuration, with no per-chip signals.
142 return __raw_readl(info->base + offset);
148 __raw_writel(value, info->base + offset);
151 /*----------------------------------------------------------------------*/
154 * 1-bit hardware ECC ... context maintained for each core chipselect
162 + 4 * info->core_chipsel);
173 /* Reset ECC hardware */
178 /* Restart ECC hardware */
180 nandcfr |= BIT(8 + info->core_chipsel);
187 * Read hardware ECC value and pack into three bytes
195 /* invert so that erased block ecc is correct */
216 if ((diff >> (12 + 3)) < chip->ecc.size) {
220 return -EBADMSG;
222 } else if (!(diff & (diff - 1))) {
223 /* Single bit ECC error in the ECC itself,
228 return -EBADMSG;
235 /*----------------------------------------------------------------------*/
238 * 4-bit hardware ECC ... context maintained over entire AEMIF
243 * Also, and specific to this hardware, it ECC-protects the "prepad"
244 * in the OOB ... while having ECC protection for parts of OOB would
246 * OOB without recomputing ECC.
255 /* Reset ECC hardware */
260 /* Start 4-bit ECC calculation for read/write */
263 val |= (info->core_chipsel << 4) | BIT(12);
266 info->is_readmode = (mode == NAND_ECC_READ);
271 /* Read raw ECC code after writing to NAND. */
283 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
291 /* After a read, terminate ECC calculation by a dummy read
292 * of some 4-bit ECC register. ECC covers everything that
296 if (info->is_readmode) {
301 /* Pack eight raw 10-bit ecc values into ten bytes, making
303 * lower halves of two 32-bit words) into five bytes. The
334 * little-endian, and use type punning for less shifting/masking.
337 return -EINVAL;
349 /* Tell ECC controller about the expected ECC codes. */
350 for (i = 7; i >= 0; i--)
380 * long as ECC_STATE reads less than 4. After that, ECC HW has entered
399 return -EBADMSG;
432 error_address = (512 + 7) - error_address;
443 /*----------------------------------------------------------------------*/
445 /* An ECC layout for using 4-bit ECC with small-page flash, storing
446 * ten ECC bytes plus the manufacturer's bad block marker byte, and
453 return -ERANGE;
456 oobregion->offset = 0;
457 oobregion->length = 5;
459 oobregion->offset = 6;
460 oobregion->length = 2;
462 oobregion->offset = 13;
463 oobregion->length = 3;
473 return -ERANGE;
476 oobregion->offset = 8;
477 oobregion->length = 5;
479 oobregion->offset = 16;
480 oobregion->length = mtd->oobsize - 16;
487 .ecc = hwecc4_ooblayout_small_ecc,
494 struct nand_device *nand = mtd_to_nanddev(mtd);
495 unsigned int total_ecc_bytes = nand->ecc.ctx.total;
499 return -ERANGE;
501 oobregion->offset = (section * 16) + 6;
502 oobregion->length = 10;
510 struct nand_device *nand = mtd_to_nanddev(mtd);
511 unsigned int total_ecc_bytes = nand->ecc.ctx.total;
515 if (section >= (nregions - 1))
516 return -ERANGE;
518 oobregion->offset = ((section + 1) * 16);
519 oobregion->length = 6;
525 .ecc = hwecc4_ooblayout_large_ecc,
531 {.compatible = "ti,davinci-nand", },
532 {.compatible = "ti,keystone-nand", },
540 if (!dev_get_platdata(&pdev->dev)) {
545 pdata = devm_kzalloc(&pdev->dev,
548 pdev->dev.platform_data = pdata;
550 return ERR_PTR(-ENOMEM);
551 if (!device_property_read_u32(&pdev->dev,
552 "ti,davinci-chipselect", &prop))
553 pdata->core_chipsel = prop;
555 return ERR_PTR(-EINVAL);
557 if (!device_property_read_u32(&pdev->dev,
558 "ti,davinci-mask-ale", &prop))
559 pdata->mask_ale = prop;
560 if (!device_property_read_u32(&pdev->dev,
561 "ti,davinci-mask-cle", &prop))
562 pdata->mask_cle = prop;
563 if (!device_property_read_u32(&pdev->dev,
564 "ti,davinci-mask-chipsel", &prop))
565 pdata->mask_chipsel = prop;
566 if (!device_property_read_string(&pdev->dev,
567 "ti,davinci-ecc-mode",
570 pdata->engine_type = NAND_ECC_ENGINE_TYPE_NONE;
572 pdata->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
574 pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
575 if (!strncmp("on-die", mode, 6))
576 pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE;
578 if (!device_property_read_u32(&pdev->dev,
579 "ti,davinci-ecc-bits", &prop))
580 pdata->ecc_bits = prop;
582 if (!device_property_read_u32(&pdev->dev,
583 "ti,davinci-nand-buswidth",
585 pdata->options |= NAND_BUSWIDTH_16;
587 if (device_property_read_bool(&pdev->dev,
588 "ti,davinci-nand-use-bbt"))
589 pdata->bbt_options = NAND_BBT_USE_FLASH;
593 * use of 4-bit hardware ECC with subpages and verified on
596 * existing UBI partitions, sub-page writes are not being
599 * then use "ti,davinci-nand" as the compatible in your
600 * device-tree file.
602 if (device_is_compatible(&pdev->dev, "ti,keystone-nand"))
603 pdata->options |= NAND_NO_SUBPAGE_WRITE;
606 return dev_get_platdata(&pdev->dev);
612 return dev_get_platdata(&pdev->dev);
620 struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev);
626 /* Use board-specific ECC config */
627 chip->ecc.engine_type = pdata->engine_type;
628 chip->ecc.placement = pdata->ecc_placement;
630 switch (chip->ecc.engine_type) {
633 pdata->ecc_bits = 0;
636 pdata->ecc_bits = 0;
638 * This driver expects Hamming based ECC when engine_type is set
639 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to
640 * NAND_ECC_ALGO_HAMMING to avoid adding an extra ->ecc_algo
643 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
646 if (pdata->ecc_bits == 4) {
647 int chunks = mtd->writesize / 512;
649 if (!chunks || mtd->oobsize < 16) {
650 dev_dbg(&info->pdev->dev, "too small\n");
651 return -EINVAL;
659 /* No sharing 4-bit hardware between chipselects yet */
662 ret = -EBUSY;
667 if (ret == -EBUSY)
670 chip->ecc.calculate = nand_davinci_calculate_4bit;
671 chip->ecc.correct = nand_davinci_correct_4bit;
672 chip->ecc.hwctl = nand_davinci_hwctl_4bit;
673 chip->ecc.bytes = 10;
674 chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
675 chip->ecc.algo = NAND_ECC_ALGO_BCH;
678 * Update ECC layout if needed ... for 1-bit HW ECC, the
680 * are needed (for each 512 bytes). For 4-bit HW ECC,
691 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
693 if (chip->options & NAND_IS_BOOT_MEDIUM)
698 return -EIO;
701 /* 1bit ecc hamming */
702 chip->ecc.calculate = nand_davinci_calculate_1bit;
703 chip->ecc.correct = nand_davinci_correct_1bit;
704 chip->ecc.hwctl = nand_davinci_hwctl_1bit;
705 chip->ecc.bytes = 3;
706 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
708 chip->ecc.size = 512;
709 chip->ecc.strength = pdata->ecc_bits;
712 return -EINVAL;
724 ioread8_rep(info->current_cs, buf, len);
726 ioread16_rep(info->current_cs, buf, len >> 1);
728 ioread32_rep(info->current_cs, buf, len >> 2);
738 iowrite8_rep(info->current_cs, buf, len);
740 iowrite16_rep(info->current_cs, buf, len >> 1);
742 iowrite32_rep(info->current_cs, buf, len >> 2);
752 switch (instr->type) {
754 iowrite8(instr->ctx.cmd.opcode,
755 info->current_cs + info->mask_cle);
759 for (i = 0; i < instr->ctx.addr.naddrs; i++) {
760 iowrite8(instr->ctx.addr.addrs[i],
761 info->current_cs + info->mask_ale);
766 nand_davinci_data_in(info, instr->ctx.data.buf.in,
767 instr->ctx.data.len,
768 instr->ctx.data.force_8bit);
772 nand_davinci_data_out(info, instr->ctx.data.buf.out,
773 instr->ctx.data.len,
774 instr->ctx.data.force_8bit);
778 timeout_us = instr->ctx.waitrdy.timeout_ms * 1000;
779 ret = readl_relaxed_poll_timeout(info->base + NANDFSR_OFFSET,
788 if (instr->delay_ns) {
791 ndelay(instr->delay_ns);
807 info->current_cs = info->vaddr + (op->cs * info->mask_chipsel);
809 for (i = 0; i < op->ninstrs; i++) {
812 ret = davinci_nand_exec_instr(info, &op->instrs[i]);
831 cyc_ns = 1000000000 / clk_get_rate(info->clk);
837 cfg = TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1;
840 cfg = max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns),
841 TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1;
844 min = TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2;
848 cfg = TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1;
851 min = TO_CYCLES(sdr->tRC_min, cyc_ns) - 3;
855 cfg = TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 1000), cyc_ns);
856 cfg = max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1;
859 cfg = TO_CYCLES(sdr->tWP_min, cyc_ns) - 1;
862 cfg = max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tALS_min, cyc_ns));
863 cfg = max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1;
866 min = TO_CYCLES(sdr->tDS_min, cyc_ns) - 2;
870 cfg = max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tALH_min, cyc_ns));
871 cfg = max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns));
872 cfg = max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1;
875 min = TO_CYCLES(sdr->tWC_min, cyc_ns) - 2;
879 dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n",
881 dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta);
882 dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n",
889 return aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings);
914 /* insist on board-specific configuration */
916 return -ENODEV;
919 if (pdata->core_chipsel > 3)
920 return -ENODEV;
922 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
924 return -ENOMEM;
931 dev_err(&pdev->dev, "resource missing\n");
932 return -EINVAL;
935 vaddr = devm_ioremap_resource(&pdev->dev, res1);
940 * This registers range is used to setup NAND settings. In case with
943 * The AEMIF and NAND drivers not use the same registers in this range.
945 base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
947 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
948 return -EADDRNOTAVAIL;
951 info->clk = devm_clk_get_enabled(&pdev->dev, "aemif");
952 if (IS_ERR(info->clk))
953 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed to get clock");
955 info->pdev = pdev;
956 info->base = base;
957 info->vaddr = vaddr;
958 info->aemif = dev_get_drvdata(pdev->dev.parent);
960 mtd = nand_to_mtd(&info->chip);
961 mtd->dev.parent = &pdev->dev;
962 nand_set_flash_node(&info->chip, pdev->dev.of_node);
965 info->chip.bbt_options = pdata->bbt_options;
966 /* options such as 16-bit widths */
967 info->chip.options = pdata->options;
968 info->chip.bbt_td = pdata->bbt_td;
969 info->chip.bbt_md = pdata->bbt_md;
971 info->current_cs = info->vaddr;
972 info->core_chipsel = pdata->core_chipsel;
973 info->mask_chipsel = pdata->mask_chipsel;
975 /* use nandboot-capable ALE/CLE masks by default */
976 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
977 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
981 /* put CSxNAND into NAND mode */
983 val |= BIT(info->core_chipsel);
989 nand_controller_init(&info->controller);
990 info->controller.ops = &davinci_nand_controller_ops;
991 info->chip.controller = &info->controller;
992 ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
994 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
998 if (pdata->parts)
999 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
1006 dev_info(&pdev->dev, "controller rev. %d.%d\n",
1012 nand_cleanup(&info->chip);
1020 struct nand_chip *chip = &info->chip;
1024 if (chip->ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED)
1047 MODULE_DESCRIPTION("Davinci NAND flash driver");