Lines Matching defs:sdr
2400 const struct nand_sdr_timings *sdr)
2431 tdvw_min = sdr->tREA_max + board_delay_skew_max;
2441 if (sdr->tRC_min <= clk_period &&
2442 sdr->tRP_min <= (clk_period / 2) &&
2443 sdr->tREH_min <= (clk_period / 2)) {
2446 tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
2447 sdr->tREA_max, ext_rd_mode);
2448 tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min,
2471 trp_cnt = (sdr->tREA_max + board_delay_skew_max
2481 trp_cnt = calc_cycl(sdr->tRP_min, clk_period);
2482 trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period);
2483 if (sdr->tREH_min >= trh)
2484 trh_cnt = calc_cycl(sdr->tREH_min, clk_period);
2488 tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
2489 sdr->tREA_max, ext_rd_mode);
2497 sdr->tRHOH_min,
2521 trp_cnt = (sdr->tREA_max + board_delay_skew_max
2527 sdr->tRHOH_min,
2530 if (sdr->tWC_min <= clk_period &&
2531 (sdr->tWP_min + if_skew) <= (clk_period / 2) &&
2532 (sdr->tWH_min + if_skew) <= (clk_period / 2)) {
2538 twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period);
2539 if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew))
2540 twp_cnt = calc_cycl(sdr->tALS_min + if_skew,
2543 twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period);
2544 if (sdr->tWH_min >= twh)
2545 twh = sdr->tWH_min;
2557 tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period);
2558 tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period);
2559 twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period);
2560 trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period);
2578 trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period);
2580 twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period);
2598 tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period);
2602 tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period);
2603 tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period);
2878 const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
2880 if (IS_ERR(sdr))
2881 return PTR_ERR(sdr);
2883 ret = cadence_nand_setup_sdr_interface(chip, sdr);