Lines Matching +full:nand +full:- +full:ecc +full:- +full:strength
1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Macronix external hardware ECC engine for NAND devices, also
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
53 /* ECC Chunk Size */
63 /* ECC Chunk Count */
98 /* ECC machinery */
124 static struct mxic_ecc_engine *nand_to_mxic(struct nand_device *nand)
126 struct nand_ecc_engine *eng = nand->ecc.engine;
128 if (eng->integration == NAND_ECC_ENGINE_INTEGRATION_EXTERNAL)
137 struct nand_device *nand = mtd_to_nanddev(mtd);
138 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
140 if (section < 0 || section >= ctx->steps)
141 return -ERANGE;
143 oobregion->offset = (section * ctx->oob_step_sz) + ctx->meta_sz;
144 oobregion->length = ctx->parity_sz;
152 struct nand_device *nand = mtd_to_nanddev(mtd);
153 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
155 if (section < 0 || section >= ctx->steps)
156 return -ERANGE;
159 oobregion->offset = 2;
160 oobregion->length = ctx->meta_sz - 2;
162 oobregion->offset = section * ctx->oob_step_sz;
163 oobregion->length = ctx->meta_sz;
170 .ecc = mxic_ecc_ooblayout_ecc,
178 reg = readl(mxic->regs + DP_CONFIG);
180 writel(reg, mxic->regs + DP_CONFIG);
187 reg = readl(mxic->regs + DP_CONFIG);
189 writel(reg, mxic->regs + DP_CONFIG);
194 writel(0, mxic->regs + INTRPT_SIG_EN);
199 writel(TRANS_CMPLT, mxic->regs + INTRPT_SIG_EN);
207 sts = readl(mxic->regs + INTRPT_STS);
212 complete(&mxic->complete);
214 writel(sts, mxic->regs + INTRPT_STS);
219 static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)
221 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
222 struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
223 struct nand_ecc_props *reqs = &nand->ecc.requirements;
224 struct nand_ecc_props *user = &nand->ecc.user_conf;
225 struct mtd_info *mtd = nanddev_to_mtd(nand);
226 int step_size = 0, strength = 0, desired_correction = 0, steps, idx;
235 return -ENOMEM;
237 nand->ecc.ctx.priv = ctx;
239 /* Only large page NAND chips may use BCH */
240 if (mtd->oobsize < 64) {
241 pr_err("BCH cannot be used with small page NAND chips\n");
242 return -EINVAL;
249 TO_SPARE | TO_MAIN, mxic->regs + INTRPT_STS_EN);
251 /* Configure the correction depending on the NAND device topology */
252 if (user->step_size && user->strength) {
253 step_size = user->step_size;
254 strength = user->strength;
255 } else if (reqs->step_size && reqs->strength) {
256 step_size = reqs->step_size;
257 strength = reqs->strength;
260 if (step_size && strength) {
261 steps = mtd->writesize / step_size;
262 desired_correction = steps * strength;
265 /* Step size is fixed to 1kiB, strength may vary (4 possible values) */
266 conf->step_size = SZ_1K;
267 steps = mtd->writesize / conf->step_size;
269 ctx->status = devm_kzalloc(dev, steps * sizeof(u8), GFP_KERNEL);
270 if (!ctx->status)
271 return -ENOMEM;
274 strength = desired_correction / steps;
277 if (possible_strength[idx] >= strength)
281 ARRAY_SIZE(possible_strength) - 1);
284 idx = ARRAY_SIZE(possible_strength) - 1;
287 /* Tune the selected strength until it fits in the OOB area */
288 for (; idx >= 0; idx--) {
289 if (spare_size[idx] * steps <= mtd->oobsize)
293 /* This engine cannot be used with this NAND device */
295 return -EINVAL;
297 /* Configure the engine for the desired strength */
298 writel(ECC_TYP(idx), mxic->regs + DP_CONFIG);
299 conf->strength = possible_strength[idx];
300 spare_reg = readl(mxic->regs + SPARE_SIZE);
302 ctx->steps = steps;
303 ctx->data_step_sz = mtd->writesize / steps;
304 ctx->oob_step_sz = mtd->oobsize / steps;
305 ctx->parity_sz = PARITY_SZ(spare_reg);
306 ctx->meta_sz = META_SZ(spare_reg);
309 ctx->req_ctx.oob_buffer_size = nanddev_per_page_oobsize(nand) +
310 (ctx->steps * STAT_BYTES);
311 ret = nand_ecc_init_req_tweaking(&ctx->req_ctx, nand);
315 ctx->oobwithstat = kmalloc(mtd->oobsize + (ctx->steps * STAT_BYTES),
317 if (!ctx->oobwithstat) {
318 ret = -ENOMEM;
322 sg_init_table(ctx->sg, 2);
326 readl(mxic->regs + DP_VER) >> DP_VER_OFFSET);
327 dev_err(dev, "Chunk size: %d\n", readl(mxic->regs + CHUNK_SIZE));
328 dev_err(dev, "Main size: %d\n", readl(mxic->regs + MAIN_SIZE));
331 dev_err(dev, "Parity size: %d\n", ctx->parity_sz);
332 dev_err(dev, "Meta size: %d\n", ctx->meta_sz);
334 if ((ctx->meta_sz + ctx->parity_sz + RSV_SZ(spare_reg)) !=
337 ctx->meta_sz, ctx->parity_sz, RSV_SZ(spare_reg),
339 ret = -EINVAL;
343 if (ctx->oob_step_sz != SPARE_SZ(spare_reg)) {
345 ctx->oob_step_sz, SPARE_SZ(spare_reg));
346 ret = -EINVAL;
353 kfree(ctx->oobwithstat);
355 nand_ecc_cleanup_req_tweaking(&ctx->req_ctx);
360 static int mxic_ecc_init_ctx_external(struct nand_device *nand)
362 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
363 struct device *dev = nand->ecc.engine->dev;
366 dev_info(dev, "Macronix ECC engine in external mode\n");
368 ret = mxic_ecc_init_ctx(nand, dev);
373 writel(1, mxic->regs + CHUNK_CNT);
375 mxic->regs + HC_CONFIG);
380 static int mxic_ecc_init_ctx_pipelined(struct nand_device *nand)
382 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
387 dev = nand_ecc_get_engine_dev(nand->ecc.engine->dev);
389 return -EINVAL;
391 dev_info(dev, "Macronix ECC engine in pipelined/mapping mode\n");
393 ret = mxic_ecc_init_ctx(nand, dev);
397 ctx = nand_to_ecc_ctx(nand);
400 writel(ctx->steps, mxic->regs + CHUNK_CNT);
403 * Interleaved ECC scheme cannot be used otherwise factory bad block
407 mxic->regs + HC_CONFIG);
412 static void mxic_ecc_cleanup_ctx(struct nand_device *nand)
414 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
417 nand_ecc_cleanup_req_tweaking(&ctx->req_ctx);
418 kfree(ctx->oobwithstat);
427 if (mxic->irq) {
428 reinit_completion(&mxic->complete);
430 ret = wait_for_completion_timeout(&mxic->complete,
432 ret = ret ? 0 : -ETIMEDOUT;
435 ret = readl_poll_timeout(mxic->regs + INTRPT_STS, val,
437 writel(val, mxic->regs + INTRPT_STS);
441 dev_err(mxic->dev, "Timeout on data xfer completion\n");
442 return -ETIMEDOUT;
458 writel(SDMA_STRT | dir, mxic->regs + SDMA_CTRL);
474 writel(dirmap, mxic->regs + HC_SLV_ADDR);
482 u8 *buf = ctx->oobwithstat;
486 /* Extract the ECC status */
487 for (step = 0; step < ctx->steps; step++) {
488 next_stat_pos = ctx->oob_step_sz +
489 ((STAT_BYTES + ctx->oob_step_sz) * step);
491 ctx->status[step] = buf[next_stat_pos];
500 /* Reconstruct the OOB buffer linearly (without the ECC status bytes) */
501 for (step = 0; step < ctx->steps; step++)
502 memcpy(dst + (step * ctx->oob_step_sz),
503 src + (step * (ctx->oob_step_sz + STAT_BYTES)),
504 ctx->oob_step_sz);
513 for (step = 0; step < ctx->steps; step++)
514 memcpy(dst + (step * (ctx->oob_step_sz + STAT_BYTES)),
515 src + (step * ctx->oob_step_sz),
516 ctx->oob_step_sz);
520 struct nand_device *nand)
522 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
523 struct mtd_info *mtd = nanddev_to_mtd(nand);
524 struct device *dev = mxic->dev;
529 for (step = 0; step < ctx->steps; step++) {
530 u8 stat = ctx->status[step];
533 dev_dbg(dev, "ECC step %d: no error\n", step);
535 dev_dbg(dev, "ECC step %d: erased\n", step);
537 dev_dbg(dev, "ECC step %d: uncorrectable\n", step);
538 mtd->ecc_stats.failed++;
541 dev_dbg(dev, "ECC step %d: %d bits corrected\n",
544 mtd->ecc_stats.corrected += stat;
548 return failure ? -EBADMSG : max_bf;
551 /* External ECC engine helpers */
552 static int mxic_ecc_prepare_io_req_external(struct nand_device *nand,
555 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
556 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
557 struct mtd_info *mtd = nanddev_to_mtd(nand);
560 if (req->mode == MTD_OPS_RAW)
563 nand_ecc_tweak_req(&ctx->req_ctx, req);
564 ctx->req = req;
566 if (req->type == NAND_PAGE_READ)
569 mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat,
570 ctx->req->oobbuf.out);
572 sg_set_buf(&ctx->sg[0], req->databuf.out, req->datalen);
573 sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
574 req->ooblen + (ctx->steps * STAT_BYTES));
576 nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
578 return -EINVAL;
580 mutex_lock(&mxic->lock);
582 for (step = 0; step < ctx->steps; step++) {
583 writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
584 mxic->regs + SDMA_MAIN_ADDR);
585 writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
586 mxic->regs + SDMA_SPARE_ADDR);
587 ret = mxic_ecc_process_data(mxic, ctx->req->type);
592 mutex_unlock(&mxic->lock);
594 dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
599 /* Retrieve the calculated ECC bytes */
600 for (step = 0; step < ctx->steps; step++) {
601 offset = ctx->meta_sz + (step * ctx->oob_step_sz);
603 (u8 *)ctx->req->oobbuf.out + offset,
604 ctx->oobwithstat + (step * STAT_BYTES),
605 step * ctx->parity_sz,
606 ctx->parity_sz);
612 static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
615 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
616 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
619 if (req->mode == MTD_OPS_RAW)
622 if (req->type == NAND_PAGE_WRITE) {
623 nand_ecc_restore_req(&ctx->req_ctx, req);
627 /* Copy the OOB buffer and add room for the ECC engine status bytes */
628 mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat, ctx->req->oobbuf.in);
630 sg_set_buf(&ctx->sg[0], req->databuf.in, req->datalen);
631 sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
632 req->ooblen + (ctx->steps * STAT_BYTES));
633 nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
635 return -EINVAL;
637 mutex_lock(&mxic->lock);
639 for (step = 0; step < ctx->steps; step++) {
640 writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
641 mxic->regs + SDMA_MAIN_ADDR);
642 writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
643 mxic->regs + SDMA_SPARE_ADDR);
644 ret = mxic_ecc_process_data(mxic, ctx->req->type);
649 mutex_unlock(&mxic->lock);
651 dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
654 nand_ecc_restore_req(&ctx->req_ctx, req);
660 mxic_ecc_reconstruct_oobbuf(ctx, ctx->req->oobbuf.in, ctx->oobwithstat);
662 nand_ecc_restore_req(&ctx->req_ctx, req);
664 return mxic_ecc_count_biterrs(mxic, nand);
667 /* Pipelined ECC engine helpers */
668 static int mxic_ecc_prepare_io_req_pipelined(struct nand_device *nand,
671 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
672 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
675 if (req->mode == MTD_OPS_RAW)
678 nand_ecc_tweak_req(&ctx->req_ctx, req);
679 ctx->req = req;
681 /* Copy the OOB buffer and add room for the ECC engine status bytes */
682 mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat, ctx->req->oobbuf.in);
684 sg_set_buf(&ctx->sg[0], req->databuf.in, req->datalen);
685 sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
686 req->ooblen + (ctx->steps * STAT_BYTES));
688 nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
690 return -EINVAL;
692 mutex_lock(&mxic->lock);
694 writel(sg_dma_address(&ctx->sg[0]), mxic->regs + SDMA_MAIN_ADDR);
695 writel(sg_dma_address(&ctx->sg[1]), mxic->regs + SDMA_SPARE_ADDR);
700 static int mxic_ecc_finish_io_req_pipelined(struct nand_device *nand,
703 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
704 struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
707 if (req->mode == MTD_OPS_RAW)
710 mutex_unlock(&mxic->lock);
712 dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
714 if (req->type == NAND_PAGE_READ) {
716 mxic_ecc_reconstruct_oobbuf(ctx, ctx->req->oobbuf.in,
717 ctx->oobwithstat);
718 ret = mxic_ecc_count_biterrs(mxic, nand);
721 nand_ecc_restore_req(&ctx->req_ctx, req);
752 /* Retrieve the nand-ecc-engine phandle */
753 np = of_parse_phandle(spi_pdev->dev.of_node, "nand-ecc-engine", 0);
768 platform_device_put(to_platform_device(mxic->dev));
780 return ERR_PTR(-ENODEV);
785 return ERR_PTR(-EPROBE_DEFER);
788 return &mxic->pipelined_engine;
793 * Only the external ECC engine is exported as the pipelined is SoC specific, so
798 struct device *dev = &pdev->dev;
802 mxic = devm_kzalloc(&pdev->dev, sizeof(*mxic), GFP_KERNEL);
804 return -ENOMEM;
806 mxic->dev = &pdev->dev;
809 * Both memory regions for the ECC engine itself and the AXI slave
812 mxic->regs = devm_platform_ioremap_resource(pdev, 0);
813 if (IS_ERR(mxic->regs)) {
814 dev_err(&pdev->dev, "Missing memory region\n");
815 return PTR_ERR(mxic->regs);
822 mxic->irq = platform_get_irq_byname_optional(pdev, "ecc-engine");
823 if (mxic->irq > 0) {
824 ret = devm_request_irq(&pdev->dev, mxic->irq, mxic_ecc_isr, 0,
825 "mxic-ecc", mxic);
830 mxic->irq = 0;
833 mutex_init(&mxic->lock);
836 * In external mode, the device is the ECC engine. In pipelined mode,
838 * right ECC engine based on the DT properties.
840 mxic->external_engine.dev = &pdev->dev;
841 mxic->external_engine.integration = NAND_ECC_ENGINE_INTEGRATION_EXTERNAL;
842 mxic->external_engine.ops = &mxic_ecc_engine_external_ops;
844 nand_ecc_register_on_host_hw_engine(&mxic->external_engine);
855 nand_ecc_unregister_on_host_hw_engine(&mxic->external_engine);
860 .compatible = "mxicy,nand-ecc-engine-rev3",
868 .name = "mxic-nand-ecc-engine",
878 MODULE_DESCRIPTION("Macronix NAND hardware ECC controller");