51 #define SMI_CR1		0x0	/* SMI control register 1 */
52 #define SMI_CR2		0x4	/* SMI control register 2 */
53 #define SMI_SR		0x8	/* SMI status register */
54 #define SMI_TR		0xC	/* SMI transmit register */
55 #define SMI_RR		0x10	/* SMI receive register */
58 #define BANK_EN		(0xF << 0)	/* enables all banks */
59 #define DSEL_TIME	(0x6 << 4)	/* Deselect time 6 + 1 SMI_CK periods */
60 #define SW_MODE		(0x1 << 28)	/* enables SW Mode */
61 #define WB_MODE		(0x1 << 29)	/* Write Burst Mode */
62 #define FAST_MODE	(0x1 << 15)	/* Fast Mode */
63 #define HOLD1		(0x1 << 16)	/* Clock Hold period selection */
66 #define SEND		(0x1 << 7)	/* Send data */
67 #define TFIE		(0x1 << 8)	/* Transmission Flag Interrupt Enable */
68 #define WCIE		(0x1 << 9)	/* Write Complete Interrupt Enable */
69 #define RD_STATUS_REG	(0x1 << 10)	/* reads status reg */
70 #define WE		(0x1 << 11)	/* Write Enable */
72 #define TX_LEN_SHIFT	0
77 #define SR_WIP		0x1	/* Write in progress */
78 #define SR_WEL		0x2	/* Write enable latch */
79 #define SR_BP0		0x4	/* Block protect 0 */
80 #define SR_BP1		0x8	/* Block protect 1 */
81 #define SR_BP2		0x10	/* Block protect 2 */
82 #define SR_SRWD		0x80	/* SR write protect */
83 #define TFF		0x100	/* Transfer Finished Flag */
84 #define WCF		0x200	/* Transfer Finished Flag */
85 #define ERF1		0x400	/* Forbidden Write Request */
86 #define ERF2		0x800	/* Forbidden Access */
91 #define OPCODE_RDID	0x9f	/* Read JEDEC ID */
116 	FLASH_ID("st m25p16"     , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
117 	FLASH_ID("st m25p32"     , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
118 	FLASH_ID("st m25p64"     , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
119 	FLASH_ID("st m25p128"    , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
120 	FLASH_ID("st m25p05"     , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
121 	FLASH_ID("st m25p10"     , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
122 	FLASH_ID("st m25p20"     , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
123 	FLASH_ID("st m25p40"     , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
124 	FLASH_ID("st m25p80"     , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
125 	FLASH_ID("st m45pe10"    , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
126 	FLASH_ID("st m45pe20"    , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
127 	FLASH_ID("st m45pe40"    , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
128 	FLASH_ID("st m45pe80"    , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
129 	FLASH_ID("sp s25fl004"   , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
130 	FLASH_ID("sp s25fl008"   , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
131 	FLASH_ID("sp s25fl016"   , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
132 	FLASH_ID("sp s25fl032"   , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
133 	FLASH_ID("sp s25fl064"   , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
134 	FLASH_ID("atmel 25f512"  , 0x52, 0x0065001F, 0x80 , 0x8000 , 0x10000),
135 	FLASH_ID("atmel 25f1024" , 0x52, 0x0060001F, 0x100, 0x8000 , 0x20000),
136 	FLASH_ID("atmel 25f2048" , 0x52, 0x0063001F, 0x100, 0x10000, 0x40000),
137 	FLASH_ID("atmel 25f4096" , 0x52, 0x0064001F, 0x100, 0x10000, 0x80000),
138 	FLASH_ID("atmel 25fs040" , 0xd7, 0x0004661F, 0x100, 0x10000, 0x80000),
139 	FLASH_ID("mac 25l512"    , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
140 	FLASH_ID("mac 25l1005"   , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
141 	FLASH_ID("mac 25l2005"   , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
142 	FLASH_ID("mac 25l4005"   , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
143 	FLASH_ID("mac 25l4005a"  , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
144 	FLASH_ID("mac 25l8005"   , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
145 	FLASH_ID("mac 25l1605"   , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
146 	FLASH_ID("mac 25l1605a"  , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
147 	FLASH_ID("mac 25l3205"   , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
148 	FLASH_ID("mac 25l3205a"  , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
149 	FLASH_ID("mac 25l6405"   , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
184  * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
227 	dev->status = 0; /* Will be set in interrupt handler */  in spear_smi_read_sr()
242 	if (ret > 0)  in spear_smi_read_sr()
243 		ret = dev->status & 0xffff;  in spear_smi_read_sr()
244 	else if (ret == 0)  in spear_smi_read_sr()
249 	writel(0, dev->io_base + SMI_CR2);  in spear_smi_read_sr()
262  * If successful the routine returns 0 else -EBUSY
273 		if (status < 0) {  in spear_smi_wait_till_ready()
278 			return 0;  in spear_smi_wait_till_ready()
298 	u32 status = 0;  in spear_smi_int_handler()
307 	writel(0, dev->io_base + SMI_SR);  in spear_smi_int_handler()
326 	unsigned long rate = 0;  in spear_smi_hw_init()
327 	u32 prescale = 0;  in spear_smi_hw_init()
343 	writel(0, dev->io_base + SMI_SR);  in spear_smi_hw_init()
362 	for (index = 0; index < ARRAY_SIZE(flash_devices); index++) {  in get_flash_index()
377  * Returns 0 on success.
385 	dev->status = 0; /* Will be set in interrupt handler */  in spear_smi_write_enable()
399 	writel(0, dev->io_base + SMI_CR2);  in spear_smi_write_enable()
401 	if (ret == 0) {  in spear_smi_write_enable()
405 	} else if (ret > 0) {  in spear_smi_write_enable()
408 			ret = 0;  in spear_smi_write_enable()
425 	x[0] = flash->erase_cmd;  in get_sector_erase_cmd()
442  * Returns 0 if successful, non-zero otherwise.
447 	u32 ctrlreg1 = 0;  in spear_smi_erase_sector()
472 	if (ret == 0) {  in spear_smi_erase_sector()
475 	} else if (ret > 0)  in spear_smi_erase_sector()
476 		ret = 0; /* success */  in spear_smi_erase_sector()
480 	writel(0, dev->io_base + SMI_CR2);  in spear_smi_erase_sector()
530 	return 0;  in spear_mtd_erase()
543  * Returns 0 on success, non zero otherwise
592 	return 0;  in spear_mtd_read()
658 	return 0;  in spear_smi_cpy_toio()
672  * Returns 0 on success, non zero otherwise
748 	u32 val = 0;  in spear_smi_probe_flash()
756 	dev->status = 0; /* Will be set in interrupt handler */  in spear_smi_probe_flash()
771 	if (ret <= 0) {  in spear_smi_probe_flash()
778 	val &= 0x00ffffff;  in spear_smi_probe_flash()
800 	int i = 0;  in spear_smi_probe_config_dt()
820 		pdata->board_flash_info->mem_base = be32_to_cpup(&addr[0]);  in spear_smi_probe_config_dt()
831 	return 0;  in spear_smi_probe_config_dt()
849 	int count = 0;  in spear_smi_setup_banks()
851 	int ret = 0;  in spear_smi_setup_banks()
865 	flash->fast_mode = flash_info->fast_mode ? 1 : 0;  in spear_smi_setup_banks()
870 	if (flash_index < 0) {  in spear_smi_setup_banks()
907 	dev_info(&dev->pdev->dev, ".erasesize = 0x%x(%uK)\n",  in spear_smi_setup_banks()
923 	return 0;  in spear_smi_setup_banks()
933  * Returns 0 on success, non zero otherwise
940 	int irq, ret = 0;  in spear_smi_probe()
965 	irq = platform_get_irq(pdev, 0);  in spear_smi_probe()
966 	if (irq < 0) {  in spear_smi_probe()
977 	dev->io_base = devm_platform_ioremap_resource(pdev, 0);  in spear_smi_probe()
1002 	ret = devm_request_irq(&pdev->dev, irq, spear_smi_int_handler, 0,  in spear_smi_probe()
1015 	for (i = 0; i < dev->num_flashes; i++) {  in spear_smi_probe()
1023 	return 0;  in spear_smi_probe()
1043 	for (i = 0; i < dev->num_flashes; i++) {  in spear_smi_remove()
1061 	return 0;  in spear_smi_suspend()