Lines Matching +full:mmc +full:- +full:host
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for sunxi SD/MMC host controllers
4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
13 #include <linux/clk/sunxi-ng.h>
16 #include <linux/dma-mapping.h>
21 #include <linux/mmc/card.h>
22 #include <linux/mmc/core.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/sd.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/slot-gpio.h>
77 #define mmc_readl(host, reg) \ argument
78 readl((host)->reg_base + SDXC_##reg)
79 #define mmc_writel(host, reg, value) \ argument
80 writel((value), (host)->reg_base + SDXC_##reg)
203 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
204 * Bits 0-12: buf1 size
205 * Bits 13-25: buf2 size
206 * Bits 26-31: not used
215 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
259 * a mode switch in the clock controller, or the mmc controller
271 struct mmc_host *mmc; member
306 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) in sunxi_mmc_reset_host() argument
311 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); in sunxi_mmc_reset_host()
313 rval = mmc_readl(host, REG_GCTRL); in sunxi_mmc_reset_host()
317 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); in sunxi_mmc_reset_host()
318 return -EIO; in sunxi_mmc_reset_host()
324 static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) in sunxi_mmc_init_host() argument
328 if (sunxi_mmc_reset_host(host)) in sunxi_mmc_init_host()
329 return -EIO; in sunxi_mmc_init_host()
336 mmc_writel(host, REG_FTRGL, 0x20070008); in sunxi_mmc_init_host()
338 mmc_writel(host, REG_TMOUT, 0xffffffff); in sunxi_mmc_init_host()
340 mmc_writel(host, REG_IMASK, host->sdio_imask); in sunxi_mmc_init_host()
342 mmc_writel(host, REG_RINTR, 0xffffffff); in sunxi_mmc_init_host()
344 mmc_writel(host, REG_DBGC, 0xdeb); in sunxi_mmc_init_host()
346 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); in sunxi_mmc_init_host()
348 mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift); in sunxi_mmc_init_host()
350 rval = mmc_readl(host, REG_GCTRL); in sunxi_mmc_init_host()
354 mmc_writel(host, REG_GCTRL, rval); in sunxi_mmc_init_host()
359 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, in sunxi_mmc_init_idma_des() argument
362 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; in sunxi_mmc_init_idma_des()
363 dma_addr_t next_desc = host->sg_dma; in sunxi_mmc_init_idma_des()
364 int i, max_len = (1 << host->cfg->idma_des_size_bits); in sunxi_mmc_init_idma_des()
366 for (i = 0; i < data->sg_len; i++) { in sunxi_mmc_init_idma_des()
371 if (data->sg[i].length == max_len) in sunxi_mmc_init_idma_des()
374 pdes[i].buf_size = cpu_to_le32(data->sg[i].length); in sunxi_mmc_init_idma_des()
378 cpu_to_le32(sg_dma_address(&data->sg[i]) >> in sunxi_mmc_init_idma_des()
379 host->cfg->idma_des_shift); in sunxi_mmc_init_idma_des()
382 host->cfg->idma_des_shift); in sunxi_mmc_init_idma_des()
386 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | in sunxi_mmc_init_idma_des()
388 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); in sunxi_mmc_init_idma_des()
389 pdes[i - 1].buf_addr_ptr2 = 0; in sunxi_mmc_init_idma_des()
392 * Avoid the io-store starting the idmac hitting io-mem before the in sunxi_mmc_init_idma_des()
393 * descriptors hit the main-mem. in sunxi_mmc_init_idma_des()
398 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, in sunxi_mmc_map_dma() argument
404 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, in sunxi_mmc_map_dma()
407 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); in sunxi_mmc_map_dma()
408 return -ENOMEM; in sunxi_mmc_map_dma()
411 for_each_sg(data->sg, sg, data->sg_len, i) { in sunxi_mmc_map_dma()
412 if (sg->offset & 3 || sg->length & 3) { in sunxi_mmc_map_dma()
413 dev_err(mmc_dev(host->mmc), in sunxi_mmc_map_dma()
415 sg->offset, sg->length); in sunxi_mmc_map_dma()
416 return -EINVAL; in sunxi_mmc_map_dma()
423 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, in sunxi_mmc_start_dma() argument
428 sunxi_mmc_init_idma_des(host, data); in sunxi_mmc_start_dma()
430 rval = mmc_readl(host, REG_GCTRL); in sunxi_mmc_start_dma()
432 mmc_writel(host, REG_GCTRL, rval); in sunxi_mmc_start_dma()
434 mmc_writel(host, REG_GCTRL, rval); in sunxi_mmc_start_dma()
436 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); in sunxi_mmc_start_dma()
438 if (!(data->flags & MMC_DATA_WRITE)) in sunxi_mmc_start_dma()
439 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); in sunxi_mmc_start_dma()
441 mmc_writel(host, REG_DMAC, in sunxi_mmc_start_dma()
445 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, in sunxi_mmc_send_manual_stop() argument
454 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { in sunxi_mmc_send_manual_stop()
457 ((req->cmd->arg >> 28) & 0x7); in sunxi_mmc_send_manual_stop()
463 mmc_writel(host, REG_CARG, arg); in sunxi_mmc_send_manual_stop()
464 mmc_writel(host, REG_CMDR, cmd_val); in sunxi_mmc_send_manual_stop()
467 ri = mmc_readl(host, REG_RINTR); in sunxi_mmc_send_manual_stop()
472 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); in sunxi_mmc_send_manual_stop()
473 if (req->stop) in sunxi_mmc_send_manual_stop()
474 req->stop->resp[0] = -ETIMEDOUT; in sunxi_mmc_send_manual_stop()
476 if (req->stop) in sunxi_mmc_send_manual_stop()
477 req->stop->resp[0] = mmc_readl(host, REG_RESP0); in sunxi_mmc_send_manual_stop()
480 mmc_writel(host, REG_RINTR, 0xffff); in sunxi_mmc_send_manual_stop()
483 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) in sunxi_mmc_dump_errinfo() argument
485 struct mmc_command *cmd = host->mrq->cmd; in sunxi_mmc_dump_errinfo()
486 struct mmc_data *data = host->mrq->data; in sunxi_mmc_dump_errinfo()
488 /* For some cmds timeout is normal with sd/mmc cards */ in sunxi_mmc_dump_errinfo()
489 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == in sunxi_mmc_dump_errinfo()
490 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || in sunxi_mmc_dump_errinfo()
491 cmd->opcode == SD_IO_RW_DIRECT)) in sunxi_mmc_dump_errinfo()
494 dev_dbg(mmc_dev(host->mmc), in sunxi_mmc_dump_errinfo()
496 host->mmc->index, cmd->opcode, in sunxi_mmc_dump_errinfo()
497 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", in sunxi_mmc_dump_errinfo()
498 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", in sunxi_mmc_dump_errinfo()
499 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", in sunxi_mmc_dump_errinfo()
500 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", in sunxi_mmc_dump_errinfo()
501 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", in sunxi_mmc_dump_errinfo()
502 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", in sunxi_mmc_dump_errinfo()
503 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", in sunxi_mmc_dump_errinfo()
504 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", in sunxi_mmc_dump_errinfo()
505 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", in sunxi_mmc_dump_errinfo()
506 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" in sunxi_mmc_dump_errinfo()
511 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) in sunxi_mmc_finalize_request() argument
513 struct mmc_request *mrq = host->mrq; in sunxi_mmc_finalize_request()
514 struct mmc_data *data = mrq->data; in sunxi_mmc_finalize_request()
517 mmc_writel(host, REG_IMASK, host->sdio_imask); in sunxi_mmc_finalize_request()
518 mmc_writel(host, REG_IDIE, 0); in sunxi_mmc_finalize_request()
520 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { in sunxi_mmc_finalize_request()
521 sunxi_mmc_dump_errinfo(host); in sunxi_mmc_finalize_request()
522 mrq->cmd->error = -ETIMEDOUT; in sunxi_mmc_finalize_request()
525 data->error = -ETIMEDOUT; in sunxi_mmc_finalize_request()
526 host->manual_stop_mrq = mrq; in sunxi_mmc_finalize_request()
529 if (mrq->stop) in sunxi_mmc_finalize_request()
530 mrq->stop->error = -ETIMEDOUT; in sunxi_mmc_finalize_request()
532 if (mrq->cmd->flags & MMC_RSP_136) { in sunxi_mmc_finalize_request()
533 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); in sunxi_mmc_finalize_request()
534 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); in sunxi_mmc_finalize_request()
535 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); in sunxi_mmc_finalize_request()
536 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); in sunxi_mmc_finalize_request()
538 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); in sunxi_mmc_finalize_request()
542 data->bytes_xfered = data->blocks * data->blksz; in sunxi_mmc_finalize_request()
546 mmc_writel(host, REG_IDST, 0x337); in sunxi_mmc_finalize_request()
547 mmc_writel(host, REG_DMAC, 0); in sunxi_mmc_finalize_request()
548 rval = mmc_readl(host, REG_GCTRL); in sunxi_mmc_finalize_request()
550 mmc_writel(host, REG_GCTRL, rval); in sunxi_mmc_finalize_request()
552 mmc_writel(host, REG_GCTRL, rval); in sunxi_mmc_finalize_request()
554 mmc_writel(host, REG_GCTRL, rval); in sunxi_mmc_finalize_request()
555 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, in sunxi_mmc_finalize_request()
559 mmc_writel(host, REG_RINTR, 0xffff); in sunxi_mmc_finalize_request()
561 host->mrq = NULL; in sunxi_mmc_finalize_request()
562 host->int_sum = 0; in sunxi_mmc_finalize_request()
563 host->wait_dma = false; in sunxi_mmc_finalize_request()
565 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; in sunxi_mmc_finalize_request()
570 struct sunxi_mmc_host *host = dev_id; in sunxi_mmc_irq() local
577 spin_lock(&host->lock); in sunxi_mmc_irq()
579 idma_int = mmc_readl(host, REG_IDST); in sunxi_mmc_irq()
580 msk_int = mmc_readl(host, REG_MISTA); in sunxi_mmc_irq()
582 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", in sunxi_mmc_irq()
583 host->mrq, msk_int, idma_int); in sunxi_mmc_irq()
585 mrq = host->mrq; in sunxi_mmc_irq()
588 host->wait_dma = false; in sunxi_mmc_irq()
590 host->int_sum |= msk_int; in sunxi_mmc_irq()
593 if ((host->int_sum & SDXC_RESP_TIMEOUT) && in sunxi_mmc_irq()
594 !(host->int_sum & SDXC_COMMAND_DONE)) in sunxi_mmc_irq()
595 mmc_writel(host, REG_IMASK, in sunxi_mmc_irq()
596 host->sdio_imask | SDXC_COMMAND_DONE); in sunxi_mmc_irq()
598 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) in sunxi_mmc_irq()
600 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && in sunxi_mmc_irq()
601 !host->wait_dma) in sunxi_mmc_irq()
608 mmc_writel(host, REG_RINTR, msk_int); in sunxi_mmc_irq()
609 mmc_writel(host, REG_IDST, idma_int); in sunxi_mmc_irq()
612 ret = sunxi_mmc_finalize_request(host); in sunxi_mmc_irq()
614 spin_unlock(&host->lock); in sunxi_mmc_irq()
617 mmc_request_done(host->mmc, mrq); in sunxi_mmc_irq()
620 mmc_signal_sdio_irq(host->mmc); in sunxi_mmc_irq()
627 struct sunxi_mmc_host *host = dev_id; in sunxi_mmc_handle_manual_stop() local
631 spin_lock_irqsave(&host->lock, iflags); in sunxi_mmc_handle_manual_stop()
632 mrq = host->manual_stop_mrq; in sunxi_mmc_handle_manual_stop()
633 spin_unlock_irqrestore(&host->lock, iflags); in sunxi_mmc_handle_manual_stop()
636 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); in sunxi_mmc_handle_manual_stop()
640 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); in sunxi_mmc_handle_manual_stop()
645 * we've cleared host->manual_stop_mrq so we do not need to in sunxi_mmc_handle_manual_stop()
650 sunxi_mmc_send_manual_stop(host, mrq); in sunxi_mmc_handle_manual_stop()
652 spin_lock_irqsave(&host->lock, iflags); in sunxi_mmc_handle_manual_stop()
653 host->manual_stop_mrq = NULL; in sunxi_mmc_handle_manual_stop()
654 spin_unlock_irqrestore(&host->lock, iflags); in sunxi_mmc_handle_manual_stop()
656 mmc_request_done(host->mmc, mrq); in sunxi_mmc_handle_manual_stop()
661 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) in sunxi_mmc_oclk_onoff() argument
666 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", in sunxi_mmc_oclk_onoff()
669 rval = mmc_readl(host, REG_CLKCR); in sunxi_mmc_oclk_onoff()
674 if (host->cfg->mask_data0) in sunxi_mmc_oclk_onoff()
677 mmc_writel(host, REG_CLKCR, rval); in sunxi_mmc_oclk_onoff()
680 mmc_writel(host, REG_CMDR, rval); in sunxi_mmc_oclk_onoff()
683 rval = mmc_readl(host, REG_CMDR); in sunxi_mmc_oclk_onoff()
687 mmc_writel(host, REG_RINTR, in sunxi_mmc_oclk_onoff()
688 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); in sunxi_mmc_oclk_onoff()
691 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); in sunxi_mmc_oclk_onoff()
692 return -EIO; in sunxi_mmc_oclk_onoff()
695 if (host->cfg->mask_data0) { in sunxi_mmc_oclk_onoff()
696 rval = mmc_readl(host, REG_CLKCR); in sunxi_mmc_oclk_onoff()
697 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); in sunxi_mmc_oclk_onoff()
703 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) in sunxi_mmc_calibrate() argument
705 if (!host->cfg->can_calibrate) in sunxi_mmc_calibrate()
717 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); in sunxi_mmc_calibrate()
722 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, in sunxi_mmc_clk_set_phase() argument
728 if (host->use_new_timings) in sunxi_mmc_clk_set_phase()
732 if (!host->cfg->clk_delays) in sunxi_mmc_clk_set_phase()
741 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()
742 ios->timing != MMC_TIMING_MMC_DDR52) { in sunxi_mmc_clk_set_phase()
744 } else if (ios->bus_width == MMC_BUS_WIDTH_8) { in sunxi_mmc_clk_set_phase()
750 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); in sunxi_mmc_clk_set_phase()
751 return -EINVAL; in sunxi_mmc_clk_set_phase()
754 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); in sunxi_mmc_clk_set_phase()
755 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); in sunxi_mmc_clk_set_phase()
760 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, in sunxi_mmc_clk_set_rate() argument
763 struct mmc_host *mmc = host->mmc; in sunxi_mmc_clk_set_rate() local
765 u32 rval, clock = ios->clock, div = 1; in sunxi_mmc_clk_set_rate()
768 ret = sunxi_mmc_oclk_onoff(host, 0); in sunxi_mmc_clk_set_rate()
773 mmc->actual_clock = 0; in sunxi_mmc_clk_set_rate()
775 if (!ios->clock) in sunxi_mmc_clk_set_rate()
783 * We currently only support the standard MMC DDR52 mode. in sunxi_mmc_clk_set_rate()
787 if (ios->timing == MMC_TIMING_MMC_DDR52 && in sunxi_mmc_clk_set_rate()
788 (host->use_new_timings || in sunxi_mmc_clk_set_rate()
789 ios->bus_width == MMC_BUS_WIDTH_8)) { in sunxi_mmc_clk_set_rate()
794 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { in sunxi_mmc_clk_set_rate()
795 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); in sunxi_mmc_clk_set_rate()
797 dev_err(mmc_dev(mmc), in sunxi_mmc_clk_set_rate()
803 rate = clk_round_rate(host->clk_mmc, clock); in sunxi_mmc_clk_set_rate()
805 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", in sunxi_mmc_clk_set_rate()
809 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", in sunxi_mmc_clk_set_rate()
813 ret = clk_set_rate(host->clk_mmc, rate); in sunxi_mmc_clk_set_rate()
815 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", in sunxi_mmc_clk_set_rate()
821 rval = mmc_readl(host, REG_CLKCR); in sunxi_mmc_clk_set_rate()
823 rval |= div - 1; in sunxi_mmc_clk_set_rate()
824 mmc_writel(host, REG_CLKCR, rval); in sunxi_mmc_clk_set_rate()
835 if (host->use_new_timings) { in sunxi_mmc_clk_set_rate()
837 rval = mmc_readl(host, REG_SD_NTSR); in sunxi_mmc_clk_set_rate()
839 mmc_writel(host, REG_SD_NTSR, rval); in sunxi_mmc_clk_set_rate()
843 ret = sunxi_mmc_clk_set_phase(host, ios, rate); in sunxi_mmc_clk_set_rate()
847 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); in sunxi_mmc_clk_set_rate()
859 ret = sunxi_mmc_oclk_onoff(host, 1); in sunxi_mmc_clk_set_rate()
864 mmc->actual_clock = rate; in sunxi_mmc_clk_set_rate()
869 static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, in sunxi_mmc_set_bus_width() argument
874 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); in sunxi_mmc_set_bus_width()
877 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); in sunxi_mmc_set_bus_width()
880 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); in sunxi_mmc_set_bus_width()
885 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) in sunxi_mmc_set_clk() argument
890 rval = mmc_readl(host, REG_GCTRL); in sunxi_mmc_set_clk()
891 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
892 ios->timing == MMC_TIMING_MMC_DDR52) in sunxi_mmc_set_clk()
896 mmc_writel(host, REG_GCTRL, rval); in sunxi_mmc_set_clk()
898 host->ferror = sunxi_mmc_clk_set_rate(host, ios); in sunxi_mmc_set_clk()
902 static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, in sunxi_mmc_card_power() argument
905 struct mmc_host *mmc = host->mmc; in sunxi_mmc_card_power() local
907 switch (ios->power_mode) { in sunxi_mmc_card_power()
909 dev_dbg(mmc_dev(mmc), "Powering card up\n"); in sunxi_mmc_card_power()
911 if (!IS_ERR(mmc->supply.vmmc)) { in sunxi_mmc_card_power()
912 host->ferror = mmc_regulator_set_ocr(mmc, in sunxi_mmc_card_power()
913 mmc->supply.vmmc, in sunxi_mmc_card_power()
914 ios->vdd); in sunxi_mmc_card_power()
915 if (host->ferror) in sunxi_mmc_card_power()
919 if (!IS_ERR(mmc->supply.vqmmc)) { in sunxi_mmc_card_power()
920 host->ferror = regulator_enable(mmc->supply.vqmmc); in sunxi_mmc_card_power()
921 if (host->ferror) { in sunxi_mmc_card_power()
922 dev_err(mmc_dev(mmc), in sunxi_mmc_card_power()
926 host->vqmmc_enabled = true; in sunxi_mmc_card_power()
931 dev_dbg(mmc_dev(mmc), "Powering card off\n"); in sunxi_mmc_card_power()
933 if (!IS_ERR(mmc->supply.vmmc)) in sunxi_mmc_card_power()
934 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in sunxi_mmc_card_power()
936 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) in sunxi_mmc_card_power()
937 regulator_disable(mmc->supply.vqmmc); in sunxi_mmc_card_power()
939 host->vqmmc_enabled = false; in sunxi_mmc_card_power()
943 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n"); in sunxi_mmc_card_power()
948 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) in sunxi_mmc_set_ios() argument
950 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_set_ios() local
952 sunxi_mmc_card_power(host, ios); in sunxi_mmc_set_ios()
953 sunxi_mmc_set_bus_width(host, ios->bus_width); in sunxi_mmc_set_ios()
954 sunxi_mmc_set_clk(host, ios); in sunxi_mmc_set_ios()
957 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) in sunxi_mmc_volt_switch() argument
962 if (!IS_ERR(mmc->supply.vqmmc)) { in sunxi_mmc_volt_switch()
963 ret = mmc_regulator_set_vqmmc(mmc, ios); in sunxi_mmc_volt_switch()
968 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) in sunxi_mmc_volt_switch()
971 return -EINVAL; in sunxi_mmc_volt_switch()
974 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) in sunxi_mmc_enable_sdio_irq() argument
976 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_enable_sdio_irq() local
981 pm_runtime_get_noresume(host->dev); in sunxi_mmc_enable_sdio_irq()
983 spin_lock_irqsave(&host->lock, flags); in sunxi_mmc_enable_sdio_irq()
985 imask = mmc_readl(host, REG_IMASK); in sunxi_mmc_enable_sdio_irq()
987 host->sdio_imask = SDXC_SDIO_INTERRUPT; in sunxi_mmc_enable_sdio_irq()
990 host->sdio_imask = 0; in sunxi_mmc_enable_sdio_irq()
993 mmc_writel(host, REG_IMASK, imask); in sunxi_mmc_enable_sdio_irq()
994 spin_unlock_irqrestore(&host->lock, flags); in sunxi_mmc_enable_sdio_irq()
997 pm_runtime_put_noidle(host->mmc->parent); in sunxi_mmc_enable_sdio_irq()
1000 static void sunxi_mmc_hw_reset(struct mmc_host *mmc) in sunxi_mmc_hw_reset() argument
1002 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_hw_reset() local
1003 mmc_writel(host, REG_HWRST, 0); in sunxi_mmc_hw_reset()
1005 mmc_writel(host, REG_HWRST, 1); in sunxi_mmc_hw_reset()
1009 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) in sunxi_mmc_request() argument
1011 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_request() local
1012 struct mmc_command *cmd = mrq->cmd; in sunxi_mmc_request()
1013 struct mmc_data *data = mrq->data; in sunxi_mmc_request()
1016 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); in sunxi_mmc_request()
1017 bool wait_dma = host->wait_dma; in sunxi_mmc_request()
1021 if (host->ferror) { in sunxi_mmc_request()
1022 mrq->cmd->error = host->ferror; in sunxi_mmc_request()
1023 mmc_request_done(mmc, mrq); in sunxi_mmc_request()
1028 ret = sunxi_mmc_map_dma(host, data); in sunxi_mmc_request()
1030 dev_err(mmc_dev(mmc), "map DMA failed\n"); in sunxi_mmc_request()
1031 cmd->error = ret; in sunxi_mmc_request()
1032 data->error = ret; in sunxi_mmc_request()
1033 mmc_request_done(mmc, mrq); in sunxi_mmc_request()
1038 if (cmd->opcode == MMC_GO_IDLE_STATE) { in sunxi_mmc_request()
1043 if (cmd->flags & MMC_RSP_PRESENT) { in sunxi_mmc_request()
1045 if (cmd->flags & MMC_RSP_136) in sunxi_mmc_request()
1047 if (cmd->flags & MMC_RSP_CRC) in sunxi_mmc_request()
1050 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { in sunxi_mmc_request()
1053 if (cmd->data->stop) { in sunxi_mmc_request()
1060 if (cmd->data->flags & MMC_DATA_WRITE) in sunxi_mmc_request()
1071 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", in sunxi_mmc_request()
1072 cmd_val & 0x3f, cmd_val, cmd->arg, imask, in sunxi_mmc_request()
1073 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); in sunxi_mmc_request()
1075 spin_lock_irqsave(&host->lock, iflags); in sunxi_mmc_request()
1077 if (host->mrq || host->manual_stop_mrq) { in sunxi_mmc_request()
1078 spin_unlock_irqrestore(&host->lock, iflags); in sunxi_mmc_request()
1081 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, in sunxi_mmc_request()
1084 dev_err(mmc_dev(mmc), "request already pending\n"); in sunxi_mmc_request()
1085 mrq->cmd->error = -EBUSY; in sunxi_mmc_request()
1086 mmc_request_done(mmc, mrq); in sunxi_mmc_request()
1091 mmc_writel(host, REG_BLKSZ, data->blksz); in sunxi_mmc_request()
1092 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); in sunxi_mmc_request()
1093 sunxi_mmc_start_dma(host, data); in sunxi_mmc_request()
1096 host->mrq = mrq; in sunxi_mmc_request()
1097 host->wait_dma = wait_dma; in sunxi_mmc_request()
1098 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); in sunxi_mmc_request()
1099 mmc_writel(host, REG_CARG, cmd->arg); in sunxi_mmc_request()
1100 mmc_writel(host, REG_CMDR, cmd_val); in sunxi_mmc_request()
1102 spin_unlock_irqrestore(&host->lock, iflags); in sunxi_mmc_request()
1105 static int sunxi_mmc_card_busy(struct mmc_host *mmc) in sunxi_mmc_card_busy() argument
1107 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_card_busy() local
1109 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); in sunxi_mmc_card_busy()
1211 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1212 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1213 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1214 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
1215 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1216 { .compatible = "allwinner,sun20i-d1-mmc", .data = &sun20i_d1_cfg },
1217 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1218 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1219 { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun20i_d1_cfg },
1220 { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
1221 { .compatible = "allwinner,sun50i-h616-mmc", .data = &sun50i_h616_cfg },
1226 static int sunxi_mmc_enable(struct sunxi_mmc_host *host) in sunxi_mmc_enable() argument
1230 if (!IS_ERR(host->reset)) { in sunxi_mmc_enable()
1231 ret = reset_control_reset(host->reset); in sunxi_mmc_enable()
1233 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", in sunxi_mmc_enable()
1239 ret = clk_prepare_enable(host->clk_ahb); in sunxi_mmc_enable()
1241 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); in sunxi_mmc_enable()
1245 ret = clk_prepare_enable(host->clk_mmc); in sunxi_mmc_enable()
1247 dev_err(host->dev, "Enable mmc clk err %d\n", ret); in sunxi_mmc_enable()
1251 ret = clk_prepare_enable(host->clk_output); in sunxi_mmc_enable()
1253 dev_err(host->dev, "Enable output clk err %d\n", ret); in sunxi_mmc_enable()
1257 ret = clk_prepare_enable(host->clk_sample); in sunxi_mmc_enable()
1259 dev_err(host->dev, "Enable sample clk err %d\n", ret); in sunxi_mmc_enable()
1267 ret = sunxi_mmc_reset_host(host); in sunxi_mmc_enable()
1274 clk_disable_unprepare(host->clk_sample); in sunxi_mmc_enable()
1276 clk_disable_unprepare(host->clk_output); in sunxi_mmc_enable()
1278 clk_disable_unprepare(host->clk_mmc); in sunxi_mmc_enable()
1280 clk_disable_unprepare(host->clk_ahb); in sunxi_mmc_enable()
1282 if (!IS_ERR(host->reset)) in sunxi_mmc_enable()
1283 reset_control_assert(host->reset); in sunxi_mmc_enable()
1287 static void sunxi_mmc_disable(struct sunxi_mmc_host *host) in sunxi_mmc_disable() argument
1289 sunxi_mmc_reset_host(host); in sunxi_mmc_disable()
1291 clk_disable_unprepare(host->clk_sample); in sunxi_mmc_disable()
1292 clk_disable_unprepare(host->clk_output); in sunxi_mmc_disable()
1293 clk_disable_unprepare(host->clk_mmc); in sunxi_mmc_disable()
1294 clk_disable_unprepare(host->clk_ahb); in sunxi_mmc_disable()
1296 if (!IS_ERR(host->reset)) in sunxi_mmc_disable()
1297 reset_control_assert(host->reset); in sunxi_mmc_disable()
1300 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, in sunxi_mmc_resource_request() argument
1305 host->cfg = of_device_get_match_data(&pdev->dev); in sunxi_mmc_resource_request()
1306 if (!host->cfg) in sunxi_mmc_resource_request()
1307 return -EINVAL; in sunxi_mmc_resource_request()
1309 ret = mmc_regulator_get_supply(host->mmc); in sunxi_mmc_resource_request()
1313 host->reg_base = devm_platform_ioremap_resource(pdev, 0); in sunxi_mmc_resource_request()
1314 if (IS_ERR(host->reg_base)) in sunxi_mmc_resource_request()
1315 return PTR_ERR(host->reg_base); in sunxi_mmc_resource_request()
1317 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sunxi_mmc_resource_request()
1318 if (IS_ERR(host->clk_ahb)) { in sunxi_mmc_resource_request()
1319 dev_err(&pdev->dev, "Could not get ahb clock\n"); in sunxi_mmc_resource_request()
1320 return PTR_ERR(host->clk_ahb); in sunxi_mmc_resource_request()
1323 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); in sunxi_mmc_resource_request()
1324 if (IS_ERR(host->clk_mmc)) { in sunxi_mmc_resource_request()
1325 dev_err(&pdev->dev, "Could not get mmc clock\n"); in sunxi_mmc_resource_request()
1326 return PTR_ERR(host->clk_mmc); in sunxi_mmc_resource_request()
1329 if (host->cfg->clk_delays) { in sunxi_mmc_resource_request()
1330 host->clk_output = devm_clk_get(&pdev->dev, "output"); in sunxi_mmc_resource_request()
1331 if (IS_ERR(host->clk_output)) { in sunxi_mmc_resource_request()
1332 dev_err(&pdev->dev, "Could not get output clock\n"); in sunxi_mmc_resource_request()
1333 return PTR_ERR(host->clk_output); in sunxi_mmc_resource_request()
1336 host->clk_sample = devm_clk_get(&pdev->dev, "sample"); in sunxi_mmc_resource_request()
1337 if (IS_ERR(host->clk_sample)) { in sunxi_mmc_resource_request()
1338 dev_err(&pdev->dev, "Could not get sample clock\n"); in sunxi_mmc_resource_request()
1339 return PTR_ERR(host->clk_sample); in sunxi_mmc_resource_request()
1343 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in sunxi_mmc_resource_request()
1345 if (PTR_ERR(host->reset) == -EPROBE_DEFER) in sunxi_mmc_resource_request()
1346 return PTR_ERR(host->reset); in sunxi_mmc_resource_request()
1348 ret = sunxi_mmc_enable(host); in sunxi_mmc_resource_request()
1352 host->irq = platform_get_irq(pdev, 0); in sunxi_mmc_resource_request()
1353 if (host->irq < 0) { in sunxi_mmc_resource_request()
1354 ret = host->irq; in sunxi_mmc_resource_request()
1358 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, in sunxi_mmc_resource_request()
1359 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); in sunxi_mmc_resource_request()
1362 sunxi_mmc_disable(host); in sunxi_mmc_resource_request()
1368 struct sunxi_mmc_host *host; in sunxi_mmc_probe() local
1369 struct mmc_host *mmc; in sunxi_mmc_probe() local
1372 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); in sunxi_mmc_probe()
1373 if (!mmc) { in sunxi_mmc_probe()
1374 dev_err(&pdev->dev, "mmc alloc host failed\n"); in sunxi_mmc_probe()
1375 return -ENOMEM; in sunxi_mmc_probe()
1377 platform_set_drvdata(pdev, mmc); in sunxi_mmc_probe()
1379 host = mmc_priv(mmc); in sunxi_mmc_probe()
1380 host->dev = &pdev->dev; in sunxi_mmc_probe()
1381 host->mmc = mmc; in sunxi_mmc_probe()
1382 spin_lock_init(&host->lock); in sunxi_mmc_probe()
1384 ret = sunxi_mmc_resource_request(host, pdev); in sunxi_mmc_probe()
1388 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, in sunxi_mmc_probe()
1389 &host->sg_dma, GFP_KERNEL); in sunxi_mmc_probe()
1390 if (!host->sg_cpu) { in sunxi_mmc_probe()
1391 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); in sunxi_mmc_probe()
1392 ret = -ENOMEM; in sunxi_mmc_probe()
1396 if (host->cfg->ccu_has_timings_switch) { in sunxi_mmc_probe()
1401 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); in sunxi_mmc_probe()
1404 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); in sunxi_mmc_probe()
1410 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); in sunxi_mmc_probe()
1411 host->use_new_timings = false; in sunxi_mmc_probe()
1413 host->use_new_timings = !!ret; in sunxi_mmc_probe()
1415 } else if (host->cfg->needs_new_timings) { in sunxi_mmc_probe()
1417 host->use_new_timings = true; in sunxi_mmc_probe()
1420 mmc->ops = &sunxi_mmc_ops; in sunxi_mmc_probe()
1421 mmc->max_blk_count = 8192; in sunxi_mmc_probe()
1422 mmc->max_blk_size = 4096; in sunxi_mmc_probe()
1423 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); in sunxi_mmc_probe()
1424 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); in sunxi_mmc_probe()
1425 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; in sunxi_mmc_probe()
1427 mmc->f_min = 400000; in sunxi_mmc_probe()
1428 mmc->f_max = 52000000; in sunxi_mmc_probe()
1429 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | in sunxi_mmc_probe()
1439 if ((host->cfg->clk_delays || host->use_new_timings) && in sunxi_mmc_probe()
1440 !of_device_is_compatible(pdev->dev.of_node, in sunxi_mmc_probe()
1441 "allwinner,sun50i-h5-emmc")) in sunxi_mmc_probe()
1442 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sunxi_mmc_probe()
1444 ret = mmc_of_parse(mmc); in sunxi_mmc_probe()
1454 if (!(host->cfg->clk_delays || host->use_new_timings)) { in sunxi_mmc_probe()
1455 mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | in sunxi_mmc_probe()
1457 mmc->caps2 &= ~MMC_CAP2_HS200; in sunxi_mmc_probe()
1461 mmc->caps2 &= ~MMC_CAP2_HS400; in sunxi_mmc_probe()
1463 ret = sunxi_mmc_init_host(host); in sunxi_mmc_probe()
1467 pm_runtime_set_active(&pdev->dev); in sunxi_mmc_probe()
1468 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sunxi_mmc_probe()
1469 pm_runtime_use_autosuspend(&pdev->dev); in sunxi_mmc_probe()
1470 pm_runtime_enable(&pdev->dev); in sunxi_mmc_probe()
1472 ret = mmc_add_host(mmc); in sunxi_mmc_probe()
1476 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n", in sunxi_mmc_probe()
1477 mmc->max_req_size >> 10, in sunxi_mmc_probe()
1478 host->use_new_timings ? ", uses new timings mode" : ""); in sunxi_mmc_probe()
1483 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); in sunxi_mmc_probe()
1485 mmc_free_host(mmc); in sunxi_mmc_probe()
1491 struct mmc_host *mmc = platform_get_drvdata(pdev); in sunxi_mmc_remove() local
1492 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_remove() local
1494 mmc_remove_host(mmc); in sunxi_mmc_remove()
1495 pm_runtime_disable(&pdev->dev); in sunxi_mmc_remove()
1496 if (!pm_runtime_status_suspended(&pdev->dev)) { in sunxi_mmc_remove()
1497 disable_irq(host->irq); in sunxi_mmc_remove()
1498 sunxi_mmc_disable(host); in sunxi_mmc_remove()
1500 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); in sunxi_mmc_remove()
1501 mmc_free_host(mmc); in sunxi_mmc_remove()
1507 struct mmc_host *mmc = dev_get_drvdata(dev); in sunxi_mmc_runtime_resume() local
1508 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_runtime_resume() local
1511 ret = sunxi_mmc_enable(host); in sunxi_mmc_runtime_resume()
1515 sunxi_mmc_init_host(host); in sunxi_mmc_runtime_resume()
1516 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); in sunxi_mmc_runtime_resume()
1517 sunxi_mmc_set_clk(host, &mmc->ios); in sunxi_mmc_runtime_resume()
1518 enable_irq(host->irq); in sunxi_mmc_runtime_resume()
1525 struct mmc_host *mmc = dev_get_drvdata(dev); in sunxi_mmc_runtime_suspend() local
1526 struct sunxi_mmc_host *host = mmc_priv(mmc); in sunxi_mmc_runtime_suspend() local
1533 disable_irq(host->irq); in sunxi_mmc_runtime_suspend()
1534 sunxi_mmc_reset_host(host); in sunxi_mmc_runtime_suspend()
1535 sunxi_mmc_disable(host); in sunxi_mmc_runtime_suspend()
1551 .name = "sunxi-mmc",
1561 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1564 MODULE_ALIAS("platform:sunxi-mmc");