Lines Matching +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy
1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
29 /* PHY Registers */
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
109 "ti,itap-del-sel-legacy",
111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
112 "ti,itap-del-sel-mmc-hs",
114 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
115 "ti,itap-del-sel-sd-hs",
117 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
118 "ti,itap-del-sel-sdr12",
120 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
121 "ti,itap-del-sel-sdr25",
123 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
126 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
129 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
132 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
133 "ti,itap-del-sel-ddr52",
135 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
138 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
186 /* Disable delay chain mode */ in sdhci_am654_setup_dll()
187 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, in sdhci_am654_setup_dll()
190 if (sdhci_am654->flags & FREQSEL_2_BIT) { in sdhci_am654_setup_dll()
205 /* Configure PHY DLL frequency */ in sdhci_am654_setup_dll()
208 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_dll()
219 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, in sdhci_am654_setup_dll()
224 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; in sdhci_am654_setup_dll()
228 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; in sdhci_am654_setup_dll()
229 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); in sdhci_am654_setup_dll()
232 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, in sdhci_am654_setup_dll()
238 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, in sdhci_am654_setup_dll()
241 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); in sdhci_am654_setup_dll()
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_am654_write_itapdly()
252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, in sdhci_am654_write_itapdly()
254 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, in sdhci_am654_write_itapdly()
256 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); in sdhci_am654_write_itapdly()
264 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); in sdhci_am654_setup_delay_chain()
268 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_delay_chain()
270 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], in sdhci_am654_setup_delay_chain()
271 sdhci_am654->itap_del_ena[timing]); in sdhci_am654_setup_delay_chain()
278 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_set_clock()
282 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); in sdhci_am654_set_clock()
286 /* Setup Output TAP delay */ in sdhci_am654_set_clock()
287 otap_del_sel = sdhci_am654->otap_del_sel[timing]; in sdhci_am654_set_clock()
295 if (sdhci_am654->flags & STRBSEL_4_BIT) in sdhci_am654_set_clock()
300 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; in sdhci_am654_set_clock()
303 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_am654_set_clock()
307 sdhci_am654->dll_enable = true; in sdhci_am654_set_clock()
310 sdhci_am654->itap_del_ena[timing] = 0x1; in sdhci_am654_set_clock()
311 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1]; in sdhci_am654_set_clock()
314 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], in sdhci_am654_set_clock()
315 sdhci_am654->itap_del_ena[timing]); in sdhci_am654_set_clock()
318 sdhci_am654->dll_enable = false; in sdhci_am654_set_clock()
321 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, in sdhci_am654_set_clock()
322 sdhci_am654->clkbuf_sel); in sdhci_am654_set_clock()
330 unsigned char timing = host->mmc->ios.timing; in sdhci_j721e_4bit_set_clock()
336 /* Setup Output TAP delay */ in sdhci_j721e_4bit_set_clock()
337 otap_del_sel = sdhci_am654->otap_del_sel[timing]; in sdhci_j721e_4bit_set_clock()
343 /* Setup Input TAP delay */ in sdhci_j721e_4bit_set_clock()
344 itap_del_ena = sdhci_am654->itap_del_ena[timing]; in sdhci_j721e_4bit_set_clock()
345 itap_del_sel = sdhci_am654->itap_del_sel[timing]; in sdhci_j721e_4bit_set_clock()
351 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_j721e_4bit_set_clock()
353 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_j721e_4bit_set_clock()
354 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); in sdhci_j721e_4bit_set_clock()
355 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, in sdhci_j721e_4bit_set_clock()
356 sdhci_am654->clkbuf_sel); in sdhci_j721e_4bit_set_clock()
368 if ((sdhci_am654->quirks & SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA) && in sdhci_am654_start_signal_voltage_switch()
369 ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { in sdhci_am654_start_signal_voltage_switch()
370 if (!IS_ERR(mmc->supply.vqmmc)) { in sdhci_am654_start_signal_voltage_switch()
375 return -EIO; in sdhci_am654_start_signal_voltage_switch()
386 writeb(val, host->ioaddr + reg); in sdhci_am654_write_power_on()
388 return readb(host->ioaddr + reg); in sdhci_am654_write_power_on()
394 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_write_b()
410 writeb(val, host->ioaddr + reg); in sdhci_am654_write_b()
422 dev_info(mmc_dev(host->mmc), "Power on failed\n"); in sdhci_am654_write_b()
434 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { in sdhci_am654_reset()
465 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_am654_cqhci_irq()
471 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
478 struct device *dev = mmc_dev(host->mmc); in sdhci_am654_calculate_itap()
480 int prev_fail_end = -1; in sdhci_am654_calculate_itap()
486 return -1; in sdhci_am654_calculate_itap()
489 if (fail_window->length == ITAPDLY_LENGTH) { in sdhci_am654_calculate_itap()
492 return -1; in sdhci_am654_calculate_itap()
495 first_fail_start = fail_window->start; in sdhci_am654_calculate_itap()
496 last_fail_end = fail_window[num_fails - 1].end; in sdhci_am654_calculate_itap()
501 pass_length = start_fail - (prev_fail_end + 1); in sdhci_am654_calculate_itap()
511 pass_length = ITAPDLY_LAST_INDEX - last_fail_end; in sdhci_am654_calculate_itap()
513 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; in sdhci_am654_calculate_itap()
533 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_do_tuning()
535 struct device *dev = mmc_dev(host->mmc); in sdhci_am654_do_tuning()
543 sdhci_am654->itap_del_ena[timing] = 0x1; in sdhci_am654_do_tuning()
546 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); in sdhci_am654_do_tuning()
548 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); in sdhci_am654_do_tuning()
569 sdhci_am654->dll_enable); in sdhci_am654_do_tuning()
577 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_platform_execute_tuning()
578 struct device *dev = mmc_dev(host->mmc); in sdhci_am654_platform_execute_tuning()
585 } while (++sdhci_am654->tuning_loop < RETRY_TUNING_MAX); in sdhci_am654_platform_execute_tuning()
589 return -1; in sdhci_am654_platform_execute_tuning()
593 sdhci_am654_write_itapdly(sdhci_am654, itapdly, sdhci_am654->itap_del_ena[timing]); in sdhci_am654_platform_execute_tuning()
595 sdhci_am654->itap_del_sel[timing] = itapdly; in sdhci_am654_platform_execute_tuning()
710 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), in sdhci_am654_cqe_add_host()
713 return -ENOMEM; in sdhci_am654_cqe_add_host()
715 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; in sdhci_am654_cqe_add_host()
716 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; in sdhci_am654_cqe_add_host()
717 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_am654_cqe_add_host()
718 cq_host->ops = &sdhci_am654_cqhci_ops; in sdhci_am654_cqe_add_host()
720 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_am654_cqe_add_host()
722 return cqhci_init(cq_host, host->mmc, 1); in sdhci_am654_cqe_add_host()
728 struct device *dev = mmc_dev(host->mmc); in sdhci_am654_get_otap_delay()
735 &sdhci_am654->otap_del_sel[i]); in sdhci_am654_get_otap_delay()
738 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); in sdhci_am654_get_otap_delay()
745 * if an otap-del-sel value is not found in sdhci_am654_get_otap_delay()
748 host->mmc->caps &= ~td[i].capability; in sdhci_am654_get_otap_delay()
750 host->mmc->caps2 &= ~td[i].capability; in sdhci_am654_get_otap_delay()
755 &sdhci_am654->itap_del_sel[i]); in sdhci_am654_get_otap_delay()
757 sdhci_am654->itap_del_ena[i] = 0x1; in sdhci_am654_get_otap_delay()
775 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); in sdhci_am654_init()
777 if (sdhci_am654->flags & DLL_CALIB) { in sdhci_am654_init()
778 regmap_read(sdhci_am654->base, PHY_STAT1, &val); in sdhci_am654_init()
781 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_init()
783 ret = regmap_read_poll_timeout(sdhci_am654->base, in sdhci_am654_init()
793 if (sdhci_am654->flags & IOMUX_PRESENT) in sdhci_am654_init()
794 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_init()
798 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_am654_init()
801 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, in sdhci_am654_init()
805 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, in sdhci_am654_init()
808 /* Use to re-execute tuning */ in sdhci_am654_init()
809 sdhci_am654->tuning_loop = 0; in sdhci_am654_init()
837 struct device *dev = &pdev->dev; in sdhci_am654_get_of_property()
841 if (sdhci_am654->flags & DLL_PRESENT) { in sdhci_am654_get_of_property()
842 ret = device_property_read_u32(dev, "ti,trm-icp", in sdhci_am654_get_of_property()
843 &sdhci_am654->trm_icp); in sdhci_am654_get_of_property()
847 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", in sdhci_am654_get_of_property()
854 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; in sdhci_am654_get_of_property()
857 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; in sdhci_am654_get_of_property()
860 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; in sdhci_am654_get_of_property()
863 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; in sdhci_am654_get_of_property()
866 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; in sdhci_am654_get_of_property()
870 return -EINVAL; in sdhci_am654_get_of_property()
874 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); in sdhci_am654_get_of_property()
875 device_property_read_u32(dev, "ti,clkbuf-sel", in sdhci_am654_get_of_property()
876 &sdhci_am654->clkbuf_sel); in sdhci_am654_get_of_property()
878 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) in sdhci_am654_get_of_property()
879 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; in sdhci_am654_get_of_property()
888 .compatible = "ti,am654-sdhci-5.1",
892 .compatible = "ti,j721e-sdhci-8bit",
896 .compatible = "ti,j721e-sdhci-4bit",
900 .compatible = "ti,am64-sdhci-8bit",
904 .compatible = "ti,am64-sdhci-4bit",
908 .compatible = "ti,am62-sdhci",
924 struct device *dev = &pdev->dev; in sdhci_am654_probe()
928 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); in sdhci_am654_probe()
929 drvdata = match->data; in sdhci_am654_probe()
933 if (soc && soc->data) in sdhci_am654_probe()
934 drvdata = soc->data; in sdhci_am654_probe()
936 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); in sdhci_am654_probe()
942 sdhci_am654->flags = drvdata->flags; in sdhci_am654_probe()
943 sdhci_am654->quirks = drvdata->quirks; in sdhci_am654_probe()
952 pltfm_host->clk = clk_xin; in sdhci_am654_probe()
960 sdhci_am654->base = devm_regmap_init_mmio(dev, base, in sdhci_am654_probe()
962 if (IS_ERR(sdhci_am654->base)) { in sdhci_am654_probe()
964 ret = PTR_ERR(sdhci_am654->base); in sdhci_am654_probe()
972 ret = mmc_of_parse(host->mmc); in sdhci_am654_probe()
978 host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch; in sdhci_am654_probe()
979 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; in sdhci_am654_probe()
986 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_am654_probe()
1002 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_probe()
1016 struct device *dev = &pdev->dev; in sdhci_am654_remove()
1024 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_remove()
1039 if (sdhci_am654->flags & DLL_CALIB) { in sdhci_am654_restore()
1040 regmap_read(sdhci_am654->base, PHY_STAT1, &val); in sdhci_am654_restore()
1043 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_restore()
1045 ret = regmap_read_poll_timeout(sdhci_am654->base, in sdhci_am654_restore()
1055 if (sdhci_am654->flags & IOMUX_PRESENT) in sdhci_am654_restore()
1056 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_restore()
1060 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_am654_restore()
1063 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, in sdhci_am654_restore()
1066 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); in sdhci_am654_restore()
1069 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, in sdhci_am654_restore()
1081 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_am654_runtime_suspend()
1082 mmc_retune_needed(host->mmc); in sdhci_am654_runtime_suspend()
1084 ret = cqhci_suspend(host->mmc); in sdhci_am654_runtime_suspend()
1093 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_runtime_suspend()
1104 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_am654_runtime_resume()
1116 ret = cqhci_resume(host->mmc); in sdhci_am654_runtime_resume()
1133 .name = "sdhci-am654",