Lines Matching +full:sd +full:- +full:uhs +full:- +full:ddr50
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
103 * VDD2 - UHS2 or PCIe/NVMe
174 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
196 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
243 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
252 /* 4C-4F reserved for more max current */
259 /* 55-57 reserved */
264 /* 60-FB reserved */
272 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
302 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
304 /* ADMA2 32-bit DMA descriptor size */
307 /* ADMA2 32-bit descriptor */
316 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
320 * alignment for the descriptor table even in 32-bit DMA mode. Memory
326 * ADMA2 64-bit DMA descriptor size
327 * According to SD Host Controller spec v4.10, there are two kinds of
328 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
330 * register, 128-bit Descriptor will be selected.
332 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
335 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
368 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
394 /* Controller can only DMA from 32-bit aligned addresses */
408 /* Controller does not provide transfer-complete interrupt when not busy */
412 /* Controller reports inverted write-protect state */
422 /* Controller cannot do multi-block transfers */
424 /* Controller can only handle 1-bit data transfers */
436 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
449 /* Controller has a non-standard host control register */
453 /* Controller does not support DDR50 */
457 /* Controller does not support 64-bit DMA */
461 /* Capability register bit-63 indicates HS400 support */
479 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
480 * for other purposes. Consequently we support 16-bit block count by default.
481 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
518 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
533 u8 drv_type; /* Current UHS-I driver type */
534 bool reinit_uhs; /* Force UHS-related re-initialization */
605 unsigned int tuning_count; /* Timer count for re-tuning */
606 unsigned int tuning_mode; /* Re-tuning mode supported by host */
607 unsigned int tuning_err; /* Error code for re-tuning */
657 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
676 if (unlikely(host->ops->write_l)) in sdhci_writel()
677 host->ops->write_l(host, val, reg); in sdhci_writel()
679 writel(val, host->ioaddr + reg); in sdhci_writel()
684 if (unlikely(host->ops->write_w)) in sdhci_writew()
685 host->ops->write_w(host, val, reg); in sdhci_writew()
687 writew(val, host->ioaddr + reg); in sdhci_writew()
692 if (unlikely(host->ops->write_b)) in sdhci_writeb()
693 host->ops->write_b(host, val, reg); in sdhci_writeb()
695 writeb(val, host->ioaddr + reg); in sdhci_writeb()
700 if (unlikely(host->ops->read_l)) in sdhci_readl()
701 return host->ops->read_l(host, reg); in sdhci_readl()
703 return readl(host->ioaddr + reg); in sdhci_readl()
708 if (unlikely(host->ops->read_w)) in sdhci_readw()
709 return host->ops->read_w(host, reg); in sdhci_readw()
711 return readw(host->ioaddr + reg); in sdhci_readw()
716 if (unlikely(host->ops->read_b)) in sdhci_readb()
717 return host->ops->read_b(host, reg); in sdhci_readb()
719 return readb(host->ioaddr + reg); in sdhci_readb()
726 writel(val, host->ioaddr + reg); in sdhci_writel()
731 writew(val, host->ioaddr + reg); in sdhci_writew()
736 writeb(val, host->ioaddr + reg); in sdhci_writeb()
741 return readl(host->ioaddr + reg); in sdhci_readl()
746 return readw(host->ioaddr + reg); in sdhci_readw()
751 return readb(host->ioaddr + reg); in sdhci_readb()
761 return host->private; in sdhci_priv()