Lines Matching refs:scratch_32
169 u32 scratch_32; in o2_pci_set_baseclk() local
172 O2_SD_PLL_SETTING, &scratch_32); in o2_pci_set_baseclk()
174 scratch_32 &= 0x0000FFFF; in o2_pci_set_baseclk()
175 scratch_32 |= value; in o2_pci_set_baseclk()
178 O2_SD_PLL_SETTING, scratch_32); in o2_pci_set_baseclk()
248 u32 scratch_32 = 0; in sdhci_o2_dll_recovery() local
263 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
264 scratch_32 |= O2_PLL_SOFT_RESET; in sdhci_o2_dll_recovery()
265 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
269 &scratch_32); in sdhci_o2_dll_recovery()
271 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; in sdhci_o2_dll_recovery()
272 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); in sdhci_o2_dll_recovery()
434 u32 scratch_32; in o2_pci_led_enable() local
438 O2_SD_FUNC_REG0, &scratch_32); in o2_pci_led_enable()
442 scratch_32 &= ~O2_SD_FREG0_LEDOFF; in o2_pci_led_enable()
444 O2_SD_FUNC_REG0, scratch_32); in o2_pci_led_enable()
447 O2_SD_TEST_REG, &scratch_32); in o2_pci_led_enable()
451 scratch_32 |= O2_SD_LED_ENABLE; in o2_pci_led_enable()
453 O2_SD_TEST_REG, scratch_32); in o2_pci_led_enable()
458 u32 scratch_32; in sdhci_pci_o2_fujin2_pci_init() local
461 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
464 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); in sdhci_pci_o2_fujin2_pci_init()
465 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
468 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
471 scratch_32 &= ~((1 << 19) | (1 << 11)); in sdhci_pci_o2_fujin2_pci_init()
472 scratch_32 |= (1 << 10); in sdhci_pci_o2_fujin2_pci_init()
473 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
476 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
479 scratch_32 |= (1 << 4); in sdhci_pci_o2_fujin2_pci_init()
480 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
486 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
489 scratch_32 &= ~(3 << 12); in sdhci_pci_o2_fujin2_pci_init()
490 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
493 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
496 scratch_32 &= ~(0x01FE); in sdhci_pci_o2_fujin2_pci_init()
497 scratch_32 |= 0x00CC; in sdhci_pci_o2_fujin2_pci_init()
498 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
501 O2_SD_TUNING_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
504 scratch_32 &= ~(0x000000FF); in sdhci_pci_o2_fujin2_pci_init()
505 scratch_32 |= 0x00000066; in sdhci_pci_o2_fujin2_pci_init()
506 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
510 O2_SD_UHS2_L1_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
513 scratch_32 &= ~(0x000000FC); in sdhci_pci_o2_fujin2_pci_init()
514 scratch_32 |= 0x00000084; in sdhci_pci_o2_fujin2_pci_init()
515 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
518 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
521 scratch_32 &= ~((1 << 21) | (1 << 30)); in sdhci_pci_o2_fujin2_pci_init()
523 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
526 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
529 scratch_32 &= ~(0xf0000000); in sdhci_pci_o2_fujin2_pci_init()
530 scratch_32 |= 0x30000000; in sdhci_pci_o2_fujin2_pci_init()
531 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
534 O2_SD_MISC_CTRL4, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
537 scratch_32 &= ~(0x000f0000); in sdhci_pci_o2_fujin2_pci_init()
538 scratch_32 |= 0x00080000; in sdhci_pci_o2_fujin2_pci_init()
539 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
582 u32 scratch_32; in sdhci_pci_o2_set_clock() local
611 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_set_clock()
613 if ((scratch_32 & 0xFFFF0000) != dmdn_208m) in sdhci_pci_o2_set_clock()
616 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_set_clock()
618 if ((scratch_32 & 0xFFFF0000) != dmdn_200m) in sdhci_pci_o2_set_clock()
622 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); in sdhci_pci_o2_set_clock()
623 scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); in sdhci_pci_o2_set_clock()
624 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); in sdhci_pci_o2_set_clock()
700 u32 scratch_32 = 0; in sdhci_pci_o2_set_power() local
712 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); in sdhci_pci_o2_set_power()
713 scratch_32 &= ~(O2_SD_SEL_DLL); in sdhci_pci_o2_set_power()
714 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); in sdhci_pci_o2_set_power()
815 u32 scratch_32; in sdhci_pci_o2_probe() local
887 &scratch_32); in sdhci_pci_o2_probe()
890 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); in sdhci_pci_o2_probe()
893 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { in sdhci_pci_o2_probe()
894 scratch_32 = 0x25100000; in sdhci_pci_o2_probe()
896 o2_pci_set_baseclk(chip, scratch_32); in sdhci_pci_o2_probe()
899 &scratch_32); in sdhci_pci_o2_probe()
904 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; in sdhci_pci_o2_probe()
907 scratch_32); in sdhci_pci_o2_probe()
922 O2_SD_CLK_SETTING, &scratch_32); in sdhci_pci_o2_probe()
926 scratch_32 &= ~(0xFF00); in sdhci_pci_o2_probe()
927 scratch_32 |= 0x07E0C800; in sdhci_pci_o2_probe()
929 O2_SD_CLK_SETTING, scratch_32); in sdhci_pci_o2_probe()
932 O2_SD_CLKREQ, &scratch_32); in sdhci_pci_o2_probe()
935 scratch_32 |= 0x3; in sdhci_pci_o2_probe()
936 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); in sdhci_pci_o2_probe()
939 O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_probe()
943 scratch_32 &= ~(0x1F3F070E); in sdhci_pci_o2_probe()
944 scratch_32 |= 0x18270106; in sdhci_pci_o2_probe()
946 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
950 O2_SD_CAP_REG2, &scratch_32); in sdhci_pci_o2_probe()
953 scratch_32 &= ~(0xE0); in sdhci_pci_o2_probe()
955 O2_SD_CAP_REG2, scratch_32); in sdhci_pci_o2_probe()
980 O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_probe()
984 if ((scratch_32 & 0xff000000) == 0x01000000) { in sdhci_pci_o2_probe()
985 scratch_32 &= 0x0000FFFF; in sdhci_pci_o2_probe()
986 scratch_32 |= 0x1F340000; in sdhci_pci_o2_probe()
989 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
991 scratch_32 &= 0x0000FFFF; in sdhci_pci_o2_probe()
992 scratch_32 |= 0x25100000; in sdhci_pci_o2_probe()
995 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
999 &scratch_32); in sdhci_pci_o2_probe()
1002 scratch_32 |= (1 << 22); in sdhci_pci_o2_probe()
1004 O2_SD_FUNC_REG4, scratch_32); in sdhci_pci_o2_probe()
1011 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32); in sdhci_pci_o2_probe()
1012 scratch_32 &= 0xFFE7FFFF; in sdhci_pci_o2_probe()
1013 scratch_32 |= 0x00180000; in sdhci_pci_o2_probe()
1014 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32); in sdhci_pci_o2_probe()
1052 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); in sdhci_pci_o2_probe()
1053 scratch_32 &= 0xFF0FFF00; in sdhci_pci_o2_probe()
1054 scratch_32 |= 0x00B0003B; in sdhci_pci_o2_probe()
1055 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); in sdhci_pci_o2_probe()