Lines Matching +full:host +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/mmc/host.h>
18 #include "sdhci-pci.h"
84 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) in sdhci_o2_wait_card_detect_stable() argument
94 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable()
101 mmc_hostname(host->mmc)); in sdhci_o2_wait_card_detect_stable()
102 sdhci_dumpregs(host); in sdhci_o2_wait_card_detect_stable()
109 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) in sdhci_o2_enable_internal_clock() argument
116 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
118 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
121 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
125 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
132 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
137 mmc_hostname(host->mmc)); in sdhci_o2_enable_internal_clock()
138 sdhci_dumpregs(host); in sdhci_o2_enable_internal_clock()
146 sdhci_o2_wait_card_detect_stable(host); in sdhci_o2_enable_internal_clock()
150 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
152 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
157 struct sdhci_host *host = mmc_priv(mmc); in sdhci_o2_get_cd() local
159 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) in sdhci_o2_get_cd()
160 sdhci_o2_enable_internal_clock(host); in sdhci_o2_get_cd()
162 sdhci_o2_wait_card_detect_stable(host); in sdhci_o2_get_cd()
164 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd()
167 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) in o2_pci_set_baseclk() argument
171 pci_read_config_dword(chip->pdev, in o2_pci_set_baseclk()
177 pci_write_config_dword(chip->pdev, in o2_pci_set_baseclk()
181 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) in sdhci_o2_pll_dll_wdt_control() argument
183 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control()
187 * This function is used to detect dll lock status.
189 * with very short interval which needs to be polled
192 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) in sdhci_o2_wait_dll_detect_lock() argument
196 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, in sdhci_o2_wait_dll_detect_lock()
200 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) in sdhci_o2_set_tuning_mode() argument
205 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); in sdhci_o2_set_tuning_mode()
207 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); in sdhci_o2_set_tuning_mode()
210 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) in __sdhci_o2_execute_tuning() argument
214 sdhci_send_tuning(host, opcode); in __sdhci_o2_execute_tuning()
217 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_o2_execute_tuning()
221 host->tuning_done = true; in __sdhci_o2_execute_tuning()
225 mmc_hostname(host->mmc)); in __sdhci_o2_execute_tuning()
232 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", in __sdhci_o2_execute_tuning()
233 mmc_hostname(host->mmc)); in __sdhci_o2_execute_tuning()
234 sdhci_reset_tuning(host); in __sdhci_o2_execute_tuning()
238 * This function is used to fix o2 dll shift issue.
239 * It isn't necessary to detect card present before recovery.
244 static int sdhci_o2_dll_recovery(struct sdhci_host *host) in sdhci_o2_dll_recovery() argument
249 struct sdhci_pci_slot *slot = sdhci_priv(host); in sdhci_o2_dll_recovery()
250 struct sdhci_pci_chip *chip = slot->chip; in sdhci_o2_dll_recovery() local
254 pci_read_config_byte(chip->pdev, in sdhci_o2_dll_recovery()
257 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_o2_dll_recovery()
258 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { in sdhci_o2_dll_recovery()
260 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_o2_dll_recovery()
263 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
265 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
267 pci_read_config_dword(chip->pdev, in sdhci_o2_dll_recovery()
272 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); in sdhci_o2_dll_recovery()
273 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); in sdhci_o2_dll_recovery()
277 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); in sdhci_o2_dll_recovery()
279 if (sdhci_o2_get_cd(host->mmc)) { in sdhci_o2_dll_recovery()
285 if (sdhci_o2_wait_dll_detect_lock(host)) { in sdhci_o2_dll_recovery()
287 sdhci_writeb(host, scratch_8, in sdhci_o2_dll_recovery()
292 mmc_hostname(host->mmc), in sdhci_o2_dll_recovery()
293 o2_host->dll_adjust_count); in sdhci_o2_dll_recovery()
297 mmc_hostname(host->mmc)); in sdhci_o2_dll_recovery()
301 o2_host->dll_adjust_count++; in sdhci_o2_dll_recovery()
303 if (!ret && o2_host->dll_adjust_count == DMDN_SZ) in sdhci_o2_dll_recovery()
305 mmc_hostname(host->mmc)); in sdhci_o2_dll_recovery()
307 pci_read_config_byte(chip->pdev, in sdhci_o2_dll_recovery()
310 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_o2_dll_recovery()
316 struct sdhci_host *host = mmc_priv(mmc); in sdhci_o2_execute_tuning() local
317 struct sdhci_pci_slot *slot = sdhci_priv(host); in sdhci_o2_execute_tuning()
318 struct sdhci_pci_chip *chip = slot->chip; in sdhci_o2_execute_tuning() local
326 * This handler implements the hardware tuning that is specific to in sdhci_o2_execute_tuning()
327 * this controller. Fall back to the standard method for other TIMING. in sdhci_o2_execute_tuning()
329 if ((host->timing != MMC_TIMING_MMC_HS200) && in sdhci_o2_execute_tuning()
330 (host->timing != MMC_TIMING_UHS_SDR104) && in sdhci_o2_execute_tuning()
331 (host->timing != MMC_TIMING_UHS_SDR50)) in sdhci_o2_execute_tuning()
335 return -EINVAL; in sdhci_o2_execute_tuning()
338 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
340 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
343 switch (chip->pdev->device) { in sdhci_o2_execute_tuning()
350 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
352 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
354 if (host->timing == MMC_TIMING_MMC_HS200 || in sdhci_o2_execute_tuning()
355 host->timing == MMC_TIMING_UHS_SDR104) { in sdhci_o2_execute_tuning()
357 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); in sdhci_o2_execute_tuning()
359 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_o2_execute_tuning()
361 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ in sdhci_o2_execute_tuning()
362 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); in sdhci_o2_execute_tuning()
365 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); in sdhci_o2_execute_tuning()
368 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); in sdhci_o2_execute_tuning()
370 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_o2_execute_tuning()
374 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
376 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); in sdhci_o2_execute_tuning()
383 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, in sdhci_o2_execute_tuning()
386 mmc_hostname(host->mmc)); in sdhci_o2_execute_tuning()
391 if (!sdhci_o2_wait_dll_detect_lock(host)) in sdhci_o2_execute_tuning()
392 if (!sdhci_o2_dll_recovery(host)) { in sdhci_o2_execute_tuning()
394 mmc_hostname(host->mmc)); in sdhci_o2_execute_tuning()
395 return -EINVAL; in sdhci_o2_execute_tuning()
398 * o2 sdhci host didn't support 8bit emmc tuning in sdhci_o2_execute_tuning()
400 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { in sdhci_o2_execute_tuning()
401 current_bus_width = mmc->ios.bus_width; in sdhci_o2_execute_tuning()
402 mmc->ios.bus_width = MMC_BUS_WIDTH_4; in sdhci_o2_execute_tuning()
403 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); in sdhci_o2_execute_tuning()
406 sdhci_o2_set_tuning_mode(host); in sdhci_o2_execute_tuning()
408 sdhci_start_tuning(host); in sdhci_o2_execute_tuning()
410 __sdhci_o2_execute_tuning(host, opcode); in sdhci_o2_execute_tuning()
412 sdhci_end_tuning(host); in sdhci_o2_execute_tuning()
415 mmc->ios.bus_width = MMC_BUS_WIDTH_8; in sdhci_o2_execute_tuning()
416 sdhci_set_bus_width(host, current_bus_width); in sdhci_o2_execute_tuning()
420 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
422 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); in sdhci_o2_execute_tuning()
424 sdhci_reset(host, SDHCI_RESET_CMD); in sdhci_o2_execute_tuning()
425 sdhci_reset(host, SDHCI_RESET_DATA); in sdhci_o2_execute_tuning()
427 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_o2_execute_tuning()
431 static void o2_pci_led_enable(struct sdhci_pci_chip *chip) in o2_pci_led_enable() argument
436 /* Set led of SD host function enable */ in o2_pci_led_enable()
437 ret = pci_read_config_dword(chip->pdev, in o2_pci_led_enable()
443 pci_write_config_dword(chip->pdev, in o2_pci_led_enable()
446 ret = pci_read_config_dword(chip->pdev, in o2_pci_led_enable()
452 pci_write_config_dword(chip->pdev, in o2_pci_led_enable()
456 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) in sdhci_pci_o2_fujin2_pci_init() argument
461 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
465 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
468 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
473 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
476 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
480 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
483 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); in sdhci_pci_o2_fujin2_pci_init()
486 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
490 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
492 /* Set Max power supply capability of SD host */ in sdhci_pci_o2_fujin2_pci_init()
493 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
498 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
500 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_fujin2_pci_init()
506 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
509 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_fujin2_pci_init()
515 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
518 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
523 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
526 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
531 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
533 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_fujin2_pci_init()
539 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
542 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, in sdhci_pci_o2_enable_msi() argument
543 struct sdhci_host *host) in sdhci_pci_o2_enable_msi() argument
547 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); in sdhci_pci_o2_enable_msi()
550 mmc_hostname(host->mmc)); in sdhci_pci_o2_enable_msi()
554 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, in sdhci_pci_o2_enable_msi()
558 mmc_hostname(host->mmc), ret); in sdhci_pci_o2_enable_msi()
562 host->irq = pci_irq_vector(chip->pdev, 0); in sdhci_pci_o2_enable_msi()
565 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) in sdhci_o2_enable_clk() argument
569 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_o2_enable_clk()
571 sdhci_o2_enable_internal_clock(host); in sdhci_o2_enable_clk()
572 if (sdhci_o2_get_cd(host->mmc)) { in sdhci_o2_enable_clk()
574 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); in sdhci_o2_enable_clk()
578 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) in sdhci_pci_o2_set_clock() argument
584 struct sdhci_pci_slot *slot = sdhci_priv(host); in sdhci_pci_o2_set_clock()
585 struct sdhci_pci_chip *chip = slot->chip; in sdhci_pci_o2_set_clock() local
587 host->mmc->actual_clock = 0; in sdhci_pci_o2_set_clock()
589 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_pci_o2_set_clock()
595 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); in sdhci_pci_o2_set_clock()
597 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_set_clock()
599 if (chip->pdev->device == PCI_DEVICE_ID_O2_GG8_9860 || in sdhci_pci_o2_set_clock()
600 chip->pdev->device == PCI_DEVICE_ID_O2_GG8_9861 || in sdhci_pci_o2_set_clock()
601 chip->pdev->device == PCI_DEVICE_ID_O2_GG8_9862 || in sdhci_pci_o2_set_clock()
602 chip->pdev->device == PCI_DEVICE_ID_O2_GG8_9863) { in sdhci_pci_o2_set_clock()
610 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { in sdhci_pci_o2_set_clock()
611 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_set_clock()
614 o2_pci_set_baseclk(chip, dmdn_208m); in sdhci_pci_o2_set_clock()
616 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_set_clock()
619 o2_pci_set_baseclk(chip, dmdn_200m); in sdhci_pci_o2_set_clock()
622 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); in sdhci_pci_o2_set_clock()
624 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); in sdhci_pci_o2_set_clock()
627 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); in sdhci_pci_o2_set_clock()
629 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_set_clock()
631 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_pci_o2_set_clock()
632 sdhci_o2_enable_clk(host, clk); in sdhci_pci_o2_set_clock()
637 struct sdhci_host *host = mmc_priv(mmc); in sdhci_pci_o2_init_sd_express() local
638 struct sdhci_pci_slot *slot = sdhci_priv(host); in sdhci_pci_o2_init_sd_express()
639 struct sdhci_pci_chip *chip = slot->chip; in sdhci_pci_o2_init_sd_express() local
645 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); in sdhci_pci_o2_init_sd_express()
648 scratch8 = sdhci_readb(host, SDHCI_POWER_CONTROL); in sdhci_pci_o2_init_sd_express()
650 if (host->mmc->ios.timing == MMC_TIMING_SD_EXP_1_2V && in sdhci_pci_o2_init_sd_express()
651 host->mmc->caps2 & MMC_CAP2_SD_EXP_1_2V) { in sdhci_pci_o2_init_sd_express()
657 sdhci_writeb(host, scratch8, SDHCI_POWER_CONTROL); in sdhci_pci_o2_init_sd_express()
660 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch8); in sdhci_pci_o2_init_sd_express()
662 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch8); in sdhci_pci_o2_init_sd_express()
666 1, 30000, false, host, O2_SD_EXP_INT_REG); in sdhci_pci_o2_init_sd_express()
669 /* Switch to PCIe mode */ in sdhci_pci_o2_init_sd_express()
670 scratch16 = sdhci_readw(host, O2_SD_PCIE_SWITCH); in sdhci_pci_o2_init_sd_express()
672 sdhci_writew(host, scratch16, O2_SD_PCIE_SWITCH); in sdhci_pci_o2_init_sd_express()
675 scratch8 = sdhci_readb(host, SDHCI_POWER_CONTROL); in sdhci_pci_o2_init_sd_express()
677 sdhci_writeb(host, scratch8, SDHCI_POWER_CONTROL); in sdhci_pci_o2_init_sd_express()
680 pci_read_config_word(chip->pdev, O2_SD_PARA_SET_REG1, &scratch16); in sdhci_pci_o2_init_sd_express()
682 pci_write_config_word(chip->pdev, O2_SD_PARA_SET_REG1, scratch16); in sdhci_pci_o2_init_sd_express()
684 host->mmc->ios.timing = MMC_TIMING_LEGACY; in sdhci_pci_o2_init_sd_express()
685 pr_info("%s: Express card initialization failed, falling back to Legacy\n", in sdhci_pci_o2_init_sd_express()
686 mmc_hostname(host->mmc)); in sdhci_pci_o2_init_sd_express()
689 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch8); in sdhci_pci_o2_init_sd_express()
691 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch8); in sdhci_pci_o2_init_sd_express()
696 static void sdhci_pci_o2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) in sdhci_pci_o2_set_power() argument
698 struct sdhci_pci_chip *chip; in sdhci_pci_o2_set_power() local
699 struct sdhci_pci_slot *slot = sdhci_priv(host); in sdhci_pci_o2_set_power()
703 chip = slot->chip; in sdhci_pci_o2_set_power()
707 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); in sdhci_pci_o2_set_power()
709 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_pci_o2_set_power()
711 /* Set PCR 0x354[16] to switch Clock Source back to OPE Clock */ in sdhci_pci_o2_set_power()
712 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); in sdhci_pci_o2_set_power()
714 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); in sdhci_pci_o2_set_power()
717 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); in sdhci_pci_o2_set_power()
719 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); in sdhci_pci_o2_set_power()
722 sdhci_set_power(host, mode, vdd); in sdhci_pci_o2_set_power()
727 struct sdhci_pci_chip *chip; in sdhci_pci_o2_probe_slot() local
728 struct sdhci_host *host; in sdhci_pci_o2_probe_slot() local
733 chip = slot->chip; in sdhci_pci_o2_probe_slot()
734 host = slot->host; in sdhci_pci_o2_probe_slot()
736 o2_host->dll_adjust_count = 0; in sdhci_pci_o2_probe_slot()
737 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot()
740 * mmc_select_bus_width() will test the bus to determine the actual bus in sdhci_pci_o2_probe_slot()
744 host->mmc->caps |= MMC_CAP_8_BIT_DATA; in sdhci_pci_o2_probe_slot()
746 host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50; in sdhci_pci_o2_probe_slot()
748 sdhci_pci_o2_enable_msi(chip, host); in sdhci_pci_o2_probe_slot()
750 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; in sdhci_pci_o2_probe_slot()
751 switch (chip->pdev->device) { in sdhci_pci_o2_probe_slot()
757 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot()
759 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; in sdhci_pci_o2_probe_slot()
761 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { in sdhci_pci_o2_probe_slot()
762 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe_slot()
765 return -EIO; in sdhci_pci_o2_probe_slot()
768 mmc_hostname(host->mmc)); in sdhci_pci_o2_probe_slot()
769 host->flags &= ~SDHCI_SIGNALING_330; in sdhci_pci_o2_probe_slot()
770 host->flags |= SDHCI_SIGNALING_180; in sdhci_pci_o2_probe_slot()
771 host->mmc->caps2 |= MMC_CAP2_NO_SD; in sdhci_pci_o2_probe_slot()
772 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in sdhci_pci_o2_probe_slot()
773 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe_slot()
777 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; in sdhci_pci_o2_probe_slot()
780 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { in sdhci_pci_o2_probe_slot()
781 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; in sdhci_pci_o2_probe_slot()
782 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in sdhci_pci_o2_probe_slot()
783 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_pci_o2_probe_slot()
786 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) in sdhci_pci_o2_probe_slot()
789 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
791 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
797 host->mmc->caps2 |= MMC_CAP2_NO_SDIO | MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; in sdhci_pci_o2_probe_slot()
798 host->mmc->caps |= MMC_CAP_HW_RESET; in sdhci_pci_o2_probe_slot()
799 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_pci_o2_probe_slot()
800 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; in sdhci_pci_o2_probe_slot()
801 host->mmc_host_ops.init_sd_express = sdhci_pci_o2_init_sd_express; in sdhci_pci_o2_probe_slot()
810 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) in sdhci_pci_o2_probe() argument
817 switch (chip->pdev->device) { in sdhci_pci_o2_probe()
822 /* This extra setup is required due to broken ADMA. */ in sdhci_pci_o2_probe()
823 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
828 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
830 /* Set Multi 3 to VCC3V# */ in sdhci_pci_o2_probe()
831 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); in sdhci_pci_o2_probe()
834 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
839 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); in sdhci_pci_o2_probe()
841 /* Choose capabilities, enable SDMA. We have to write 0x01 in sdhci_pci_o2_probe()
842 * to the capabilities register first to unlock it. in sdhci_pci_o2_probe()
844 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); in sdhci_pci_o2_probe()
848 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); in sdhci_pci_o2_probe()
849 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); in sdhci_pci_o2_probe()
852 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); in sdhci_pci_o2_probe()
853 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); in sdhci_pci_o2_probe()
856 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
861 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); in sdhci_pci_o2_probe()
864 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
869 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
875 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
881 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
883 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ in sdhci_pci_o2_probe()
884 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { in sdhci_pci_o2_probe()
885 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
896 o2_pci_set_baseclk(chip, scratch_32); in sdhci_pci_o2_probe()
897 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
905 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
909 /* Set Tuning Window to 4 */ in sdhci_pci_o2_probe()
910 pci_write_config_byte(chip->pdev, in sdhci_pci_o2_probe()
918 o2_pci_led_enable(chip); in sdhci_pci_o2_probe()
921 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
928 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
931 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
936 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); in sdhci_pci_o2_probe()
938 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
945 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
949 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
954 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
957 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) in sdhci_pci_o2_probe()
958 sdhci_pci_o2_fujin2_pci_init(chip); in sdhci_pci_o2_probe()
961 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
966 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
971 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
977 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
979 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
988 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
994 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
997 ret = pci_read_config_dword(chip->pdev, in sdhci_pci_o2_probe()
1003 pci_write_config_dword(chip->pdev, in sdhci_pci_o2_probe()
1007 /* Set Tuning Windows to 5 */ in sdhci_pci_o2_probe()
1008 pci_write_config_byte(chip->pdev, in sdhci_pci_o2_probe()
1011 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32); in sdhci_pci_o2_probe()
1014 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32); in sdhci_pci_o2_probe()
1015 pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1); in sdhci_pci_o2_probe()
1017 ret = pci_read_config_byte(chip->pdev, in sdhci_pci_o2_probe()
1022 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
1029 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); in sdhci_pci_o2_probe()
1033 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
1036 pci_read_config_word(chip->pdev, O2_SD_PARA_SET_REG1, &scratch16); in sdhci_pci_o2_probe()
1039 pci_write_config_word(chip->pdev, O2_SD_PARA_SET_REG1, scratch16); in sdhci_pci_o2_probe()
1042 pci_read_config_word(chip->pdev, O2_SD_VDDX_CTRL_REG, &scratch16); in sdhci_pci_o2_probe()
1045 pci_write_config_word(chip->pdev, O2_SD_VDDX_CTRL_REG, scratch16); in sdhci_pci_o2_probe()
1047 /* Set host drive strength*/ in sdhci_pci_o2_probe()
1049 pci_write_config_word(chip->pdev, O2_SD_PLL_SETTING, scratch16); in sdhci_pci_o2_probe()
1052 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); in sdhci_pci_o2_probe()
1055 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); in sdhci_pci_o2_probe()
1058 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); in sdhci_pci_o2_probe()
1062 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); in sdhci_pci_o2_probe()
1073 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) in sdhci_pci_o2_resume() argument
1075 sdhci_pci_o2_probe(chip); in sdhci_pci_o2_resume()
1076 return sdhci_pci_resume_host(chip); in sdhci_pci_o2_resume()