Lines Matching +full:ssc +full:- +full:on
1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
21 #include "sdhci-uhs2.h"
468 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
481 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
483 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
484 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
488 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
491 return -EAGAIN; in __sdhci_execute_tuning_9750()
496 host->mmc->retune_period = 0; in gl9750_execute_tuning()
497 if (host->tuning_mode == SDHCI_TUNING_MODE_1) in gl9750_execute_tuning()
498 host->mmc->retune_period = host->tuning_count; in gl9750_execute_tuning()
501 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); in gl9750_execute_tuning()
553 u32 ssc; in gl9750_set_ssc() local
557 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
560 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; in gl9750_set_ssc()
563 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); in gl9750_set_ssc()
564 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
573 /* set pll to 205MHz and ssc */ in gl9750_set_ssc_pll_205mhz()
582 /* set pll to 100MHz and ssc */ in gl9750_set_ssc_pll_100mhz()
591 /* set pll to 50MHz and ssc */ in gl9750_set_ssc_pll_50mhz()
598 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9750_set_clock()
601 host->mmc->actual_clock = 0; in sdhci_gl9750_set_clock()
609 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9750_set_clock()
610 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9750_set_clock()
611 host->mmc->actual_clock = 205000000; in sdhci_gl9750_set_clock()
628 pdev = slot->chip->pdev; in gl9750_hw_setting()
653 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, in gli_pcie_enable_msi()
657 mmc_hostname(slot->host->mmc), ret); in gli_pcie_enable_msi()
661 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); in gli_pcie_enable_msi()
744 u32 ssc; in gl9755_set_ssc() local
748 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); in gl9755_set_ssc()
751 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; in gl9755_set_ssc()
754 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); in gl9755_set_ssc()
755 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); in gl9755_set_ssc()
764 /* set pll to 205MHz and ssc */ in gl9755_set_ssc_pll_205mhz()
773 /* set pll to 100MHz and ssc */ in gl9755_set_ssc_pll_100mhz()
782 /* set pll to 50MHz and ssc */ in gl9755_set_ssc_pll_50mhz()
790 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9755_set_clock()
794 pdev = slot->chip->pdev; in sdhci_gl9755_set_clock()
795 host->mmc->actual_clock = 0; in sdhci_gl9755_set_clock()
803 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9755_set_clock()
804 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9755_set_clock()
805 host->mmc->actual_clock = 205000000; in sdhci_gl9755_set_clock()
818 struct pci_dev *pdev = slot->chip->pdev; in gl9755_hw_setting()
828 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) in gl9755_hw_setting()
830 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) in gl9755_hw_setting()
861 struct pci_dev *pdev = slot->chip->pdev; in gl9755_vendor_init()
918 /* Need more time on UHS2 detect flow */ in sdhci_gli_pre_detect_init()
951 WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); in gl9755_set_power()
955 if (host->pwr == pwr) in gl9755_set_power()
958 host->pwr = pwr; in gl9755_set_power()
985 pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); in sdhci_wait_clock_stable()
1014 pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); in sdhci_gli_wait_software_reset_done()
1018 return -ETIMEDOUT; in sdhci_gli_wait_software_reset_done()
1026 /* do this on UHS2 mode */ in sdhci_gli_uhs2_reset_sd_tran()
1027 if (host->mmc->uhs2_sd_tran) { in sdhci_gli_uhs2_reset_sd_tran()
1029 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_gli_uhs2_reset_sd_tran()
1030 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_gli_uhs2_reset_sd_tran()
1045 /* reset sd-tran on UHS2 mode if need to reset cmd/data */ in sdhci_gl9755_reset()
1050 host->clock = 0; in sdhci_gl9755_reset()
1107 u32 ssc; in gl9767_set_ssc() local
1112 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); in gl9767_set_ssc()
1115 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; in gl9767_set_ssc()
1118 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); in gl9767_set_ssc()
1119 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); in gl9767_set_ssc()
1150 /* set pll to 205MHz and ssc */ in gl9767_set_ssc_pll_205mhz()
1187 struct pci_dev *pdev = slot->chip->pdev; in sdhci_gl9767_uhs2_phy_reset()
1195 /* De-assert reset, clean RESETN and set RESETN_VALUE */ in sdhci_gl9767_uhs2_phy_reset()
1217 mmc_hostname(host->mmc), vdd); in __gl9767_uhs2_set_power()
1221 if (host->pwr == pwr) in __gl9767_uhs2_set_power()
1224 host->pwr = pwr; in __gl9767_uhs2_set_power()
1246 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9767_set_clock()
1250 pdev = slot->chip->pdev; in sdhci_gl9767_set_clock()
1251 host->mmc->actual_clock = 0; in sdhci_gl9767_set_clock()
1262 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9767_set_clock()
1263 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9767_set_clock()
1264 host->mmc->actual_clock = 205000000; in sdhci_gl9767_set_clock()
1270 if (mmc_card_uhs2(host->mmc)) in sdhci_gl9767_set_clock()
1271 /* De-assert reset */ in sdhci_gl9767_set_clock()
1319 struct pci_dev *pdev = slot->chip->pdev; in gl9767_hw_setting()
1354 struct pci_dev *pdev = slot->chip->pdev; in sdhci_gl9767_reset()
1370 pr_warn("%s: %s: Reset SDHC AHB and TL-AMBA failure.\n", in sdhci_gl9767_reset()
1371 __func__, mmc_hostname(host->mmc)); in sdhci_gl9767_reset()
1378 if (mmc_card_uhs2(host->mmc)) { in sdhci_gl9767_reset()
1401 pdev = slot->chip->pdev; in gl9767_init_sd_express()
1403 if (mmc->ops->get_ro(mmc)) { in gl9767_init_sd_express()
1404 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1464 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1486 struct pci_dev *pdev = slot->chip->pdev; in gl9767_vendor_init()
1531 struct pci_dev *pdev = slot->chip->pdev; in sdhci_gl9767_set_power()
1534 if (mmc_card_uhs2(host->mmc)) { in sdhci_gl9767_set_power()
1565 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9750()
1569 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9750()
1577 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9755()
1581 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9755()
1590 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9767()
1595 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9767()
1596 host->mmc->caps2 |= MMC_CAP2_SD_EXP; in gli_probe_slot_gl9767()
1597 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; in gli_probe_slot_gl9767()
1656 value = readl(host->ioaddr + reg); in sdhci_gl9750_readl()
1670 if (ios->enhanced_strobe) in gl9763e_hs400_enhanced_strobe()
1681 struct pci_dev *pdev = slot->chip->pdev; in gl9763e_set_low_power_negotiation()
1730 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_pre_enable()
1754 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_gl9763e_cqhci_irq()
1762 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_post_disable()
1781 struct device *dev = &slot->chip->pdev->dev; in gl9763e_add_host()
1782 struct sdhci_host *host = slot->host; in gl9763e_add_host()
1793 ret = -ENOMEM; in gl9763e_add_host()
1797 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; in gl9763e_add_host()
1798 cq_host->ops = &sdhci_gl9763e_cqhci_ops; in gl9763e_add_host()
1800 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in gl9763e_add_host()
1802 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in gl9763e_add_host()
1804 ret = cqhci_init(cq_host, host->mmc, dma64); in gl9763e_add_host()
1824 struct pci_dev *pdev = slot->chip->pdev; in gl9763e_hw_setting()
1863 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_suspend()
1864 struct sdhci_host *host = slot->host; in gl9763e_runtime_suspend()
1879 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_resume()
1880 struct sdhci_host *host = slot->host; in gl9763e_runtime_resume()
1883 if (host->mmc->ios.power_mode != MMC_POWER_ON) in gl9763e_runtime_resume()
1896 mmc_hostname(host->mmc)); in gl9763e_runtime_resume()
1913 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_pci_gli_resume()
1915 pci_free_irq_vectors(slot->chip->pdev); in sdhci_pci_gli_resume()
1923 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_resume()
1930 ret = cqhci_resume(slot->host->mmc); in gl9763e_resume()
1945 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_suspend()
1949 * Certain SoCs can suspend only with the bus in low- in gl9763e_suspend()
1951 * Re-enable LPM negotiation to allow entering L1 state in gl9763e_suspend()
1956 ret = cqhci_suspend(slot->host->mmc); in gl9763e_suspend()
1960 ret = sdhci_suspend_host(slot->host); in gl9763e_suspend()
1967 cqhci_resume(slot->host->mmc); in gl9763e_suspend()
1976 struct pci_dev *pdev = slot->chip->pdev; in gli_probe_slot_gl9763e()
1977 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9763e()
1980 host->mmc->caps |= MMC_CAP_8_BIT_DATA | in gli_probe_slot_gl9763e()
1983 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | in gli_probe_slot_gl9763e()
1992 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in gli_probe_slot_gl9763e()
1995 host->mmc_host_ops.hs400_enhanced_strobe = in gli_probe_slot_gl9763e()
2007 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readw()
2016 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readb()