306 static inline void gl9750_wt_on(struct sdhci_host *host)  in gl9750_wt_on()  argument
311 	wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);  in gl9750_wt_on()
320 	sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);  in gl9750_wt_on()
323 static inline void gl9750_wt_off(struct sdhci_host *host)  in gl9750_wt_off()  argument
328 	wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);  in gl9750_wt_off()
337 	sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);  in gl9750_wt_off()
340 static void gli_set_9750(struct sdhci_host *host)  in gli_set_9750()  argument
350 	gl9750_wt_on(host);  in gli_set_9750()
352 	driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);  in gli_set_9750()
353 	pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);  in gli_set_9750()
354 	sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);  in gli_set_9750()
355 	misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);  in gli_set_9750()
356 	parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);  in gli_set_9750()
357 	control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);  in gli_set_9750()
367 	sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);  in gli_set_9750()
372 	sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);  in gli_set_9750()
403 	sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);  in gli_set_9750()
404 	sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);  in gli_set_9750()
407 	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);  in gli_set_9750()
409 	sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);  in gli_set_9750()
415 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);  in gli_set_9750()
418 	sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);  in gli_set_9750()
424 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);  in gli_set_9750()
427 	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);  in gli_set_9750()
429 	sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);  in gli_set_9750()
431 	gl9750_wt_off(host);  in gli_set_9750()
434 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)  in gli_set_9750_rx_inv()  argument
438 	gl9750_wt_on(host);  in gli_set_9750_rx_inv()
440 	misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);  in gli_set_9750_rx_inv()
449 	sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);  in gli_set_9750_rx_inv()
451 	gl9750_wt_off(host);  in gli_set_9750_rx_inv()
454 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)  in __sdhci_execute_tuning_9750()  argument
460 		gli_set_9750_rx_inv(host, !!rx_inv);  in __sdhci_execute_tuning_9750()
461 		sdhci_start_tuning(host);  in __sdhci_execute_tuning_9750()
466 			sdhci_send_tuning(host, opcode);  in __sdhci_execute_tuning_9750()
468 			if (!host->tuning_done) {  in __sdhci_execute_tuning_9750()
469 				sdhci_abort_tuning(host, opcode);  in __sdhci_execute_tuning_9750()
473 			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);  in __sdhci_execute_tuning_9750()
481 	if (!host->tuning_done) {  in __sdhci_execute_tuning_9750()
483 			mmc_hostname(host->mmc));  in __sdhci_execute_tuning_9750()
488 		mmc_hostname(host->mmc));  in __sdhci_execute_tuning_9750()
489 	sdhci_reset_tuning(host);  in __sdhci_execute_tuning_9750()
494 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)  in gl9750_execute_tuning()  argument
496 	host->mmc->retune_period = 0;  in gl9750_execute_tuning()
497 	if (host->tuning_mode == SDHCI_TUNING_MODE_1)  in gl9750_execute_tuning()
498 		host->mmc->retune_period = host->tuning_count;  in gl9750_execute_tuning()
500 	gli_set_9750(host);  in gl9750_execute_tuning()
501 	host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);  in gl9750_execute_tuning()
502 	sdhci_end_tuning(host);  in gl9750_execute_tuning()
507 static void gl9750_disable_ssc_pll(struct sdhci_host *host)  in gl9750_disable_ssc_pll()  argument
511 	gl9750_wt_on(host);  in gl9750_disable_ssc_pll()
512 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);  in gl9750_disable_ssc_pll()
514 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);  in gl9750_disable_ssc_pll()
515 	gl9750_wt_off(host);  in gl9750_disable_ssc_pll()
518 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)  in gl9750_set_pll()  argument
522 	gl9750_wt_on(host);  in gl9750_set_pll()
523 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);  in gl9750_set_pll()
530 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);  in gl9750_set_pll()
531 	gl9750_wt_off(host);  in gl9750_set_pll()
537 static bool gl9750_ssc_enable(struct sdhci_host *host)  in gl9750_ssc_enable()  argument
542 	gl9750_wt_on(host);  in gl9750_ssc_enable()
543 	misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);  in gl9750_ssc_enable()
545 	gl9750_wt_off(host);  in gl9750_ssc_enable()
550 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)  in gl9750_set_ssc()  argument
555 	gl9750_wt_on(host);  in gl9750_set_ssc()
556 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);  in gl9750_set_ssc()
557 	ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
564 	sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
565 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);  in gl9750_set_ssc()
566 	gl9750_wt_off(host);  in gl9750_set_ssc()
569 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)  in gl9750_set_ssc_pll_205mhz()  argument
571 	bool enable = gl9750_ssc_enable(host);  in gl9750_set_ssc_pll_205mhz()
574 	gl9750_set_ssc(host, enable, 0xF, 0x5A1D);  in gl9750_set_ssc_pll_205mhz()
575 	gl9750_set_pll(host, 0x1, 0x246, 0x0);  in gl9750_set_ssc_pll_205mhz()
578 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)  in gl9750_set_ssc_pll_100mhz()  argument
580 	bool enable = gl9750_ssc_enable(host);  in gl9750_set_ssc_pll_100mhz()
583 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);  in gl9750_set_ssc_pll_100mhz()
584 	gl9750_set_pll(host, 0x1, 0x244, 0x1);  in gl9750_set_ssc_pll_100mhz()
587 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)  in gl9750_set_ssc_pll_50mhz()  argument
589 	bool enable = gl9750_ssc_enable(host);  in gl9750_set_ssc_pll_50mhz()
592 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);  in gl9750_set_ssc_pll_50mhz()
593 	gl9750_set_pll(host, 0x1, 0x244, 0x3);  in gl9750_set_ssc_pll_50mhz()
596 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)  in sdhci_gl9750_set_clock()  argument
598 	struct mmc_ios *ios = &host->mmc->ios;  in sdhci_gl9750_set_clock()
601 	host->mmc->actual_clock = 0;  in sdhci_gl9750_set_clock()
603 	gl9750_disable_ssc_pll(host);  in sdhci_gl9750_set_clock()
604 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in sdhci_gl9750_set_clock()
609 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);  in sdhci_gl9750_set_clock()
611 		host->mmc->actual_clock = 205000000;  in sdhci_gl9750_set_clock()
612 		gl9750_set_ssc_pll_205mhz(host);  in sdhci_gl9750_set_clock()
614 		gl9750_set_ssc_pll_100mhz(host);  in sdhci_gl9750_set_clock()
616 		gl9750_set_ssc_pll_50mhz(host);  in sdhci_gl9750_set_clock()
619 	sdhci_enable_clk(host, clk);  in sdhci_gl9750_set_clock()
622 static void gl9750_hw_setting(struct sdhci_host *host)  in gl9750_hw_setting()  argument
624 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in gl9750_hw_setting()
630 	gl9750_wt_on(host);  in gl9750_hw_setting()
632 	value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);  in gl9750_hw_setting()
637 	sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);  in gl9750_hw_setting()
646 	gl9750_wt_off(host);  in gl9750_hw_setting()
657 		       mmc_hostname(slot->host->mmc), ret);  in gli_pcie_enable_msi()
661 	slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);  in gli_pcie_enable_msi()
787 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)  in sdhci_gl9755_set_clock()  argument
789 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in sdhci_gl9755_set_clock()
790 	struct mmc_ios *ios = &host->mmc->ios;  in sdhci_gl9755_set_clock()
795 	host->mmc->actual_clock = 0;  in sdhci_gl9755_set_clock()
798 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in sdhci_gl9755_set_clock()
803 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);  in sdhci_gl9755_set_clock()
805 		host->mmc->actual_clock = 205000000;  in sdhci_gl9755_set_clock()
813 	sdhci_enable_clk(host, clk);  in sdhci_gl9755_set_clock()
858 static void gl9755_vendor_init(struct sdhci_host *host)  in gl9755_vendor_init()  argument
860 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in gl9755_vendor_init()
916 static void sdhci_gli_pre_detect_init(struct sdhci_host *host)  in sdhci_gli_pre_detect_init()  argument
919 	sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL);  in sdhci_gli_pre_detect_init()
922 static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bool enable)  in sdhci_gli_overcurrent_event_enable()  argument
926 	mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);  in sdhci_gli_overcurrent_event_enable()
932 	sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE);  in sdhci_gli_overcurrent_event_enable()
934 	mask = sdhci_readl(host, SDHCI_INT_ENABLE);  in sdhci_gli_overcurrent_event_enable()
940 	sdhci_writel(host, mask, SDHCI_INT_ENABLE);  in sdhci_gli_overcurrent_event_enable()
943 static void gl9755_set_power(struct sdhci_host *host, unsigned char mode,  in gl9755_set_power()  argument
951 			WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd);  in gl9755_set_power()
955 	if (host->pwr == pwr)  in gl9755_set_power()
958 	host->pwr = pwr;  in gl9755_set_power()
961 		sdhci_gli_overcurrent_event_enable(host, false);  in gl9755_set_power()
962 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in gl9755_set_power()
964 		sdhci_gli_overcurrent_event_enable(host, false);  in gl9755_set_power()
965 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in gl9755_set_power()
969 		sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);  in gl9755_set_power()
972 		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);  in gl9755_set_power()
975 		sdhci_gli_overcurrent_event_enable(host, true);  in gl9755_set_power()
979 static bool sdhci_wait_clock_stable(struct sdhci_host *host)  in sdhci_wait_clock_stable()  argument
984 				     10, 20000, false, host, SDHCI_CLOCK_CONTROL)) {  in sdhci_wait_clock_stable()
985 		pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc));  in sdhci_wait_clock_stable()
986 		sdhci_dumpregs(host);  in sdhci_wait_clock_stable()
992 static void sdhci_gli_enable_internal_clock(struct sdhci_host *host)  in sdhci_gli_enable_internal_clock()  argument
996 	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);  in sdhci_gli_enable_internal_clock()
998 	sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL);  in sdhci_gli_enable_internal_clock()
1002 		sdhci_wait_clock_stable(host);  in sdhci_gli_enable_internal_clock()
1003 		sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2);  in sdhci_gli_enable_internal_clock()
1007 static int sdhci_gli_wait_software_reset_done(struct sdhci_host *host, u8 mask)  in sdhci_gli_wait_software_reset_done()  argument
1013 				     10, 100000, false, host, SDHCI_SOFTWARE_RESET)) {  in sdhci_gli_wait_software_reset_done()
1014 		pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask);  in sdhci_gli_wait_software_reset_done()
1015 		sdhci_dumpregs(host);  in sdhci_gli_wait_software_reset_done()
1017 		sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET);  in sdhci_gli_wait_software_reset_done()
1024 static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host)  in sdhci_gli_uhs2_reset_sd_tran()  argument
1027 	if (host->mmc->uhs2_sd_tran) {  in sdhci_gli_uhs2_reset_sd_tran()
1028 		sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD);  in sdhci_gli_uhs2_reset_sd_tran()
1029 		sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);  in sdhci_gli_uhs2_reset_sd_tran()
1030 		sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);  in sdhci_gli_uhs2_reset_sd_tran()
1031 		sdhci_uhs2_clear_set_irqs(host,  in sdhci_gli_uhs2_reset_sd_tran()
1037 static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask)  in sdhci_gl9755_reset()  argument
1041 		sdhci_gli_enable_internal_clock(host);  in sdhci_gl9755_reset()
1043 	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);  in sdhci_gl9755_reset()
1047 		sdhci_gli_uhs2_reset_sd_tran(host);  in sdhci_gl9755_reset()
1050 		host->clock = 0;  in sdhci_gl9755_reset()
1052 	sdhci_gli_wait_software_reset_done(host, mask);  in sdhci_gl9755_reset()
1184 static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert)  in sdhci_gl9767_uhs2_phy_reset()  argument
1186 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in sdhci_gl9767_uhs2_phy_reset()
1209 static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd)  in __gl9767_uhs2_set_power()  argument
1217 			     mmc_hostname(host->mmc), vdd);  in __gl9767_uhs2_set_power()
1221 	if (host->pwr == pwr)  in __gl9767_uhs2_set_power()
1224 	host->pwr = pwr;  in __gl9767_uhs2_set_power()
1227 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in __gl9767_uhs2_set_power()
1229 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in __gl9767_uhs2_set_power()
1232 		sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);  in __gl9767_uhs2_set_power()
1236 		sdhci_gl9767_uhs2_phy_reset(host, true);  in __gl9767_uhs2_set_power()
1238 		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);  in __gl9767_uhs2_set_power()
1243 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)  in sdhci_gl9767_set_clock()  argument
1245 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in sdhci_gl9767_set_clock()
1246 	struct mmc_ios *ios = &host->mmc->ios;  in sdhci_gl9767_set_clock()
1251 	host->mmc->actual_clock = 0;  in sdhci_gl9767_set_clock()
1255 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in sdhci_gl9767_set_clock()
1262 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);  in sdhci_gl9767_set_clock()
1264 		host->mmc->actual_clock = 205000000;  in sdhci_gl9767_set_clock()
1268 	sdhci_enable_clk(host, clk);  in sdhci_gl9767_set_clock()
1270 	if (mmc_card_uhs2(host->mmc))  in sdhci_gl9767_set_clock()
1272 		sdhci_gl9767_uhs2_phy_reset(host, false);  in sdhci_gl9767_set_clock()
1277 static void sdhci_gl9767_set_card_detect_debounce_time(struct sdhci_host *host)  in sdhci_gl9767_set_card_detect_debounce_time()  argument
1281 	value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);  in sdhci_gl9767_set_card_detect_debounce_time()
1284 	if (sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)  in sdhci_gl9767_set_card_detect_debounce_time()
1294 	sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);  in sdhci_gl9767_set_card_detect_debounce_time()
1297 static void sdhci_gl9767_card_event(struct sdhci_host *host)  in sdhci_gl9767_card_event()  argument
1299 	sdhci_gl9767_set_card_detect_debounce_time(host);  in sdhci_gl9767_card_event()
1302 static void gli_set_9767(struct sdhci_host *host)  in gli_set_9767()  argument
1306 	value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);  in gli_set_9767()
1308 	sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);  in gli_set_9767()
1310 	value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);  in gli_set_9767()
1312 	sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);  in gli_set_9767()
1314 	sdhci_gl9767_set_card_detect_debounce_time(host);  in gli_set_9767()
1351 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)  in sdhci_gl9767_reset()  argument
1353 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in sdhci_gl9767_reset()
1359 		sdhci_gli_enable_internal_clock(host);  in sdhci_gl9767_reset()
1371 				__func__, mmc_hostname(host->mmc));  in sdhci_gl9767_reset()
1378 	if (mmc_card_uhs2(host->mmc)) {  in sdhci_gl9767_reset()
1380 			sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);  in sdhci_gl9767_reset()
1381 			sdhci_gli_uhs2_reset_sd_tran(host);  in sdhci_gl9767_reset()
1382 			sdhci_gli_wait_software_reset_done(host, mask);  in sdhci_gl9767_reset()
1384 			sdhci_uhs2_reset(host, mask);  in sdhci_gl9767_reset()
1387 		sdhci_reset(host, mask);  in sdhci_gl9767_reset()
1390 	gli_set_9767(host);  in sdhci_gl9767_reset()
1395 	struct sdhci_host *host = mmc_priv(mmc);  in gl9767_init_sd_express()  local
1396 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in gl9767_init_sd_express()
1436 	value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);  in gl9767_init_sd_express()
1438 	sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);  in gl9767_init_sd_express()
1440 	value = sdhci_readb(host, SDHCI_POWER_CONTROL);  in gl9767_init_sd_express()
1442 	sdhci_writeb(host, value, SDHCI_POWER_CONTROL);  in gl9767_init_sd_express()
1466 		value = sdhci_readb(host, SDHCI_POWER_CONTROL);  in gl9767_init_sd_express()
1468 		sdhci_writeb(host, value, SDHCI_POWER_CONTROL);  in gl9767_init_sd_express()
1470 		value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);  in gl9767_init_sd_express()
1472 		sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);  in gl9767_init_sd_express()
1483 static void gl9767_vendor_init(struct sdhci_host *host)  in gl9767_vendor_init()  argument
1485 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in gl9767_vendor_init()
1528 static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode,	unsigned short vdd)  in sdhci_gl9767_set_power()  argument
1530 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in sdhci_gl9767_set_power()
1534 	if (mmc_card_uhs2(host->mmc)) {  in sdhci_gl9767_set_power()
1544 		sdhci_gli_overcurrent_event_enable(host, false);  in sdhci_gl9767_set_power()
1545 		__gl9767_uhs2_set_power(host, mode, vdd);  in sdhci_gl9767_set_power()
1546 		sdhci_gli_overcurrent_event_enable(host, true);  in sdhci_gl9767_set_power()
1557 		sdhci_gli_overcurrent_event_enable(host, false);  in sdhci_gl9767_set_power()
1558 		sdhci_set_power(host, mode, vdd);  in sdhci_gl9767_set_power()
1559 		sdhci_gli_overcurrent_event_enable(host, true);  in sdhci_gl9767_set_power()
1565 	struct sdhci_host *host = slot->host;  in gli_probe_slot_gl9750()  local
1567 	gl9750_hw_setting(host);  in gli_probe_slot_gl9750()
1569 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;  in gli_probe_slot_gl9750()
1570 	sdhci_enable_v4_mode(host);  in gli_probe_slot_gl9750()
1577 	struct sdhci_host *host = slot->host;  in gli_probe_slot_gl9755()  local
1581 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;  in gli_probe_slot_gl9755()
1582 	sdhci_enable_v4_mode(host);  in gli_probe_slot_gl9755()
1583 	gl9755_vendor_init(host);  in gli_probe_slot_gl9755()
1590 	struct sdhci_host *host = slot->host;  in gli_probe_slot_gl9767()  local
1592 	gli_set_9767(host);  in gli_probe_slot_gl9767()
1595 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;  in gli_probe_slot_gl9767()
1596 	host->mmc->caps2 |= MMC_CAP2_SD_EXP;  in gli_probe_slot_gl9767()
1597 	host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;  in gli_probe_slot_gl9767()
1598 	sdhci_enable_v4_mode(host);  in gli_probe_slot_gl9767()
1599 	gl9767_vendor_init(host);  in gli_probe_slot_gl9767()
1604 static void sdhci_gli_voltage_switch(struct sdhci_host *host)  in sdhci_gli_voltage_switch()  argument
1608 	 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as  in sdhci_gli_voltage_switch()
1610 	 * (6) Set 1.8V Signal Enable in the Host Control 2 register.  in sdhci_gli_voltage_switch()
1613 	 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to  in sdhci_gli_voltage_switch()
1616 	 * Wait 5ms after set 1.8V signal enable in Host Control 2 register  in sdhci_gli_voltage_switch()
1627 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)  in sdhci_gl9767_voltage_switch()  argument
1631 	 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as  in sdhci_gl9767_voltage_switch()
1633 	 * (6) Set 1.8V Signal Enable in the Host Control 2 register.  in sdhci_gl9767_voltage_switch()
1636 	 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to  in sdhci_gl9767_voltage_switch()
1639 	 * Wait 5ms after set 1.8V signal enable in Host Control 2 register  in sdhci_gl9767_voltage_switch()
1646 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)  in sdhci_gl9750_reset()  argument
1648 	sdhci_reset(host, mask);  in sdhci_gl9750_reset()
1649 	gli_set_9750(host);  in sdhci_gl9750_reset()
1652 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)  in sdhci_gl9750_readl()  argument
1656 	value = readl(host->ioaddr + reg);  in sdhci_gl9750_readl()
1666 	struct sdhci_host *host = mmc_priv(mmc);  in gl9763e_hs400_enhanced_strobe()  local
1669 	val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);  in gl9763e_hs400_enhanced_strobe()
1675 	sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);  in gl9763e_hs400_enhanced_strobe()
1704 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,  in sdhci_set_gl9763e_signaling()  argument
1709 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);  in sdhci_set_gl9763e_signaling()
1720 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);  in sdhci_set_gl9763e_signaling()
1740 	struct sdhci_host *host = mmc_priv(mmc);  in sdhci_gl9763e_cqe_enable()  local
1742 	sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);  in sdhci_gl9763e_cqe_enable()
1746 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)  in sdhci_gl9763e_cqhci_irq()  argument
1751 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))  in sdhci_gl9763e_cqhci_irq()
1754 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);  in sdhci_gl9763e_cqhci_irq()
1761 	struct sdhci_host *host = mmc_priv(mmc);  in sdhci_gl9763e_cqe_post_disable()  local
1768 	sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);  in sdhci_gl9763e_cqe_post_disable()
1782 	struct sdhci_host *host = slot->host;  in gl9763e_add_host()  local
1787 	ret = sdhci_setup_host(host);  in gl9763e_add_host()
1797 	cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;  in gl9763e_add_host()
1800 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;  in gl9763e_add_host()
1804 	ret = cqhci_init(cq_host, host->mmc, dma64);  in gl9763e_add_host()
1808 	ret = __sdhci_add_host(host);  in gl9763e_add_host()
1818 	sdhci_cleanup_host(host);  in gl9763e_add_host()
1864 	struct sdhci_host *host = slot->host;  in gl9763e_runtime_suspend()  local
1870 	clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);  in gl9763e_runtime_suspend()
1872 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);  in gl9763e_runtime_suspend()
1880 	struct sdhci_host *host = slot->host;  in gl9763e_runtime_resume()  local
1883 	if (host->mmc->ios.power_mode != MMC_POWER_ON)  in gl9763e_runtime_resume()
1886 	clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);  in gl9763e_runtime_resume()
1890 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);  in gl9763e_runtime_resume()
1894 			      1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {  in gl9763e_runtime_resume()
1896 		       mmc_hostname(host->mmc));  in gl9763e_runtime_resume()
1897 		sdhci_dumpregs(host);  in gl9763e_runtime_resume()
1901 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);  in gl9763e_runtime_resume()
1930 	ret = cqhci_resume(slot->host->mmc);  in gl9763e_resume()
1956 	ret = cqhci_suspend(slot->host->mmc);  in gl9763e_suspend()
1960 	ret = sdhci_suspend_host(slot->host);  in gl9763e_suspend()
1967 	cqhci_resume(slot->host->mmc);  in gl9763e_suspend()
1977 	struct sdhci_host *host = slot->host;  in gli_probe_slot_gl9763e()  local
1980 	host->mmc->caps |= MMC_CAP_8_BIT_DATA |  in gli_probe_slot_gl9763e()
1983 	host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |  in gli_probe_slot_gl9763e()
1992 			host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;  in gli_probe_slot_gl9763e()
1995 	host->mmc_host_ops.hs400_enhanced_strobe =  in gli_probe_slot_gl9763e()
1998 	sdhci_enable_v4_mode(host);  in gli_probe_slot_gl9763e()
2005 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)  in sdhci_gli_readw()  argument
2007 	u32 val = readl(host->ioaddr + (reg & ~3));  in sdhci_gli_readw()
2014 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)  in sdhci_gli_readb()  argument
2016 	u32 val = readl(host->ioaddr + (reg & ~3));  in sdhci_gli_readb()