24 #define SDHCI_GLI_9750_WT         0x800
25 #define   SDHCI_GLI_9750_WT_EN      BIT(0)
26 #define   GLI_9750_WT_EN_ON	    0x1
27 #define   GLI_9750_WT_EN_OFF	    0x0
29 #define SDHCI_GLI_9750_CFG2          0x848
31 #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
33 #define SDHCI_GLI_9750_DRIVING      0x860
34 #define   SDHCI_GLI_9750_DRIVING_1    GENMASK(11, 0)
36 #define   GLI_9750_DRIVING_1_VALUE    0xFFF
37 #define   GLI_9750_DRIVING_2_VALUE    0x3
42 #define SDHCI_GLI_9750_PLL	      0x864
43 #define   SDHCI_GLI_9750_PLL_LDIV       GENMASK(9, 0)
48 #define   GLI_9750_PLL_TX2_INV_VALUE    0x1
49 #define   GLI_9750_PLL_TX2_DLY_VALUE    0x0
53 #define SDHCI_GLI_9750_PLLSSC        0x86C
56 #define SDHCI_GLI_9750_SW_CTRL      0x874
58 #define   GLI_9750_SW_CTRL_4_VALUE    0x3
60 #define SDHCI_GLI_9750_MISC            0x878
64 #define   GLI_9750_MISC_TX1_INV_VALUE    0x0
65 #define   GLI_9750_MISC_RX_INV_ON        0x1
66 #define   GLI_9750_MISC_RX_INV_OFF       0x0
68 #define   GLI_9750_MISC_TX1_DLY_VALUE    0x5
71 #define SDHCI_GLI_9750_TUNING_CONTROL	          0x540
73 #define   GLI_9750_TUNING_CONTROL_EN_ON             0x1
74 #define   GLI_9750_TUNING_CONTROL_EN_OFF            0x0
77 #define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE    0x1
78 #define   GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE    0x2
80 #define SDHCI_GLI_9750_TUNING_PARAMETERS           0x544
81 #define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY    GENMASK(2, 0)
82 #define   GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE    0x1
84 #define SDHCI_GLI_9763E_CTRL_HS400  0x7
86 #define SDHCI_GLI_9763E_HS400_ES_REG      0x52C
89 #define PCIE_GLI_9763E_VHS	 0x884
91 #define   GLI_9763E_VHS_REV_R      0x0
92 #define   GLI_9763E_VHS_REV_M      0x1
93 #define   GLI_9763E_VHS_REV_W      0x2
94 #define PCIE_GLI_9763E_MB	 0x888
97 #define PCIE_GLI_9763E_SCR	 0x8E0
100 #define PCIE_GLI_9763E_CFG       0x8A0
103 #define PCIE_GLI_9763E_CFG2      0x8A4
105 #define   GLI_9763E_CFG2_L1DLY_MID 0x54
107 #define PCIE_GLI_9763E_MMC_CTRL  0x960
110 #define PCIE_GLI_9763E_CLKRXDLY  0x934
112 #define   GLI_9763E_HS400_RXDLY_5  0x5
114 #define SDHCI_GLI_9763E_CQE_BASE_ADDR	 0x200
119 #define PCI_GLI_9755_WT       0x800
120 #define   PCI_GLI_9755_WT_EN    BIT(0)
121 #define   GLI_9755_WT_EN_ON     0x1
122 #define   GLI_9755_WT_EN_OFF    0x0
124 #define PCI_GLI_9755_PECONF   0x44
130 #define PCI_GLI_9755_CFG2          0x48
132 #define   GLI_9755_CFG2_L1DLY_VALUE  0x1F
134 #define PCI_GLI_9755_PLL            0x64
135 #define   PCI_GLI_9755_PLL_LDIV       GENMASK(9, 0)
141 #define PCI_GLI_9755_PLLSSC        0x68
142 #define   PCI_GLI_9755_PLLSSC_PPM    GENMASK(15, 0)
144 #define   GLI_9755_PLLSSC_RTL_VALUE           0x1
146 #define   GLI_9755_PLLSSC_TRANS_PASS_VALUE    0x1
148 #define   GLI_9755_PLLSSC_RECV_VALUE          0x0
150 #define   GLI_9755_PLLSSC_TRAN_VALUE          0x3
152 #define PCI_GLI_9755_UHS2_PLL            0x6C
154 #define   GLI_9755_UHS2_PLL_SSC_VALUE      0x0
156 #define   GLI_9755_UHS2_PLL_DELAY_VALUE    0x1
158 #define   GLI_9755_UHS2_PLL_PDRST_VALUE    0x1
160 #define PCI_GLI_9755_SerDes  0x70
161 #define   PCI_GLI_9755_UHS2_SERDES_INTR       GENMASK(2, 0)
162 #define   GLI_9755_UHS2_SERDES_INTR_VALUE     0x3
164 #define   GLI_9755_UHS2_SERDES_ZC1_VALUE      0x0
166 #define   GLI_9755_UHS2_SERDES_ZC2_DEFAULT    0xB
167 #define   GLI_9755_UHS2_SERDES_ZC2_SANDISK    0x0
170 #define   GLI_9755_UHS2_SERDES_TRAN_VALUE     0xC
172 #define   GLI_9755_UHS2_SERDES_RECV_VALUE     0xF
174 #define PCI_GLI_9755_MISC	    0x78
177 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL				0x508
178 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK	  BIT(0)
180 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE	  0x05
181 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE	  0x3F
183 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS	  0x2
184 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS	  0x3
186 #define SDHCI_GLI_9767_GM_BURST_SIZE			0x510
189 #define PCIE_GLI_9767_VHS	0x884
191 #define   GLI_9767_VHS_REV_R	  0x0
192 #define   GLI_9767_VHS_REV_M	  0x1
193 #define   GLI_9767_VHS_REV_W	  0x2
195 #define PCIE_GLI_9767_COM_MAILBOX		0x888
198 #define PCIE_GLI_9767_CFG		0x8A0
201 #define PCIE_GLI_9767_COMBO_MUX_CTL			0x8C8
205 #define PCIE_GLI_9767_PWR_MACRO_CTL					0x8D0
206 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE			  GENMASK(3, 0)
208 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE	  0x7
210 #define   PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE		  0x3
212 #define PCIE_GLI_9767_SCR				0x8E0
222 #define PCIE_GLI_9767_RESET_REG				0x8E4
223 #define   PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET	  BIT(0)
225 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1				0x90C
227 #define   PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE	  0x3
229 #define PCIE_GLI_9767_SDHC_CAP			0x91C
232 #define PCIE_GLI_9767_SD_PLL_CTL			0x938
233 #define   PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV		  GENMASK(9, 0)
239 #define PCIE_GLI_9767_SD_PLL_CTL2		0x93C
242 #define PCIE_GLI_9767_SD_EXPRESS_CTL			0x940
243 #define   PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE		  BIT(0)
246 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL				0x944
250 #define   PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE	  0x64
252 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2					0x948
254 #define   PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE		  0x0
256 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2			0x950
257 #define   PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE	  BIT(0)
259 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2				0x954
260 #define   PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN	  BIT(0)
262 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2				0x958
263 #define   PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN	  BIT(0)
265 #define PCIE_GLI_9767_UHS2_CTL1				0x95C
267 #define   PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE	  0x1
269 #define   PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE	  0x1
271 #define   PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE	  0x3
273 #define   PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE	  0xf
275 #define   PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE	  0x0
277 #define   PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE	  0x0
279 #define   PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE		  0x1
281 #define PCIE_GLI_9767_UHS2_CTL2			0x964
282 #define   PCIE_GLI_9767_UHS2_CTL2_ZC		  GENMASK(3, 0)
283 #define   PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE	  0xb
285 #define   PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE	  0x1
459 	for (rx_inv = 0; rx_inv < 2; rx_inv++) {  in __sdhci_execute_tuning_9750()
463 		for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {  in __sdhci_execute_tuning_9750()
476 					return 0; /* Success! */  in __sdhci_execute_tuning_9750()
496 	host->mmc->retune_period = 0;  in gl9750_execute_tuning()
504 	return 0;  in gl9750_execute_tuning()
574 	gl9750_set_ssc(host, enable, 0xF, 0x5A1D);  in gl9750_set_ssc_pll_205mhz()
575 	gl9750_set_pll(host, 0x1, 0x246, 0x0);  in gl9750_set_ssc_pll_205mhz()
583 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);  in gl9750_set_ssc_pll_100mhz()
584 	gl9750_set_pll(host, 0x1, 0x244, 0x1);  in gl9750_set_ssc_pll_100mhz()
592 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);  in gl9750_set_ssc_pll_50mhz()
593 	gl9750_set_pll(host, 0x1, 0x244, 0x3);  in gl9750_set_ssc_pll_50mhz()
601 	host->mmc->actual_clock = 0;  in sdhci_gl9750_set_clock()
604 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in sdhci_gl9750_set_clock()
606 	if (clock == 0)  in sdhci_gl9750_set_clock()
655 	if (ret < 0) {  in gli_pcie_enable_msi()
661 	slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);  in gli_pcie_enable_msi()
765 	gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);  in gl9755_set_ssc_pll_205mhz()
766 	gl9755_set_pll(pdev, 0x1, 0x246, 0x0);  in gl9755_set_ssc_pll_205mhz()
774 	gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);  in gl9755_set_ssc_pll_100mhz()
775 	gl9755_set_pll(pdev, 0x1, 0x244, 0x1);  in gl9755_set_ssc_pll_100mhz()
783 	gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);  in gl9755_set_ssc_pll_50mhz()
784 	gl9755_set_pll(pdev, 0x1, 0x244, 0x3);  in gl9755_set_ssc_pll_50mhz()
795 	host->mmc->actual_clock = 0;  in sdhci_gl9755_set_clock()
798 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in sdhci_gl9755_set_clock()
800 	if (clock == 0)  in sdhci_gl9755_set_clock()
919 	sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL);  in sdhci_gli_pre_detect_init()
946 	u8 pwr = 0;  in gl9755_set_power()
960 	if (pwr == 0) {  in gl9755_set_power()
962 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in gl9755_set_power()
965 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in gl9755_set_power()
969 		sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);  in gl9755_set_power()
981 	u16 clk = 0;  in sdhci_wait_clock_stable()
1014 		pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask);  in sdhci_gli_wait_software_reset_done()
1017 		sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET);  in sdhci_gli_wait_software_reset_done()
1021 	return 0;  in sdhci_gli_wait_software_reset_done()
1050 		host->clock = 0;  in sdhci_gl9755_reset()
1151 	gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);  in gl9767_set_ssc_pll_205mhz()
1152 	gl9767_set_pll(pdev, 0x1, 0x246, 0x0);  in gl9767_set_ssc_pll_205mhz()
1211 	u8 pwr = 0;  in __gl9767_uhs2_set_power()
1226 	if (pwr == 0) {  in __gl9767_uhs2_set_power()
1227 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in __gl9767_uhs2_set_power()
1229 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);  in __gl9767_uhs2_set_power()
1232 		sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);  in __gl9767_uhs2_set_power()
1251 	host->mmc->actual_clock = 0;  in sdhci_gl9767_set_clock()
1255 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in sdhci_gl9767_set_clock()
1257 	if (clock == 0) {  in sdhci_gl9767_set_clock()
1405 		return 0;  in gl9767_init_sd_express()
1448 	for (i = 0; i < 2; i++) {  in gl9767_init_sd_express()
1480 	return 0;  in gl9767_init_sd_express()
1572 	return 0;  in gli_probe_slot_gl9750()
1585 	return 0;  in gli_probe_slot_gl9755()
1601 	return 0;  in gli_probe_slot_gl9767()
1657 	if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))  in sdhci_gl9750_readl()
1658 		value |= 0xc8;  in sdhci_gl9750_readl()
1748 	int cmd_error = 0;  in sdhci_gl9763e_cqhci_irq()
1749 	int data_error = 0;  in sdhci_gl9763e_cqhci_irq()
1756 	return 0;  in sdhci_gl9763e_cqhci_irq()
1768 	sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);  in sdhci_gl9763e_cqe_post_disable()
1815 	return 0;  in gl9763e_add_host()
1863 	struct sdhci_pci_slot *slot = chip->slots[0];  in gl9763e_runtime_suspend()
1874 	return 0;  in gl9763e_runtime_suspend()
1879 	struct sdhci_pci_slot *slot = chip->slots[0];  in gl9763e_runtime_resume()
1884 		return 0;  in gl9763e_runtime_resume()
1906 	return 0;  in gl9763e_runtime_resume()
1913 	struct sdhci_pci_slot *slot = chip->slots[0];  in sdhci_pci_gli_resume()
1923 	struct sdhci_pci_slot *slot = chip->slots[0];  in gl9763e_resume()
1940 	return 0;  in gl9763e_resume()
1945 	struct sdhci_pci_slot *slot = chip->slots[0];  in gl9763e_suspend()
1964 	return 0;  in gl9763e_suspend()
2000 	return 0;  in gli_probe_slot_gl9763e()
2003 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
2010 	word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;  in sdhci_gli_readw()
2017 	u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;  in sdhci_gli_readb()