17 /* Extra registers for Arasan SD/SDIO/MMC Host Controller with PHY */
93 static int arasan_phy_addr_poll(struct sdhci_host *host, u32 offset, u32 mask)  in arasan_phy_addr_poll()  argument
101 		val = sdhci_readw(host, PHY_ADDR_REG);  in arasan_phy_addr_poll()
109 static int arasan_phy_write(struct sdhci_host *host, u8 data, u8 offset)  in arasan_phy_write()  argument
111 	sdhci_writew(host, data, PHY_DAT_REG);  in arasan_phy_write()
112 	sdhci_writew(host, (PHY_WRITE | offset), PHY_ADDR_REG);  in arasan_phy_write()
113 	return arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);  in arasan_phy_write()
116 static int arasan_phy_read(struct sdhci_host *host, u8 offset, u8 *data)  in arasan_phy_read()  argument
120 	sdhci_writew(host, 0, PHY_DAT_REG);  in arasan_phy_read()
121 	sdhci_writew(host, offset, PHY_ADDR_REG);  in arasan_phy_read()
122 	ret = arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);  in arasan_phy_read()
125 	*data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK;  in arasan_phy_read()
129 static int arasan_phy_sts_poll(struct sdhci_host *host, u32 offset, u32 mask)  in arasan_phy_sts_poll()  argument
138 		ret = arasan_phy_read(host, offset, &val);  in arasan_phy_sts_poll()
149 static int arasan_phy_init(struct sdhci_host *host)  in arasan_phy_init()  argument
155 	if (arasan_phy_read(host, IPAD_CTRL1, &val) ||  in arasan_phy_init()
156 	    arasan_phy_write(host, val | RETB_ENBL | PDB_ENBL, IPAD_CTRL1) ||  in arasan_phy_init()
157 	    arasan_phy_read(host, IPAD_CTRL2, &val) ||  in arasan_phy_init()
158 	    arasan_phy_write(host, val | RTRIM_EN, IPAD_CTRL2))  in arasan_phy_init()
160 	ret = arasan_phy_sts_poll(host, IPAD_STS, CALDONE_MASK);  in arasan_phy_init()
165 	if (arasan_phy_read(host, IOREN_CTRL1, &val) ||  in arasan_phy_init()
166 	    arasan_phy_write(host, val | REN_CMND | REN_STRB, IOREN_CTRL1) ||  in arasan_phy_init()
167 	    arasan_phy_read(host, IOPU_CTRL1, &val) ||  in arasan_phy_init()
168 	    arasan_phy_write(host, val | PU_CMD, IOPU_CTRL1) ||  in arasan_phy_init()
169 	    arasan_phy_read(host, CMD_CTRL, &val) ||  in arasan_phy_init()
170 	    arasan_phy_write(host, val | PDB_CMND, CMD_CTRL) ||  in arasan_phy_init()
171 	    arasan_phy_read(host, IOREN_CTRL2, &val) ||  in arasan_phy_init()
172 	    arasan_phy_write(host, val | REN_DATA, IOREN_CTRL2) ||  in arasan_phy_init()
173 	    arasan_phy_read(host, IOPU_CTRL2, &val) ||  in arasan_phy_init()
174 	    arasan_phy_write(host, val | PU_DAT, IOPU_CTRL2) ||  in arasan_phy_init()
175 	    arasan_phy_read(host, DATA_CTRL, &val) ||  in arasan_phy_init()
176 	    arasan_phy_write(host, val | PDB_DATA, DATA_CTRL) ||  in arasan_phy_init()
177 	    arasan_phy_read(host, STRB_CTRL, &val) ||  in arasan_phy_init()
178 	    arasan_phy_write(host, val | PDB_STRB, STRB_CTRL) ||  in arasan_phy_init()
179 	    arasan_phy_read(host, CLK_CTRL, &val) ||  in arasan_phy_init()
180 	    arasan_phy_write(host, val | PDB_CLOCK, CLK_CTRL) ||  in arasan_phy_init()
181 	    arasan_phy_read(host, CLKBUF_SEL, &val) ||  in arasan_phy_init()
182 	    arasan_phy_write(host, val | MAX_CLK_BUF, CLKBUF_SEL) ||  in arasan_phy_init()
183 	    arasan_phy_write(host, LEGACY_MODE, MODE_CTRL))  in arasan_phy_init()
189 static int arasan_phy_set(struct sdhci_host *host, u8 mode, u8 otap,  in arasan_phy_set()  argument
196 		ret = arasan_phy_write(host, 0x0, MODE_CTRL);  in arasan_phy_set()
198 		ret = arasan_phy_write(host, mode, MODE_CTRL);  in arasan_phy_set()
202 		ret = arasan_phy_read(host, IPAD_CTRL1, &val);  in arasan_phy_set()
205 		ret = arasan_phy_write(host, IOPAD(val, drv_type), IPAD_CTRL1);  in arasan_phy_set()
210 		ret = arasan_phy_write(host, 0x0, OTAP_DELAY);  in arasan_phy_set()
213 		ret = arasan_phy_write(host, 0x0, ITAP_DELAY);  in arasan_phy_set()
215 		ret = arasan_phy_write(host, OTAPDLY(otap), OTAP_DELAY);  in arasan_phy_set()
219 			ret = arasan_phy_write(host, ITAPDLY(itap), ITAP_DELAY);  in arasan_phy_set()
221 			ret = arasan_phy_write(host, 0x0, ITAP_DELAY);  in arasan_phy_set()
226 		ret = arasan_phy_write(host, trim, DLL_TRIM);  in arasan_phy_set()
230 	ret = arasan_phy_write(host, 0, DLL_STATUS);  in arasan_phy_set()
234 		ret = arasan_phy_write(host, FREQSEL(clk), DLL_STATUS);  in arasan_phy_set()
237 		ret = arasan_phy_sts_poll(host, DLL_STATUS, DLL_RDY_MASK);  in arasan_phy_set()
244 static int arasan_select_phy_clock(struct sdhci_host *host)  in arasan_select_phy_clock()  argument
246 	struct sdhci_pci_slot *slot = sdhci_priv(host);  in arasan_select_phy_clock()
250 	if (arasan_host->chg_clk == host->mmc->ios.clock)  in arasan_select_phy_clock()
253 	arasan_host->chg_clk = host->mmc->ios.clock;  in arasan_select_phy_clock()
254 	if (host->mmc->ios.clock == 200000000)  in arasan_select_phy_clock()
256 	else if (host->mmc->ios.clock == 100000000)  in arasan_select_phy_clock()
258 	else if (host->mmc->ios.clock == 50000000)  in arasan_select_phy_clock()
263 	if (host->mmc_host_ops.hs400_enhanced_strobe) {  in arasan_select_phy_clock()
264 		arasan_phy_set(host, ENHSTRB_MODE, 1, 0x0, 0x0,  in arasan_select_phy_clock()
267 		switch (host->mmc->ios.timing) {  in arasan_select_phy_clock()
269 			arasan_phy_set(host, LEGACY_MODE, 0x0, 0x0, 0x0,  in arasan_select_phy_clock()
274 			arasan_phy_set(host, HISPD_MODE, 0x3, 0x0, 0x2,  in arasan_select_phy_clock()
279 			arasan_phy_set(host, HS200_MODE, 0x2,  in arasan_select_phy_clock()
280 				       host->mmc->ios.drv_type, 0x0,  in arasan_select_phy_clock()
285 			arasan_phy_set(host, DDR50_MODE, 0x1, 0x0,  in arasan_select_phy_clock()
289 			arasan_phy_set(host, HS400_MODE, 0x1,  in arasan_select_phy_clock()
290 				       host->mmc->ios.drv_type, 0xa,  in arasan_select_phy_clock()
304 	slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | MMC_CAP_8_BIT_DATA;  in arasan_pci_probe_slot()
305 	err = arasan_phy_init(slot->host);  in arasan_pci_probe_slot()
311 static void arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)  in arasan_sdhci_set_clock()  argument
313 	sdhci_set_clock(host, clock);  in arasan_sdhci_set_clock()
316 	arasan_select_phy_clock(host);  in arasan_sdhci_set_clock()