Lines Matching +full:hs400 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
25 #include "sdhci-pltfm.h"
42 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
52 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
54 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
152 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
154 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
155 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */
157 /* PHY CLK delay line settings */
162 /* PHY CLK delay line delay code */
164 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */
165 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */
166 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */
171 /* PHY drift_cclk_rx delay line configuration setting */
174 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */
175 #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */
185 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */
192 /* PHY DLL master and slave delay line configuration settings */
200 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
206 /* SMC call for BlueField-3 eMMC RST_N */
224 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */
225 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */
227 int num_other_clks;
237 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
241 static int dwcmshc_get_enable_other_clks(struct device *dev, in dwcmshc_get_enable_other_clks()
243 int num_clks, in dwcmshc_get_enable_other_clks()
246 int err; in dwcmshc_get_enable_other_clks()
249 return -EINVAL; in dwcmshc_get_enable_other_clks()
251 for (int i = 0; i < num_clks; i++) in dwcmshc_get_enable_other_clks()
252 priv->other_clks[i].id = clk_ids[i]; in dwcmshc_get_enable_other_clks()
254 err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks); in dwcmshc_get_enable_other_clks()
260 err = clk_bulk_prepare_enable(num_clks, priv->other_clks); in dwcmshc_get_enable_other_clks()
264 priv->num_other_clks = num_clks; in dwcmshc_get_enable_other_clks()
274 dma_addr_t addr, int len, unsigned int cmd) in dwcmshc_adma_write_desc() argument
276 int tmplen, offset; in dwcmshc_adma_write_desc()
279 sdhci_adma_write_desc(host, desc, addr, len, cmd); in dwcmshc_adma_write_desc()
283 offset = addr & (SZ_128M - 1); in dwcmshc_adma_write_desc()
284 tmplen = SZ_128M - offset; in dwcmshc_adma_write_desc()
285 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); in dwcmshc_adma_write_desc()
288 len -= tmplen; in dwcmshc_adma_write_desc()
289 sdhci_adma_write_desc(host, desc, addr, len, cmd); in dwcmshc_adma_write_desc()
292 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) in dwcmshc_get_max_clock()
296 if (pltfm_host->clk) in dwcmshc_get_max_clock()
299 return pltfm_host->clock; in dwcmshc_get_max_clock()
302 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) in rk35xx_get_max_clock()
306 return clk_round_rate(pltfm_host->clk, ULONG_MAX); in rk35xx_get_max_clock()
315 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit in dwcmshc_check_auto_cmd23()
319 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) in dwcmshc_check_auto_cmd23()
320 host->flags &= ~SDHCI_AUTO_CMD23; in dwcmshc_check_auto_cmd23()
322 host->flags |= SDHCI_AUTO_CMD23; in dwcmshc_check_auto_cmd23()
339 if (priv->flags & FLAG_IO_FIXED_1V8 || in dwcmshc_phy_init()
340 host->mmc->ios.timing & MMC_SIGNAL_VOLTAGE_180) in dwcmshc_phy_init()
349 /* disable delay line */ in dwcmshc_phy_init()
352 /* set delay line */ in dwcmshc_phy_init()
353 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); in dwcmshc_phy_init()
356 /* enable delay lane */ in dwcmshc_phy_init()
401 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { in th1520_sdhci_set_phy()
402 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in th1520_sdhci_set_phy()
404 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in th1520_sdhci_set_phy()
412 unsigned int timing) in dwcmshc_set_uhs_signaling()
435 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ in dwcmshc_set_uhs_signaling()
436 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in dwcmshc_set_uhs_signaling()
438 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); in dwcmshc_set_uhs_signaling()
443 if (priv->flags & FLAG_IO_FIXED_1V8) in dwcmshc_set_uhs_signaling()
449 unsigned int timing) in th1520_set_uhs_signaling()
456 priv->delay_line = PHY_SDCLKDL_DC_HS400; in th1520_set_uhs_signaling()
469 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; in dwcmshc_hs400_enhanced_strobe()
472 if (ios->enhanced_strobe) in dwcmshc_hs400_enhanced_strobe()
480 static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode) in dwcmshc_execute_tuning()
482 int err = sdhci_execute_tuning(mmc, opcode); in dwcmshc_execute_tuning()
500 int cmd_error = 0; in dwcmshc_cqe_irq_handler()
501 int data_error = 0; in dwcmshc_cqe_irq_handler()
506 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in dwcmshc_cqe_irq_handler()
525 * Selection of 32-bit/64-bit System Addressing: in dwcmshc_sdhci_cqe_enable()
526 * either 32-bit or 64-bit system addressing is selected by in dwcmshc_sdhci_cqe_enable()
527 * 64-bit Addressing bit in Host Control 2 register. in dwcmshc_sdhci_cqe_enable()
540 dma_addr_t addr, int len, bool end, bool dma64) in dwcmshc_set_tran_desc()
542 int tmplen, offset; in dwcmshc_set_tran_desc()
549 offset = addr & (SZ_128M - 1); in dwcmshc_set_tran_desc()
550 tmplen = SZ_128M - offset; in dwcmshc_set_tran_desc()
554 len -= tmplen; in dwcmshc_set_tran_desc()
555 *desc += cq_host->trans_desc_len; in dwcmshc_set_tran_desc()
564 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) in dwcmshc_rk3568_set_clock()
568 struct rk35xx_priv *priv = dwc_priv->priv; in dwcmshc_rk3568_set_clock()
571 int err; in dwcmshc_rk3568_set_clock()
573 host->mmc->actual_clock = 0; in dwcmshc_rk3568_set_clock()
585 err = clk_set_rate(pltfm_host->clk, clock); in dwcmshc_rk3568_set_clock()
587 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); in dwcmshc_rk3568_set_clock()
591 /* Disable cmd conflict check */ in dwcmshc_rk3568_set_clock()
592 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; in dwcmshc_rk3568_set_clock()
628 if (priv->devtype == DWCMSHC_RK3568) in dwcmshc_rk3568_set_clock()
637 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, in dwcmshc_rk3568_set_clock()
641 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); in dwcmshc_rk3568_set_clock()
646 0x3 << 17 | /* pre-change delay */ in dwcmshc_rk3568_set_clock()
647 0x3 << 19; /* post-change delay */ in dwcmshc_rk3568_set_clock()
648 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); in dwcmshc_rk3568_set_clock()
650 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || in dwcmshc_rk3568_set_clock()
651 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) in dwcmshc_rk3568_set_clock()
652 txclk_tapnum = priv->txclk_tapnum; in dwcmshc_rk3568_set_clock()
654 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { in dwcmshc_rk3568_set_clock()
681 struct rk35xx_priv *priv = dwc_priv->priv; in rk35xx_sdhci_reset()
683 if (mask & SDHCI_RESET_ALL && priv->reset) { in rk35xx_sdhci_reset()
684 reset_control_assert(priv->reset); in rk35xx_sdhci_reset()
686 reset_control_deassert(priv->reset); in rk35xx_sdhci_reset()
692 static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host, in dwcmshc_rk35xx_init()
697 int err; in dwcmshc_rk35xx_init()
701 return -ENOMEM; in dwcmshc_rk35xx_init()
703 if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc")) in dwcmshc_rk35xx_init()
704 priv->devtype = DWCMSHC_RK3588; in dwcmshc_rk35xx_init()
706 priv->devtype = DWCMSHC_RK3568; in dwcmshc_rk35xx_init()
708 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); in dwcmshc_rk35xx_init()
709 if (IS_ERR(priv->reset)) { in dwcmshc_rk35xx_init()
710 err = PTR_ERR(priv->reset); in dwcmshc_rk35xx_init()
711 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); in dwcmshc_rk35xx_init()
715 err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, in dwcmshc_rk35xx_init()
720 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", in dwcmshc_rk35xx_init()
721 &priv->txclk_tapnum)) in dwcmshc_rk35xx_init()
722 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; in dwcmshc_rk35xx_init()
724 /* Disable cmd conflict check */ in dwcmshc_rk35xx_init()
725 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); in dwcmshc_rk35xx_init()
730 dwc_priv->priv = priv; in dwcmshc_rk35xx_init()
741 if (host->mmc->f_max <= 52000000) { in dwcmshc_rk35xx_postinit()
742 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", in dwcmshc_rk35xx_postinit()
743 host->mmc->f_max); in dwcmshc_rk35xx_postinit()
744 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); in dwcmshc_rk35xx_postinit()
745 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); in dwcmshc_rk35xx_postinit()
751 struct device *dev = mmc_dev(host->mmc); in dwcmshc_rk3576_postinit()
752 int ret; in dwcmshc_rk3576_postinit()
757 * RK3576 is in, never come back the same way once it's run-time in dwcmshc_rk3576_postinit()
765 if (ret && ret != -EOPNOTSUPP) in dwcmshc_rk3576_postinit()
772 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) in th1520_execute_tuning()
778 if (host->flags & SDHCI_HS400_TUNING) in th1520_execute_tuning()
783 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); in th1520_execute_tuning()
787 * - center phase select code driven in block gap interval in th1520_execute_tuning()
788 * - disable reporting of framing errors in th1520_execute_tuning()
789 * - disable software managed tuning in th1520_execute_tuning()
790 * - disable user selection of sampling window edges, in th1520_execute_tuning()
798 * - enable auto-tuning in th1520_execute_tuning()
799 * - enable sampling window threshold in th1520_execute_tuning()
800 * - stop clocks during phase code change in th1520_execute_tuning()
801 * - set max latency in cycles between tx and rx clocks in th1520_execute_tuning()
802 * - set max latency in cycles to switch output phase in th1520_execute_tuning()
803 * - set max sampling window threshold value in th1520_execute_tuning()
810 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); in th1520_execute_tuning()
811 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); in th1520_execute_tuning()
815 host->tuning_loop_count = 128; in th1520_execute_tuning()
816 host->tuning_err = __sdhci_execute_tuning(host, opcode); in th1520_execute_tuning()
817 if (host->tuning_err) { in th1520_execute_tuning()
818 /* disable auto-tuning upon tuning error */ in th1520_execute_tuning()
820 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); in th1520_execute_tuning()
821 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); in th1520_execute_tuning()
822 return -EIO; in th1520_execute_tuning()
837 /* The T-Head 1520 SoC does not comply with the SDHCI specification in th1520_sdhci_reset()
838 * regarding the "Software Reset for CMD line should clear 'Command in th1520_sdhci_reset()
845 if (priv->flags & FLAG_IO_FIXED_1V8) { in th1520_sdhci_reset()
854 static int th1520_init(struct device *dev, in th1520_init()
858 dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; in th1520_init()
860 if (device_property_read_bool(dev, "mmc-ddr-1_8v") || in th1520_init()
861 device_property_read_bool(dev, "mmc-hs200-1_8v") || in th1520_init()
862 device_property_read_bool(dev, "mmc-hs400-1_8v")) in th1520_init()
863 dwc_priv->flags |= FLAG_IO_FIXED_1V8; in th1520_init()
865 dwc_priv->flags &= ~FLAG_IO_FIXED_1V8; in th1520_init()
873 if (dwc_priv->flags & FLAG_IO_FIXED_1V8) { in th1520_init()
874 host->flags &= ~SDHCI_SIGNALING_330; in th1520_init()
875 host->flags |= SDHCI_SIGNALING_180; in th1520_init()
891 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { in cv18xx_sdhci_reset()
892 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_reset()
894 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_reset()
897 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_reset()
899 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_reset()
901 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); in cv18xx_sdhci_reset()
903 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); in cv18xx_sdhci_reset()
909 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); in cv18xx_sdhci_reset()
912 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap) in cv18xx_sdhci_set_tap()
923 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_set_tap()
925 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_set_tap()
930 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); in cv18xx_sdhci_set_tap()
932 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); in cv18xx_sdhci_set_tap()
939 static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error) in cv18xx_retry_tuning()
941 int ret, retry = 0; in cv18xx_retry_tuning()
964 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) in cv18xx_sdhci_execute_tuning()
966 int min, max, avg, ret; in cv18xx_sdhci_execute_tuning()
967 int win_length, target_min, target_max, target_win_length; in cv18xx_sdhci_execute_tuning()
975 /* find the mininum delay first which can pass tuning */ in cv18xx_sdhci_execute_tuning()
978 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL)) in cv18xx_sdhci_execute_tuning()
983 /* find the maxinum delay which can not pass tuning */ in cv18xx_sdhci_execute_tuning()
987 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) { in cv18xx_sdhci_execute_tuning()
988 max -= CV18XX_TUNE_STEP; in cv18xx_sdhci_execute_tuning()
994 win_length = max - min + 1; in cv18xx_sdhci_execute_tuning()
1008 /* use average delay to get the best timing */ in cv18xx_sdhci_execute_tuning()
1011 ret = mmc_send_tuning(host->mmc, opcode, NULL); in cv18xx_sdhci_execute_tuning()
1013 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in cv18xx_sdhci_execute_tuning()
1051 /* Configure delay line */ in sg2042_sdhci_phy_init()
1052 /* Enable fixed delay */ in sg2042_sdhci_phy_init()
1055 * Set delay line. in sg2042_sdhci_phy_init()
1062 /* Add 10 * 70ps = 0.7ns for output delay */ in sg2042_sdhci_phy_init()
1089 static int sg2042_init(struct device *dev, struct sdhci_host *host, in sg2042_init()
1094 return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, in sg2042_init()
1116 pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc)); in dwcmshc_bf3_hw_reset()
1255 int err; in dwcmshc_cqhci_init()
1257 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in dwcmshc_cqhci_init()
1258 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in dwcmshc_cqhci_init()
1260 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n"); in dwcmshc_cqhci_init()
1273 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n"); in dwcmshc_cqhci_init()
1277 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; in dwcmshc_cqhci_init()
1278 cq_host->ops = &dwcmshc_cqhci_ops; in dwcmshc_cqhci_init()
1280 /* Enable using of 128-bit task descriptors */ in dwcmshc_cqhci_init()
1281 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in dwcmshc_cqhci_init()
1283 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n"); in dwcmshc_cqhci_init()
1284 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in dwcmshc_cqhci_init()
1286 err = cqhci_init(cq_host, host->mmc, dma64); in dwcmshc_cqhci_init()
1288 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err); in dwcmshc_cqhci_init()
1292 dev_dbg(mmc_dev(host->mmc), "CQE init done\n"); in dwcmshc_cqhci_init()
1302 devm_kfree(&pdev->dev, cq_host); in dwcmshc_cqhci_init()
1305 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); in dwcmshc_cqhci_init()
1310 .compatible = "rockchip,rk3588-dwcmshc",
1314 .compatible = "rockchip,rk3576-dwcmshc",
1318 .compatible = "rockchip,rk3568-dwcmshc",
1322 .compatible = "snps,dwcmshc-sdhci",
1326 .compatible = "sophgo,cv1800b-dwcmshc",
1330 .compatible = "sophgo,sg2002-dwcmshc",
1334 .compatible = "thead,th1520-dwcmshc",
1338 .compatible = "sophgo,sg2042-dwcmshc",
1356 static int dwcmshc_probe(struct platform_device *pdev) in dwcmshc_probe()
1358 struct device *dev = &pdev->dev; in dwcmshc_probe()
1363 int err; in dwcmshc_probe()
1366 pltfm_data = device_get_match_data(&pdev->dev); in dwcmshc_probe()
1368 dev_err(&pdev->dev, "Error: No device match data found\n"); in dwcmshc_probe()
1369 return -ENODEV; in dwcmshc_probe()
1372 host = sdhci_pltfm_init(pdev, &pltfm_data->pdata, in dwcmshc_probe()
1383 host->adma_table_cnt += extra; in dwcmshc_probe()
1388 if (dev->of_node) { in dwcmshc_probe()
1389 pltfm_host->clk = devm_clk_get(dev, "core"); in dwcmshc_probe()
1390 if (IS_ERR(pltfm_host->clk)) { in dwcmshc_probe()
1391 err = PTR_ERR(pltfm_host->clk); in dwcmshc_probe()
1395 err = clk_prepare_enable(pltfm_host->clk); in dwcmshc_probe()
1399 priv->bus_clk = devm_clk_get(dev, "bus"); in dwcmshc_probe()
1400 if (!IS_ERR(priv->bus_clk)) in dwcmshc_probe()
1401 clk_prepare_enable(priv->bus_clk); in dwcmshc_probe()
1404 err = mmc_of_parse(host->mmc); in dwcmshc_probe()
1410 priv->vendor_specific_area1 = in dwcmshc_probe()
1413 host->mmc_host_ops.request = dwcmshc_request; in dwcmshc_probe()
1414 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; in dwcmshc_probe()
1415 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; in dwcmshc_probe()
1417 if (pltfm_data->init) { in dwcmshc_probe()
1418 err = pltfm_data->init(&pdev->dev, host, priv); in dwcmshc_probe()
1432 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in dwcmshc_probe()
1443 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { in dwcmshc_probe()
1444 priv->vendor_specific_area2 = in dwcmshc_probe()
1450 if (pltfm_data->postinit) in dwcmshc_probe()
1451 pltfm_data->postinit(host, priv); in dwcmshc_probe()
1467 clk_disable_unprepare(pltfm_host->clk); in dwcmshc_probe()
1468 clk_disable_unprepare(priv->bus_clk); in dwcmshc_probe()
1469 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); in dwcmshc_probe()
1492 pm_runtime_get_sync(&pdev->dev); in dwcmshc_remove()
1493 pm_runtime_disable(&pdev->dev); in dwcmshc_remove()
1494 pm_runtime_put_noidle(&pdev->dev); in dwcmshc_remove()
1500 clk_disable_unprepare(pltfm_host->clk); in dwcmshc_remove()
1501 clk_disable_unprepare(priv->bus_clk); in dwcmshc_remove()
1502 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); in dwcmshc_remove()
1507 static int dwcmshc_suspend(struct device *dev) in dwcmshc_suspend()
1512 int ret; in dwcmshc_suspend()
1516 if (host->mmc->caps2 & MMC_CAP2_CQE) { in dwcmshc_suspend()
1517 ret = cqhci_suspend(host->mmc); in dwcmshc_suspend()
1526 clk_disable_unprepare(pltfm_host->clk); in dwcmshc_suspend()
1527 if (!IS_ERR(priv->bus_clk)) in dwcmshc_suspend()
1528 clk_disable_unprepare(priv->bus_clk); in dwcmshc_suspend()
1530 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); in dwcmshc_suspend()
1535 static int dwcmshc_resume(struct device *dev) in dwcmshc_resume()
1540 int ret; in dwcmshc_resume()
1542 ret = clk_prepare_enable(pltfm_host->clk); in dwcmshc_resume()
1546 if (!IS_ERR(priv->bus_clk)) { in dwcmshc_resume()
1547 ret = clk_prepare_enable(priv->bus_clk); in dwcmshc_resume()
1552 ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks); in dwcmshc_resume()
1560 if (host->mmc->caps2 & MMC_CAP2_CQE) { in dwcmshc_resume()
1561 ret = cqhci_resume(host->mmc); in dwcmshc_resume()
1569 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); in dwcmshc_resume()
1571 if (!IS_ERR(priv->bus_clk)) in dwcmshc_resume()
1572 clk_disable_unprepare(priv->bus_clk); in dwcmshc_resume()
1574 clk_disable_unprepare(pltfm_host->clk); in dwcmshc_resume()
1592 static int dwcmshc_runtime_suspend(struct device *dev) in dwcmshc_runtime_suspend()
1601 static int dwcmshc_runtime_resume(struct device *dev) in dwcmshc_runtime_resume()
1620 .name = "sdhci-dwcmshc",