Lines Matching full:dll

177 /* PHY DLL control settings */
179 #define PHY_DLL_CTRL_DISABLE		0x0 /* PHY DLL is enabled */
180 #define PHY_DLL_CTRL_ENABLE		0x1 /* PHY DLL is disabled */
182 /* PHY DLL  configuration register 1 */
185 #define PHY_DLL_CNFG1_SLVDLY		0x2 /* DLL slave update delay input */
186 #define PHY_DLL_CNFG1_WAITCYCLE		0x5 /* DLL wait cycle input */
188 /* PHY DLL configuration register 2 */
190 #define PHY_DLL_CNFG2_JUMPSTEP		0xa /* DLL jump step input */
192 /* PHY DLL master and slave delay line configuration settings */
387 	/* enable phy dll */  in dwcmshc_phy_init()
599 		 * Disable DLL and reset both of sample and drive clock.  in dwcmshc_rk3568_set_clock()
600 		 * The bypass bit and start bit need to be set if DLL is not locked.  in dwcmshc_rk3568_set_clock()
618 	/* Reset DLL */  in dwcmshc_rk3568_set_clock()
632 	/* Init DLL settings */  in dwcmshc_rk3568_set_clock()
641 		dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");  in dwcmshc_rk3568_set_clock()
739 	 * cannot use DLL for this condition.  in dwcmshc_rk35xx_postinit()