1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9  * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
94  * On some SoCs the syscon area has a feature where the upper 16-bits of
95  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
106  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
110  * @shift:	Bit offset within @reg of this field (or -1 if not avail)
119  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
138  * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
149  * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
172  * struct sdhci_arasan_data - Arasan Controller Data
174  * @host:		Pointer to the main SDHCI host structure.
212 /* Enable CD stable check before power-up */
231 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
237 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
252 	reg = readl(host->ioaddr + PHY_CTRL_REG2);  in sdhci_arasan_phy_set_delaychain()
258 	writel(reg, host->ioaddr + PHY_CTRL_REG2);  in sdhci_arasan_phy_set_delaychain()
265 	reg = readl(host->ioaddr + PHY_CTRL_REG2);  in sdhci_arasan_phy_set_dll()
271 	writel(reg, host->ioaddr + PHY_CTRL_REG2);  in sdhci_arasan_phy_set_dll()
276 	return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,  in sdhci_arasan_phy_set_dll()
297 	reg = readl(host->ioaddr + PHY_CTRL_REG2);  in sdhci_arasan_phy_dll_set_freq()
300 	writel(reg, host->ioaddr + PHY_CTRL_REG2);  in sdhci_arasan_phy_dll_set_freq()
304  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
323 	struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;  in sdhci_arasan_syscon_write()
324 	u32 reg = fld->reg;  in sdhci_arasan_syscon_write()
325 	u16 width = fld->width;  in sdhci_arasan_syscon_write()
326 	s16 shift = fld->shift;  in sdhci_arasan_syscon_write()
336 		return -EINVAL;  in sdhci_arasan_syscon_write()
338 	if (sdhci_arasan->soc_ctl_map->hiword_update)  in sdhci_arasan_syscon_write()
350 			 mmc_hostname(host->mmc), ret);  in sdhci_arasan_syscon_write()
359 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_set_clock()
362 	if (!IS_ERR(sdhci_arasan->phy)) {  in sdhci_arasan_set_clock()
363 		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {  in sdhci_arasan_set_clock()
377 			sdhci_set_clock(host, host->max_clk);  in sdhci_arasan_set_clock()
378 			if (phy_power_on(sdhci_arasan->phy)) {  in sdhci_arasan_set_clock()
380 				       mmc_hostname(host->mmc));  in sdhci_arasan_set_clock()
384 			sdhci_arasan->is_phy_on = true;  in sdhci_arasan_set_clock()
401 	if (ctrl_phy && sdhci_arasan->is_phy_on) {  in sdhci_arasan_set_clock()
402 		phy_power_off(sdhci_arasan->phy);  in sdhci_arasan_set_clock()
403 		sdhci_arasan->is_phy_on = false;  in sdhci_arasan_set_clock()
406 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {  in sdhci_arasan_set_clock()
417 	if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ)  in sdhci_arasan_set_clock()
418 		clk_data->set_clk_delays(host);  in sdhci_arasan_set_clock()
420 	if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {  in sdhci_arasan_set_clock()
425 	} else if (sdhci_arasan->internal_phy_reg) {  in sdhci_arasan_set_clock()
432 	if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ)  in sdhci_arasan_set_clock()
435 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)  in sdhci_arasan_set_clock()
446 		if (phy_power_on(sdhci_arasan->phy)) {  in sdhci_arasan_set_clock()
448 			       mmc_hostname(host->mmc));  in sdhci_arasan_set_clock()
452 		sdhci_arasan->is_phy_on = true;  in sdhci_arasan_set_clock()
463 	if (ios->enhanced_strobe)  in sdhci_arasan_hs400_enhanced_strobe()
479 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {  in sdhci_arasan_reset()
504 	switch (ios->signal_voltage) {  in sdhci_arasan_voltage_switch()
520 	return -EINVAL;  in sdhci_arasan_voltage_switch()
534 	if (mode == MMC_POWER_UP && sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE)  in sdhci_arasan_set_power_and_bus_voltage()
560 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);  in sdhci_arasan_cqhci_irq()
610  * sdhci_arasan_suspend - Suspend method for the driver
624 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)  in sdhci_arasan_suspend()
625 		mmc_retune_needed(host->mmc);  in sdhci_arasan_suspend()
627 	if (sdhci_arasan->has_cqe) {  in sdhci_arasan_suspend()
628 		ret = cqhci_suspend(host->mmc);  in sdhci_arasan_suspend()
637 	if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {  in sdhci_arasan_suspend()
638 		ret = phy_power_off(sdhci_arasan->phy);  in sdhci_arasan_suspend()
646 		sdhci_arasan->is_phy_on = false;  in sdhci_arasan_suspend()
649 	clk_disable(pltfm_host->clk);  in sdhci_arasan_suspend()
650 	clk_disable(sdhci_arasan->clk_ahb);  in sdhci_arasan_suspend()
656  * sdhci_arasan_resume - Resume method for the driver
670 	ret = clk_enable(sdhci_arasan->clk_ahb);  in sdhci_arasan_resume()
676 	ret = clk_enable(pltfm_host->clk);  in sdhci_arasan_resume()
682 	if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {  in sdhci_arasan_resume()
683 		ret = phy_power_on(sdhci_arasan->phy);  in sdhci_arasan_resume()
688 		sdhci_arasan->is_phy_on = true;  in sdhci_arasan_resume()
697 	if (sdhci_arasan->has_cqe)  in sdhci_arasan_resume()
698 		return cqhci_resume(host->mmc);  in sdhci_arasan_resume()
708  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
725 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_arasan_sdcardclk_recalc_rate()
727 	return host->mmc->actual_clock;  in sdhci_arasan_sdcardclk_recalc_rate()
735  * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
752 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_arasan_sampleclk_recalc_rate()
754 	return host->mmc->actual_clock;  in sdhci_arasan_sampleclk_recalc_rate()
762  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
765  * @degrees:		The clock phase shift between 0 - 359.
777 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_zynqmp_sdcardclk_set_phase()
784 	if (host->version < SDHCI_SPEC_300)  in sdhci_zynqmp_sdcardclk_set_phase()
787 	switch (host->timing) {  in sdhci_zynqmp_sdcardclk_set_phase()
828  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
831  * @degrees:		The clock phase shift between 0 - 359.
843 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_zynqmp_sampleclk_set_phase()
850 	if (host->version < SDHCI_SPEC_300)  in sdhci_zynqmp_sampleclk_set_phase()
856 	switch (host->timing) {  in sdhci_zynqmp_sampleclk_set_phase()
894  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
897  * @degrees:		The clock phase shift between 0 - 359.
909 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_versal_sdcardclk_set_phase()
913 	if (host->version < SDHCI_SPEC_300)  in sdhci_versal_sdcardclk_set_phase()
916 	switch (host->timing) {  in sdhci_versal_sdcardclk_set_phase()
961  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
964  * @degrees:		The clock phase shift between 0 - 359.
976 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_versal_sampleclk_set_phase()
980 	if (host->version < SDHCI_SPEC_300)  in sdhci_versal_sampleclk_set_phase()
983 	switch (host->timing) {  in sdhci_versal_sampleclk_set_phase()
1037 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_versal_net_emmc_sdcardclk_set_phase()
1040 	switch (host->timing) {  in sdhci_versal_net_emmc_sdcardclk_set_phase()
1082 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_versal_net_emmc_sampleclk_set_phase()
1086 	switch (host->timing) {  in sdhci_versal_net_emmc_sampleclk_set_phase()
1147 	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;  in arasan_zynqmp_execute_tuning()
1154 	if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)  in arasan_zynqmp_execute_tuning()
1169  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
1178  * - Many existing devices don't seem to do this and work fine.  To keep
1182  * - The value of corecfg_clockmultiplier should sync with that of corresponding
1192 		sdhci_arasan->soc_ctl_map;  in sdhci_arasan_update_clockmultiplier()
1199 	if (!sdhci_arasan->soc_ctl_base) {  in sdhci_arasan_update_clockmultiplier()
1200 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",  in sdhci_arasan_update_clockmultiplier()
1201 			mmc_hostname(host->mmc));  in sdhci_arasan_update_clockmultiplier()
1205 	sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);  in sdhci_arasan_update_clockmultiplier()
1209  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
1217  * - Many existing devices don't seem to do this and work fine.  To keep
1221  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
1230 		sdhci_arasan->soc_ctl_map;  in sdhci_arasan_update_baseclkfreq()
1231 	u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_arasan_update_baseclkfreq()
1238 	if (!sdhci_arasan->soc_ctl_base) {  in sdhci_arasan_update_baseclkfreq()
1239 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",  in sdhci_arasan_update_baseclkfreq()
1240 			mmc_hostname(host->mmc));  in sdhci_arasan_update_baseclkfreq()
1244 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);  in sdhci_arasan_update_baseclkfreq()
1251 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_set_clk_delays()
1253 	clk_set_phase(clk_data->sampleclk,  in sdhci_arasan_set_clk_delays()
1254 		      clk_data->clk_phase_in[host->timing]);  in sdhci_arasan_set_clk_delays()
1255 	clk_set_phase(clk_data->sdcardclk,  in sdhci_arasan_set_clk_delays()
1256 		      clk_data->clk_phase_out[host->timing]);  in sdhci_arasan_set_clk_delays()
1263 	struct device_node *np = dev->of_node;  in arasan_dt_read_clk_phase()
1270 	 * Tap Values then use the pre-defined values.  in arasan_dt_read_clk_phase()
1276 			prop, clk_data->clk_phase_in[timing],  in arasan_dt_read_clk_phase()
1277 			clk_data->clk_phase_out[timing]);  in arasan_dt_read_clk_phase()
1282 	clk_data->clk_phase_in[timing] = clk_phase[0];  in arasan_dt_read_clk_phase()
1283 	clk_data->clk_phase_out[timing] = clk_phase[1];  in arasan_dt_read_clk_phase()
1287  * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1305 	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;  in arasan_dt_parse_clk_phases()
1307 	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {  in arasan_dt_parse_clk_phases()
1313 		of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);  in arasan_dt_parse_clk_phases()
1320 			clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];  in arasan_dt_parse_clk_phases()
1321 			clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];  in arasan_dt_parse_clk_phases()
1325 	if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {  in arasan_dt_parse_clk_phases()
1332 			clk_data->clk_phase_in[i] = versal_iclk_phase[i];  in arasan_dt_parse_clk_phases()
1333 			clk_data->clk_phase_out[i] = versal_oclk_phase[i];  in arasan_dt_parse_clk_phases()
1336 	if (of_device_is_compatible(dev->of_node, "xlnx,versal-net-emmc")) {  in arasan_dt_parse_clk_phases()
1343 			clk_data->clk_phase_in[i] = versal_net_iclk_phase[i];  in arasan_dt_parse_clk_phases()
1344 			clk_data->clk_phase_out[i] = versal_net_oclk_phase[i];  in arasan_dt_parse_clk_phases()
1348 				 "clk-phase-legacy");  in arasan_dt_parse_clk_phases()
1350 				 "clk-phase-mmc-hs");  in arasan_dt_parse_clk_phases()
1352 				 "clk-phase-sd-hs");  in arasan_dt_parse_clk_phases()
1354 				 "clk-phase-uhs-sdr12");  in arasan_dt_parse_clk_phases()
1356 				 "clk-phase-uhs-sdr25");  in arasan_dt_parse_clk_phases()
1358 				 "clk-phase-uhs-sdr50");  in arasan_dt_parse_clk_phases()
1360 				 "clk-phase-uhs-sdr104");  in arasan_dt_parse_clk_phases()
1362 				 "clk-phase-uhs-ddr50");  in arasan_dt_parse_clk_phases()
1364 				 "clk-phase-mmc-ddr52");  in arasan_dt_parse_clk_phases()
1366 				 "clk-phase-mmc-hs200");  in arasan_dt_parse_clk_phases()
1368 				 "clk-phase-mmc-hs400");  in arasan_dt_parse_clk_phases()
1518 	/* SoC-specific compatible strings w/ soc_ctl_map */
1520 		.compatible = "rockchip,rk3399-sdhci-5.1",
1524 		.compatible = "intel,lgm-sdhci-5.1-emmc",
1528 		.compatible = "intel,lgm-sdhci-5.1-sdxc",
1532 		.compatible = "intel,keembay-sdhci-5.1-emmc",
1536 		.compatible = "intel,keembay-sdhci-5.1-sd",
1540 		.compatible = "intel,keembay-sdhci-5.1-sdio",
1545 		.compatible = "arasan,sdhci-8.9a",
1549 		.compatible = "arasan,sdhci-5.1",
1553 		.compatible = "arasan,sdhci-4.9a",
1557 		.compatible = "xlnx,zynqmp-8.9a",
1561 		.compatible = "xlnx,versal-8.9a",
1565 		.compatible = "xlnx,versal-net-emmc",
1573  * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1590 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_register_sdcardclk()
1591 	struct device_node *np = dev->of_node;  in sdhci_arasan_register_sdcardclk()
1596 	ret = of_property_read_string_index(np, "clock-output-names", 0,  in sdhci_arasan_register_sdcardclk()
1599 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");  in sdhci_arasan_register_sdcardclk()
1607 	sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;  in sdhci_arasan_register_sdcardclk()
1609 	clk_data->sdcardclk_hw.init = &sdcardclk_init;  in sdhci_arasan_register_sdcardclk()
1610 	clk_data->sdcardclk =  in sdhci_arasan_register_sdcardclk()
1611 		devm_clk_register(dev, &clk_data->sdcardclk_hw);  in sdhci_arasan_register_sdcardclk()
1612 	if (IS_ERR(clk_data->sdcardclk))  in sdhci_arasan_register_sdcardclk()
1613 		return PTR_ERR(clk_data->sdcardclk);  in sdhci_arasan_register_sdcardclk()
1614 	clk_data->sdcardclk_hw.init = NULL;  in sdhci_arasan_register_sdcardclk()
1617 				  clk_data->sdcardclk);  in sdhci_arasan_register_sdcardclk()
1625  * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1642 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_register_sampleclk()
1643 	struct device_node *np = dev->of_node;  in sdhci_arasan_register_sampleclk()
1648 	ret = of_property_read_string_index(np, "clock-output-names", 1,  in sdhci_arasan_register_sampleclk()
1651 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");  in sdhci_arasan_register_sampleclk()
1659 	sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;  in sdhci_arasan_register_sampleclk()
1661 	clk_data->sampleclk_hw.init = &sampleclk_init;  in sdhci_arasan_register_sampleclk()
1662 	clk_data->sampleclk =  in sdhci_arasan_register_sampleclk()
1663 		devm_clk_register(dev, &clk_data->sampleclk_hw);  in sdhci_arasan_register_sampleclk()
1664 	if (IS_ERR(clk_data->sampleclk))  in sdhci_arasan_register_sampleclk()
1665 		return PTR_ERR(clk_data->sampleclk);  in sdhci_arasan_register_sampleclk()
1666 	clk_data->sampleclk_hw.init = NULL;  in sdhci_arasan_register_sampleclk()
1669 				  clk_data->sampleclk);  in sdhci_arasan_register_sampleclk()
1677  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1686 	struct device_node *np = dev->of_node;  in sdhci_arasan_unregister_sdclk()
1688 	if (!of_property_present(np, "#clock-cells"))  in sdhci_arasan_unregister_sdclk()
1691 	of_clk_del_provider(dev->of_node);  in sdhci_arasan_unregister_sdclk()
1695  * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1700  * 0: the Core supports only 32-bit System Address Bus.
1701  * 1: the Core supports 64-bit System Address Bus.
1705  * Keem Bay does not support 64-bit access.
1714 	soc_ctl_map = sdhci_arasan->soc_ctl_map;  in sdhci_arasan_update_support64b()
1719 	if (!sdhci_arasan->soc_ctl_base) {  in sdhci_arasan_update_support64b()
1720 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",  in sdhci_arasan_update_support64b()
1721 			mmc_hostname(host->mmc));  in sdhci_arasan_update_support64b()
1725 	sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);  in sdhci_arasan_update_support64b()
1729  * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1739  * Note: without seriously re-architecting SDHCI's clock code and testing on
1745  * re-architecting SDHCI if we see some benefit to it.
1753 	struct device_node *np = dev->of_node;  in sdhci_arasan_register_sdclk()
1758 	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)  in sdhci_arasan_register_sdclk()
1780 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_zynqmp_set_dynamic_config()
1781 	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;  in sdhci_zynqmp_set_dynamic_config()
1804 				      !!(host->mmc->caps & MMC_CAP_NONREMOVABLE));  in sdhci_zynqmp_set_dynamic_config()
1808 	mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_zynqmp_set_dynamic_config()
1823 				      !!(host->mmc->caps & MMC_CAP_8_BIT_DATA));  in sdhci_zynqmp_set_dynamic_config()
1838 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_arasan_add_host()
1843 	if (!sdhci_arasan->has_cqe)  in sdhci_arasan_add_host()
1850 	cq_host = devm_kzalloc(host->mmc->parent,  in sdhci_arasan_add_host()
1853 		ret = -ENOMEM;  in sdhci_arasan_add_host()
1857 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;  in sdhci_arasan_add_host()
1858 	cq_host->ops = &sdhci_arasan_cqhci_ops;  in sdhci_arasan_add_host()
1860 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;  in sdhci_arasan_add_host()
1862 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;  in sdhci_arasan_add_host()
1864 	ret = cqhci_init(cq_host, host->mmc, dma64);  in sdhci_arasan_add_host()
1887 	struct device *dev = &pdev->dev;  in sdhci_arasan_probe()
1888 	struct device_node *np = dev->of_node;  in sdhci_arasan_probe()
1894 		return -EINVAL;  in sdhci_arasan_probe()
1896 	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));  in sdhci_arasan_probe()
1903 	sdhci_arasan->host = host;  in sdhci_arasan_probe()
1905 	sdhci_arasan->soc_ctl_map = data->soc_ctl_map;  in sdhci_arasan_probe()
1906 	sdhci_arasan->clk_ops = data->clk_ops;  in sdhci_arasan_probe()
1908 	node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0);  in sdhci_arasan_probe()
1910 		sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);  in sdhci_arasan_probe()
1913 		if (IS_ERR(sdhci_arasan->soc_ctl_base))  in sdhci_arasan_probe()
1915 					    PTR_ERR(sdhci_arasan->soc_ctl_base),  in sdhci_arasan_probe()
1921 	sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");  in sdhci_arasan_probe()
1922 	if (IS_ERR(sdhci_arasan->clk_ahb))  in sdhci_arasan_probe()
1923 		return dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),  in sdhci_arasan_probe()
1930 	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);  in sdhci_arasan_probe()
1934 	/* If clock-frequency property is set, use the provided value */  in sdhci_arasan_probe()
1935 	if (pltfm_host->clock &&  in sdhci_arasan_probe()
1936 	    pltfm_host->clock != clk_get_rate(clk_xin)) {  in sdhci_arasan_probe()
1937 		ret = clk_set_rate(clk_xin, pltfm_host->clock);  in sdhci_arasan_probe()
1939 			dev_err(&pdev->dev, "Failed to set SD clock rate\n");  in sdhci_arasan_probe()
1956 	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))  in sdhci_arasan_probe()
1957 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;  in sdhci_arasan_probe()
1959 	if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))  in sdhci_arasan_probe()
1960 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;  in sdhci_arasan_probe()
1962 	pltfm_host->clk = clk_xin;  in sdhci_arasan_probe()
1964 	if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))  in sdhci_arasan_probe()
1967 	sdhci_arasan->quirks |= data->quirks;  in sdhci_arasan_probe()
1969 	if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||  in sdhci_arasan_probe()
1970 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||  in sdhci_arasan_probe()
1971 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {  in sdhci_arasan_probe()
1975 		host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;  in sdhci_arasan_probe()
1984 	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {  in sdhci_arasan_probe()
1985 		host->mmc_host_ops.execute_tuning =  in sdhci_arasan_probe()
1988 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;  in sdhci_arasan_probe()
1989 		host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;  in sdhci_arasan_probe()
1992 	arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data);  in sdhci_arasan_probe()
1994 	ret = mmc_of_parse(host->mmc);  in sdhci_arasan_probe()
2000 	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {  in sdhci_arasan_probe()
2009 	sdhci_arasan->phy = ERR_PTR(-ENODEV);  in sdhci_arasan_probe()
2010 	if (of_device_is_compatible(np, "arasan,sdhci-5.1")) {  in sdhci_arasan_probe()
2011 		sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan");  in sdhci_arasan_probe()
2012 		if (IS_ERR(sdhci_arasan->phy)) {  in sdhci_arasan_probe()
2013 			ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy),  in sdhci_arasan_probe()
2014 					    "No phy for arasan,sdhci-5.1.\n");  in sdhci_arasan_probe()
2018 		ret = phy_init(sdhci_arasan->phy);  in sdhci_arasan_probe()
2024 		host->mmc_host_ops.hs400_enhanced_strobe =  in sdhci_arasan_probe()
2026 		host->mmc_host_ops.start_signal_voltage_switch =  in sdhci_arasan_probe()
2028 		sdhci_arasan->has_cqe = true;  in sdhci_arasan_probe()
2029 		host->mmc->caps2 |= MMC_CAP2_CQE;  in sdhci_arasan_probe()
2031 		if (!of_property_read_bool(np, "disable-cqe-dcmd"))  in sdhci_arasan_probe()
2032 			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;  in sdhci_arasan_probe()
2035 	if (of_device_is_compatible(np, "xlnx,versal-net-emmc"))  in sdhci_arasan_probe()
2036 		sdhci_arasan->internal_phy_reg = true;  in sdhci_arasan_probe()
2045 	if (!IS_ERR(sdhci_arasan->phy))  in sdhci_arasan_probe()
2046 		phy_exit(sdhci_arasan->phy);  in sdhci_arasan_probe()
2052 	clk_disable_unprepare(sdhci_arasan->clk_ahb);  in sdhci_arasan_probe()
2061 	struct clk *clk_ahb = sdhci_arasan->clk_ahb;  in sdhci_arasan_remove()
2062 	struct clk *clk_xin = pltfm_host->clk;  in sdhci_arasan_remove()
2064 	if (!IS_ERR(sdhci_arasan->phy)) {  in sdhci_arasan_remove()
2065 		if (sdhci_arasan->is_phy_on)  in sdhci_arasan_remove()
2066 			phy_power_off(sdhci_arasan->phy);  in sdhci_arasan_remove()
2067 		phy_exit(sdhci_arasan->phy);  in sdhci_arasan_remove()
2070 	sdhci_arasan_unregister_sdclk(&pdev->dev);  in sdhci_arasan_remove()
2080 		.name = "sdhci-arasan",
2091 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");