Lines Matching +full:supports +full:- +full:cqe
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
140 /* Max load for eMMC Vdd-io supply */
146 /* Max load for SD Vdd-io supply */
150 msm_host->var_ops->msm_readl_relaxed(host, offset)
153 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
309 return msm_host->offset; in sdhci_priv_msm_offset()
322 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
328 return readl_relaxed(host->ioaddr + offset); in sdhci_msm_v5_variant_readl_relaxed()
337 writel_relaxed(val, msm_host->core_mem + offset); in sdhci_msm_mci_variant_writel_relaxed()
343 writel_relaxed(val, host->ioaddr + offset); in sdhci_msm_v5_variant_writel_relaxed()
348 struct mmc_ios ios = host->mmc->ios; in msm_get_clock_mult_for_bus_mode()
358 host->flags & SDHCI_HS400_TUNING) in msm_get_clock_mult_for_bus_mode()
368 struct mmc_ios curr_ios = host->mmc->ios; in msm_set_clock_rate_for_bus_mode()
369 struct clk *core_clk = msm_host->bulk_clks[0].clk; in msm_set_clock_rate_for_bus_mode()
377 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate); in msm_set_clock_rate_for_bus_mode()
380 mmc_hostname(host->mmc), desired_rate, curr_ios.timing); in msm_set_clock_rate_for_bus_mode()
392 mmc_hostname(host->mmc), desired_rate, achieved_rate); in msm_set_clock_rate_for_bus_mode()
393 host->mmc->actual_clock = achieved_rate / mult; in msm_set_clock_rate_for_bus_mode()
396 msm_host->clk_rate = desired_rate; in msm_set_clock_rate_for_bus_mode()
399 mmc_hostname(host->mmc), achieved_rate, curr_ios.timing); in msm_set_clock_rate_for_bus_mode()
407 struct mmc_host *mmc = host->mmc; in msm_dll_poll_ck_out_en()
412 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
413 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
416 if (--wait_cnt == 0) { in msm_dll_poll_ck_out_en()
419 return -ETIMEDOUT; in msm_dll_poll_ck_out_en()
423 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
424 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
439 struct mmc_host *mmc = host->mmc; in msm_config_cm_dll_phase()
444 return -EINVAL; in msm_config_cm_dll_phase()
446 spin_lock_irqsave(&host->lock, flags); in msm_config_cm_dll_phase()
448 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
451 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
462 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
465 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
467 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
469 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
476 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
479 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
486 spin_unlock_irqrestore(&host->lock, flags); in msm_config_cm_dll_phase()
493 * setting for SD3.0 UHS-I card read operation (in SDR104
509 struct mmc_host *mmc = host->mmc; in msm_find_most_appropriate_phase()
514 return -EINVAL; in msm_find_most_appropriate_phase()
532 return -EINVAL; in msm_find_most_appropriate_phase()
534 /* Check if phase-0 is present in first valid window? */ in msm_find_most_appropriate_phase()
565 return -EINVAL; in msm_find_most_appropriate_phase()
589 i--; in msm_find_most_appropriate_phase()
594 ret = -EINVAL; in msm_find_most_appropriate_phase()
609 if (host->clock <= 112000000) in msm_cm_dll_set_freq()
611 else if (host->clock <= 125000000) in msm_cm_dll_set_freq()
613 else if (host->clock <= 137000000) in msm_cm_dll_set_freq()
615 else if (host->clock <= 150000000) in msm_cm_dll_set_freq()
617 else if (host->clock <= 162000000) in msm_cm_dll_set_freq()
619 else if (host->clock <= 175000000) in msm_cm_dll_set_freq()
621 else if (host->clock <= 187000000) in msm_cm_dll_set_freq()
623 else if (host->clock <= 200000000) in msm_cm_dll_set_freq()
626 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
629 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
635 struct mmc_host *mmc = host->mmc; in msm_init_cm_dll()
642 msm_host->offset; in msm_init_cm_dll()
644 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) in msm_init_cm_dll()
645 xo_clk = clk_get_rate(msm_host->xo_clk); in msm_init_cm_dll()
647 spin_lock_irqsave(&host->lock, flags); in msm_init_cm_dll()
654 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
656 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
658 if (msm_host->dll_config) in msm_init_cm_dll()
659 writel_relaxed(msm_host->dll_config, in msm_init_cm_dll()
660 host->ioaddr + msm_offset->core_dll_config); in msm_init_cm_dll()
662 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
663 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
664 msm_offset->core_dll_config); in msm_init_cm_dll()
666 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
667 msm_offset->core_dll_config); in msm_init_cm_dll()
669 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
670 msm_offset->core_dll_config_2); in msm_init_cm_dll()
672 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
673 msm_offset->core_dll_config_2); in msm_init_cm_dll()
676 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
677 msm_offset->core_dll_config); in msm_init_cm_dll()
679 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
680 msm_offset->core_dll_config); in msm_init_cm_dll()
682 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
683 msm_offset->core_dll_config); in msm_init_cm_dll()
685 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
686 msm_offset->core_dll_config); in msm_init_cm_dll()
688 if (!msm_host->dll_config) in msm_init_cm_dll()
691 if (msm_host->use_14lpp_dll_reset && in msm_init_cm_dll()
692 !IS_ERR_OR_NULL(msm_host->xo_clk)) { in msm_init_cm_dll()
695 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
696 msm_offset->core_dll_config_2); in msm_init_cm_dll()
699 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), in msm_init_cm_dll()
702 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), in msm_init_cm_dll()
705 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
706 msm_offset->core_dll_config_2); in msm_init_cm_dll()
710 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
711 msm_offset->core_dll_config_2); in msm_init_cm_dll()
716 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
717 msm_offset->core_dll_config); in msm_init_cm_dll()
719 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
720 msm_offset->core_dll_config); in msm_init_cm_dll()
722 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
723 msm_offset->core_dll_config); in msm_init_cm_dll()
725 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
726 msm_offset->core_dll_config); in msm_init_cm_dll()
728 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
729 if (!msm_host->dll_config) in msm_init_cm_dll()
731 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
732 msm_offset->core_dll_config_2); in msm_init_cm_dll()
734 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
735 msm_offset->core_dll_config_2); in msm_init_cm_dll()
742 if (msm_host->uses_tassadar_dll) { in msm_init_cm_dll()
745 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
746 msm_offset->core_dll_usr_ctl); in msm_init_cm_dll()
748 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
749 msm_offset->core_dll_config_3); in msm_init_cm_dll()
751 if (msm_host->clk_rate < 150000000) in msm_init_cm_dll()
755 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
756 msm_offset->core_dll_config_3); in msm_init_cm_dll()
759 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
760 msm_offset->core_dll_config); in msm_init_cm_dll()
762 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
763 msm_offset->core_dll_config); in msm_init_cm_dll()
765 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
766 msm_offset->core_dll_config); in msm_init_cm_dll()
768 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
769 msm_offset->core_dll_config); in msm_init_cm_dll()
772 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & in msm_init_cm_dll()
775 if (--wait_cnt == 0) { in msm_init_cm_dll()
778 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
779 return -ETIMEDOUT; in msm_init_cm_dll()
784 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
794 msm_host->offset; in msm_hc_select_default()
796 if (!msm_host->use_cdclp533) { in msm_hc_select_default()
797 config = readl_relaxed(host->ioaddr + in msm_hc_select_default()
798 msm_offset->core_vendor_spec3); in msm_hc_select_default()
800 writel_relaxed(config, host->ioaddr + in msm_hc_select_default()
801 msm_offset->core_vendor_spec3); in msm_hc_select_default()
804 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
807 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
816 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
819 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
832 struct mmc_ios ios = host->mmc->ios; in msm_hc_select_hs400()
836 msm_host->offset; in msm_hc_select_hs400()
839 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
843 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
848 if ((msm_host->tuning_done || ios.enhanced_strobe) && in msm_hc_select_hs400()
849 !msm_host->calibration_done) { in msm_hc_select_hs400()
850 config = readl_relaxed(host->ioaddr + in msm_hc_select_hs400()
851 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
854 writel_relaxed(config, host->ioaddr + in msm_hc_select_hs400()
855 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
857 if (!msm_host->clk_rate && !msm_host->use_cdclp533) { in msm_hc_select_hs400()
863 rc = readl_relaxed_poll_timeout(host->ioaddr + in msm_hc_select_hs400()
864 msm_offset->core_dll_status, in msm_hc_select_hs400()
870 if (rc == -ETIMEDOUT) in msm_hc_select_hs400()
872 mmc_hostname(host->mmc), dll_lock); in msm_hc_select_hs400()
882 * sdhci_msm_hc_select_mode :- In general all timing modes are
887 * HS200 - SDR104 (Since they both are equivalent in functionality)
888 * HS400 - This involves multiple configurations
889 * Initially SDR104 - when tuning is required as HS200
896 * HS400 - divided clock (free running MCLK/2)
897 * All other modes - default (free running MCLK)
901 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_hc_select_mode()
904 host->flags & SDHCI_HS400_TUNING) in sdhci_msm_hc_select_mode()
917 msm_host->offset; in sdhci_msm_cdclp533_calibration()
919 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
930 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_cdclp533_calibration()
934 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
936 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
938 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
940 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
942 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
944 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
946 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
948 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
950 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
952 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
956 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
957 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); in sdhci_msm_cdclp533_calibration()
958 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
959 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); in sdhci_msm_cdclp533_calibration()
960 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); in sdhci_msm_cdclp533_calibration()
961 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); in sdhci_msm_cdclp533_calibration()
962 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); in sdhci_msm_cdclp533_calibration()
963 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); in sdhci_msm_cdclp533_calibration()
964 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); in sdhci_msm_cdclp533_calibration()
968 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
970 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
972 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
974 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
976 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
978 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
980 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
982 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
984 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, in sdhci_msm_cdclp533_calibration()
989 if (ret == -ETIMEDOUT) { in sdhci_msm_cdclp533_calibration()
991 mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
995 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) in sdhci_msm_cdclp533_calibration()
999 mmc_hostname(host->mmc), __func__, ret); in sdhci_msm_cdclp533_calibration()
1000 ret = -EINVAL; in sdhci_msm_cdclp533_calibration()
1004 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
1006 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
1008 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cdclp533_calibration()
1015 struct mmc_host *mmc = host->mmc; in sdhci_msm_cm_dll_sdc4_calibration()
1023 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1032 if (msm_host->updated_ddr_cfg) in sdhci_msm_cm_dll_sdc4_calibration()
1033 ddr_cfg_offset = msm_offset->core_ddr_config; in sdhci_msm_cm_dll_sdc4_calibration()
1035 ddr_cfg_offset = msm_offset->core_ddr_config_old; in sdhci_msm_cm_dll_sdc4_calibration()
1036 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); in sdhci_msm_cm_dll_sdc4_calibration()
1038 if (mmc->ios.enhanced_strobe) { in sdhci_msm_cm_dll_sdc4_calibration()
1039 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1040 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1042 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1043 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1046 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1048 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1050 ret = readl_relaxed_poll_timeout(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1051 msm_offset->core_dll_status, in sdhci_msm_cm_dll_sdc4_calibration()
1056 if (ret == -ETIMEDOUT) { in sdhci_msm_cm_dll_sdc4_calibration()
1058 mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1065 * and MCLK must be switched on for at-least 1us before DATA in sdhci_msm_cm_dll_sdc4_calibration()
1070 if (!msm_host->use_14lpp_dll_reset) { in sdhci_msm_cm_dll_sdc4_calibration()
1071 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1072 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1074 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1075 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1084 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cm_dll_sdc4_calibration()
1093 struct mmc_host *mmc = host->mmc; in sdhci_msm_hs400_dll_calibration()
1097 msm_host->offset; in sdhci_msm_hs400_dll_calibration()
1099 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_hs400_dll_calibration()
1109 if (!mmc->ios.enhanced_strobe) { in sdhci_msm_hs400_dll_calibration()
1112 msm_host->saved_tuning_phase); in sdhci_msm_hs400_dll_calibration()
1115 config = readl_relaxed(host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1116 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1118 writel_relaxed(config, host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1119 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1122 if (msm_host->use_cdclp533) in sdhci_msm_hs400_dll_calibration()
1127 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_hs400_dll_calibration()
1134 struct mmc_ios *ios = &host->mmc->ios; in sdhci_msm_is_tuning_needed()
1140 if (host->clock <= CORE_FREQ_100MHZ || in sdhci_msm_is_tuning_needed()
1141 !(ios->timing == MMC_TIMING_MMC_HS400 || in sdhci_msm_is_tuning_needed()
1142 ios->timing == MMC_TIMING_MMC_HS200 || in sdhci_msm_is_tuning_needed()
1143 ios->timing == MMC_TIMING_UHS_SDR104) || in sdhci_msm_is_tuning_needed()
1144 ios->enhanced_strobe) in sdhci_msm_is_tuning_needed()
1169 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_restore_sdr_dll_config()
1177 u32 config, oldconfig = readl_relaxed(host->ioaddr + in sdhci_msm_set_cdr()
1178 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1190 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_cdr()
1191 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1201 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_execute_tuning()
1206 msm_host->use_cdr = false; in sdhci_msm_execute_tuning()
1211 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ in sdhci_msm_execute_tuning()
1212 msm_host->use_cdr = true; in sdhci_msm_execute_tuning()
1218 msm_host->tuning_done = 0; in sdhci_msm_execute_tuning()
1222 * - select MCLK/2 in VENDOR_SPEC in sdhci_msm_execute_tuning()
1223 * - program MCLK to 400MHz (or nearest supported) in GCC in sdhci_msm_execute_tuning()
1225 if (host->flags & SDHCI_HS400_TUNING) { in sdhci_msm_execute_tuning()
1228 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_msm_execute_tuning()
1264 if (--tuning_seq_cnt) { in sdhci_msm_execute_tuning()
1284 msm_host->saved_tuning_phase = phase; in sdhci_msm_execute_tuning()
1288 if (--tuning_seq_cnt) in sdhci_msm_execute_tuning()
1293 rc = -EIO; in sdhci_msm_execute_tuning()
1297 msm_host->tuning_done = true; in sdhci_msm_execute_tuning()
1302 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1313 if (host->clock > CORE_FREQ_100MHZ && in sdhci_msm_hs400()
1314 (msm_host->tuning_done || ios->enhanced_strobe) && in sdhci_msm_hs400()
1315 !msm_host->calibration_done) { in sdhci_msm_hs400()
1318 msm_host->calibration_done = true; in sdhci_msm_hs400()
1321 mmc_hostname(host->mmc), ret); in sdhci_msm_hs400()
1328 struct mmc_host *mmc = host->mmc; in sdhci_msm_set_uhs_signaling()
1334 msm_host->offset; in sdhci_msm_set_uhs_signaling()
1366 if (host->clock <= CORE_FREQ_100MHZ) { in sdhci_msm_set_uhs_signaling()
1375 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1376 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1378 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1379 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1381 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1382 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1384 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1385 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1391 msm_host->calibration_done = false; in sdhci_msm_set_uhs_signaling()
1395 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); in sdhci_msm_set_uhs_signaling()
1398 if (mmc->ios.timing == MMC_TIMING_MMC_HS400) in sdhci_msm_set_uhs_signaling()
1399 sdhci_msm_hs400(host, &mmc->ios); in sdhci_msm_set_uhs_signaling()
1404 struct platform_device *pdev = msm_host->pdev; in sdhci_msm_set_pincfg()
1408 ret = pinctrl_pm_select_default_state(&pdev->dev); in sdhci_msm_set_pincfg()
1410 ret = pinctrl_pm_select_sleep_state(&pdev->dev); in sdhci_msm_set_pincfg()
1421 else if (!mmc->card) in msm_config_vmmc_regulator()
1423 else if (mmc_card_mmc(mmc->card)) in msm_config_vmmc_regulator()
1425 else if (mmc_card_sd(mmc->card)) in msm_config_vmmc_regulator()
1430 regulator_set_load(mmc->supply.vmmc, load); in msm_config_vmmc_regulator()
1439 else if (!mmc->card) in msm_config_vqmmc_regulator()
1441 else if (mmc_card_sd(mmc->card)) in msm_config_vqmmc_regulator()
1446 regulator_set_load(mmc->supply.vqmmc, load); in msm_config_vqmmc_regulator()
1452 if (IS_ERR(mmc->supply.vmmc)) in sdhci_msm_set_vmmc()
1457 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); in sdhci_msm_set_vmmc()
1466 if (msm_host->vqmmc_enabled == level) in msm_toggle_vqmmc()
1473 if (msm_host->caps_0 & CORE_3_0V_SUPPORT) in msm_toggle_vqmmc()
1475 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) in msm_toggle_vqmmc()
1478 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in msm_toggle_vqmmc()
1486 ret = regulator_enable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1488 ret = regulator_disable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1495 msm_host->vqmmc_enabled = level; in msm_toggle_vqmmc()
1506 ret = regulator_set_load(mmc->supply.vqmmc, load); in msm_config_vqmmc_mode()
1519 if (IS_ERR(mmc->supply.vqmmc) || in sdhci_msm_set_vqmmc()
1520 (mmc->ios.power_mode == MMC_POWER_UNDEFINED)) in sdhci_msm_set_vqmmc()
1533 mmc->card && mmc_card_mmc(mmc->card); in sdhci_msm_set_vqmmc()
1545 init_waitqueue_head(&msm_host->pwr_irq_wait); in sdhci_msm_init_pwr_irq_wait()
1551 wake_up(&msm_host->pwr_irq_wait); in sdhci_msm_complete_pwr_irq_wait()
1567 struct mmc_host *mmc = host->mmc; in sdhci_msm_check_power_status()
1571 msm_host->offset; in sdhci_msm_check_power_status()
1574 mmc_hostname(host->mmc), __func__, req_type, in sdhci_msm_check_power_status()
1575 msm_host->curr_pwr_state, msm_host->curr_io_level); in sdhci_msm_check_power_status()
1580 * Since sdhci-msm-v5, this bit has been removed and SW must consider in sdhci_msm_check_power_status()
1583 if (!msm_host->mci_removed) in sdhci_msm_check_power_status()
1585 msm_offset->core_generics); in sdhci_msm_check_power_status()
1592 * The IRQ for request type IO High/LOW will be generated when - in sdhci_msm_check_power_status()
1600 * for host->pwr to handle a case where IO voltage high request is in sdhci_msm_check_power_status()
1603 if ((req_type & REQ_IO_HIGH) && !host->pwr) { in sdhci_msm_check_power_status()
1605 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1608 if ((req_type & msm_host->curr_pwr_state) || in sdhci_msm_check_power_status()
1609 (req_type & msm_host->curr_io_level)) in sdhci_msm_check_power_status()
1618 if (!wait_event_timeout(msm_host->pwr_irq_wait, in sdhci_msm_check_power_status()
1619 msm_host->pwr_irq_flag, in sdhci_msm_check_power_status()
1621 dev_warn(&msm_host->pdev->dev, in sdhci_msm_check_power_status()
1623 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1626 if ((req_type & REQ_BUS_ON) && mmc->card && !mmc->ops->get_cd(mmc)) { in sdhci_msm_check_power_status()
1628 host->pwr = 0; in sdhci_msm_check_power_status()
1631 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), in sdhci_msm_check_power_status()
1640 msm_host->offset; in sdhci_msm_dump_pwr_ctrl_regs()
1643 mmc_hostname(host->mmc), in sdhci_msm_dump_pwr_ctrl_regs()
1644 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), in sdhci_msm_dump_pwr_ctrl_regs()
1645 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), in sdhci_msm_dump_pwr_ctrl_regs()
1646 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); in sdhci_msm_dump_pwr_ctrl_regs()
1653 struct mmc_host *mmc = host->mmc; in sdhci_msm_handle_pwr_irq()
1658 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_handle_pwr_irq()
1661 msm_offset->core_pwrctl_status); in sdhci_msm_handle_pwr_irq()
1665 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1675 msm_offset->core_pwrctl_status)) { in sdhci_msm_handle_pwr_irq()
1678 mmc_hostname(host->mmc), irq_status); in sdhci_msm_handle_pwr_irq()
1684 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1685 retry--; in sdhci_msm_handle_pwr_irq()
1689 if ((irq_status & CORE_PWRCTL_BUS_ON) && mmc->card && in sdhci_msm_handle_pwr_irq()
1690 !mmc->ops->get_cd(mmc)) { in sdhci_msm_handle_pwr_irq()
1692 msm_offset->core_pwrctl_ctl); in sdhci_msm_handle_pwr_irq()
1731 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { in sdhci_msm_handle_pwr_irq()
1732 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); in sdhci_msm_handle_pwr_irq()
1736 mmc->ios.signal_voltage, mmc->ios.vdd, in sdhci_msm_handle_pwr_irq()
1748 msm_offset->core_pwrctl_ctl); in sdhci_msm_handle_pwr_irq()
1754 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in sdhci_msm_handle_pwr_irq()
1767 config = readl_relaxed(host->ioaddr + in sdhci_msm_handle_pwr_irq()
1768 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1772 (msm_host->caps_0 & CORE_3_0V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1775 (msm_host->caps_0 & CORE_1_8V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1779 writel_relaxed(new_config, host->ioaddr + in sdhci_msm_handle_pwr_irq()
1780 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1784 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
1786 msm_host->curr_io_level = io_level; in sdhci_msm_handle_pwr_irq()
1789 mmc_hostname(msm_host->mmc), __func__, irq, irq_status, in sdhci_msm_handle_pwr_irq()
1800 msm_host->pwr_irq_flag = 1; in sdhci_msm_pwr_irq()
1811 struct clk *core_clk = msm_host->bulk_clks[0].clk; in sdhci_msm_get_max_clock()
1822 * __sdhci_msm_set_clock - sdhci_msm clock control.
1847 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1854 host->mmc->actual_clock = msm_host->clk_rate = 0; in sdhci_msm_set_clock()
1878 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_ice_init()
1879 struct blk_crypto_profile *profile = &mmc->crypto_profile; in sdhci_msm_ice_init()
1891 if (ice == ERR_PTR(-EOPNOTSUPP)) { in sdhci_msm_ice_init()
1904 msm_host->ice = ice; in sdhci_msm_ice_init()
1915 profile->ll_ops = sdhci_msm_crypto_ops; in sdhci_msm_ice_init()
1916 profile->max_dun_bytes_supported = 4; in sdhci_msm_ice_init()
1917 profile->key_types_supported = BLK_CRYPTO_KEY_TYPE_RAW; in sdhci_msm_ice_init()
1918 profile->dev = dev; in sdhci_msm_ice_init()
1921 * Currently this driver only supports AES-256-XTS. All known versions in sdhci_msm_ice_init()
1932 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= in sdhci_msm_ice_init()
1936 mmc->caps2 |= MMC_CAP2_CRYPTO; in sdhci_msm_ice_init()
1942 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) in sdhci_msm_ice_enable()
1943 qcom_ice_enable(msm_host->ice); in sdhci_msm_ice_enable()
1948 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) in sdhci_msm_ice_resume()
1949 return qcom_ice_resume(msm_host->ice); in sdhci_msm_ice_resume()
1956 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) in sdhci_msm_ice_suspend()
1957 return qcom_ice_suspend(msm_host->ice); in sdhci_msm_ice_suspend()
1974 * Program a key into a QC ICE keyslot. QC ICE requires a QC-specific SCM call
1984 return qcom_ice_program_key(msm_host->ice, slot, key); in sdhci_msm_ice_keyslot_program()
1994 return qcom_ice_evict_key(msm_host->ice, slot); in sdhci_msm_ice_keyslot_evict()
2029 * MSM Command Queue Engine (CQE) *
2041 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_msm_cqe_irq()
2062 * When CQE is halted, the legacy SDHCI path operates only in sdhci_msm_cqe_disable()
2063 * on 16-byte descriptors in 64bit mode. in sdhci_msm_cqe_disable()
2065 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_disable()
2066 host->desc_sz = 16; in sdhci_msm_cqe_disable()
2068 spin_lock_irqsave(&host->lock, flags); in sdhci_msm_cqe_disable()
2071 * During CQE command transfers, command complete bit gets latched. in sdhci_msm_cqe_disable()
2072 * So s/w should clear command complete interrupt status when CQE is in sdhci_msm_cqe_disable()
2074 * interrupt gets triggered when CQE is halted/disabled. in sdhci_msm_cqe_disable()
2081 spin_unlock_irqrestore(&host->lock, flags); in sdhci_msm_cqe_disable()
2095 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock. in sdhci_msm_set_timeout()
2097 if (cmd && cmd->data && host->clock > 400000 && in sdhci_msm_set_timeout()
2098 host->clock <= 50000000 && in sdhci_msm_set_timeout()
2099 ((1 << (count + start)) > (10 * host->clock))) in sdhci_msm_set_timeout()
2100 host->data_timeout = 22LL * NSEC_PER_SEC; in sdhci_msm_set_timeout()
2122 * When CQE is halted, SDHC operates only on 16byte ADMA descriptors. in sdhci_msm_cqe_add_host()
2125 if (host->caps & SDHCI_CAN_64BIT) in sdhci_msm_cqe_add_host()
2126 host->alloc_desc_sz = 16; in sdhci_msm_cqe_add_host()
2135 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret); in sdhci_msm_cqe_add_host()
2139 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_msm_cqe_add_host()
2140 cq_host->ops = &sdhci_msm_cqhci_ops; in sdhci_msm_cqe_add_host()
2142 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_msm_cqe_add_host()
2148 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_msm_cqe_add_host()
2150 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n", in sdhci_msm_cqe_add_host()
2151 mmc_hostname(host->mmc), ret); in sdhci_msm_cqe_add_host()
2155 /* Disable cqe reset due to cqe enable signal */ in sdhci_msm_cqe_add_host()
2161 * SDHC expects 12byte ADMA descriptors till CQE is enabled. in sdhci_msm_cqe_add_host()
2163 * during card initialization (before CQE gets enabled) would in sdhci_msm_cqe_add_host()
2166 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_add_host()
2167 host->desc_sz = 12; in sdhci_msm_cqe_add_host()
2173 dev_info(&pdev->dev, "%s: CQE init: success\n", in sdhci_msm_cqe_add_host()
2174 mmc_hostname(host->mmc)); in sdhci_msm_cqe_add_host()
2201 if (host->pwr && (val & SDHCI_RESET_ALL)) in __sdhci_msm_check_write()
2208 msm_host->transfer_mode = val; in __sdhci_msm_check_write()
2211 if (!msm_host->use_cdr) in __sdhci_msm_check_write()
2213 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && in __sdhci_msm_check_write()
2222 msm_host->pwr_irq_flag = 0; in __sdhci_msm_check_write()
2238 writew_relaxed(val, host->ioaddr + reg); in sdhci_msm_writew()
2251 writeb_relaxed(val, host->ioaddr + reg); in sdhci_msm_writeb()
2259 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_set_regulator_caps()
2260 struct regulator *supply = mmc->supply.vqmmc; in sdhci_msm_set_regulator_caps()
2263 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_set_regulator_caps()
2265 if (!IS_ERR(mmc->supply.vqmmc)) { in sdhci_msm_set_regulator_caps()
2281 u32 io_level = msm_host->curr_io_level; in sdhci_msm_set_regulator_caps()
2283 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_regulator_caps()
2284 msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2293 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2295 msm_host->caps_0 |= caps; in sdhci_msm_set_regulator_caps()
2303 ret = mmc_regulator_get_supply(msm_host->mmc); in sdhci_msm_register_vreg()
2322 if (host->version < SDHCI_SPEC_300) in sdhci_msm_start_signal_voltage_switch()
2327 switch (ios->signal_voltage) { in sdhci_msm_start_signal_voltage_switch()
2329 if (!(host->flags & SDHCI_SIGNALING_330)) in sdhci_msm_start_signal_voltage_switch()
2330 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2336 if (!(host->flags & SDHCI_SIGNALING_180)) in sdhci_msm_start_signal_voltage_switch()
2337 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2344 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2361 return -EAGAIN; in sdhci_msm_start_signal_voltage_switch()
2366 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2372 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_dump_vendor_regs()
2374 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n"); in sdhci_msm_dump_vendor_regs()
2378 readl_relaxed(host->ioaddr + msm_offset->core_dll_status), in sdhci_msm_dump_vendor_regs()
2379 readl_relaxed(host->ioaddr + msm_offset->core_dll_config), in sdhci_msm_dump_vendor_regs()
2380 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2)); in sdhci_msm_dump_vendor_regs()
2383 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3), in sdhci_msm_dump_vendor_regs()
2384 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl), in sdhci_msm_dump_vendor_regs()
2385 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config)); in sdhci_msm_dump_vendor_regs()
2388 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec), in sdhci_msm_dump_vendor_regs()
2389 readl_relaxed(host->ioaddr + in sdhci_msm_dump_vendor_regs()
2390 msm_offset->core_vendor_spec_func2), in sdhci_msm_dump_vendor_regs()
2391 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3)); in sdhci_msm_dump_vendor_regs()
2427 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2428 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2429 {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
2430 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2431 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2465 struct device_node *node = pdev->dev.of_node; in sdhci_msm_get_of_property()
2469 if (of_property_read_u32(node, "qcom,ddr-config", in sdhci_msm_get_of_property()
2470 &msm_host->ddr_config)) in sdhci_msm_get_of_property()
2471 msm_host->ddr_config = DDR_CONFIG_POR_VAL; in sdhci_msm_get_of_property()
2473 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); in sdhci_msm_get_of_property()
2475 if (of_device_is_compatible(node, "qcom,msm8916-sdhci")) in sdhci_msm_get_of_property()
2476 host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA; in sdhci_msm_get_of_property()
2500 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in sdhci_msm_gcc_reset()
2529 struct device_node *node = pdev->dev.of_node; in sdhci_msm_probe()
2535 host->sdma_boundary = 0; in sdhci_msm_probe()
2538 msm_host->mmc = host->mmc; in sdhci_msm_probe()
2539 msm_host->pdev = pdev; in sdhci_msm_probe()
2541 ret = mmc_of_parse(host->mmc); in sdhci_msm_probe()
2549 var_info = of_device_get_match_data(&pdev->dev); in sdhci_msm_probe()
2551 msm_host->mci_removed = var_info->mci_removed; in sdhci_msm_probe()
2552 msm_host->restore_dll_config = var_info->restore_dll_config; in sdhci_msm_probe()
2553 msm_host->var_ops = var_info->var_ops; in sdhci_msm_probe()
2554 msm_host->offset = var_info->offset; in sdhci_msm_probe()
2556 msm_offset = msm_host->offset; in sdhci_msm_probe()
2561 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; in sdhci_msm_probe()
2563 ret = sdhci_msm_gcc_reset(&pdev->dev, host); in sdhci_msm_probe()
2568 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); in sdhci_msm_probe()
2569 if (!IS_ERR(msm_host->bus_clk)) { in sdhci_msm_probe()
2571 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); in sdhci_msm_probe()
2574 ret = clk_prepare_enable(msm_host->bus_clk); in sdhci_msm_probe()
2580 clk = devm_clk_get(&pdev->dev, "iface"); in sdhci_msm_probe()
2583 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2586 msm_host->bulk_clks[1].clk = clk; in sdhci_msm_probe()
2589 clk = devm_clk_get(&pdev->dev, "core"); in sdhci_msm_probe()
2592 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2595 msm_host->bulk_clks[0].clk = clk; in sdhci_msm_probe()
2598 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); in sdhci_msm_probe()
2602 ret = devm_pm_opp_set_clkname(&pdev->dev, "core"); in sdhci_msm_probe()
2607 ret = devm_pm_opp_of_add_table(&pdev->dev); in sdhci_msm_probe()
2608 if (ret && ret != -ENODEV) { in sdhci_msm_probe()
2609 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); in sdhci_msm_probe()
2614 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX); in sdhci_msm_probe()
2616 dev_warn(&pdev->dev, "core clock boost failed\n"); in sdhci_msm_probe()
2618 clk = devm_clk_get(&pdev->dev, "cal"); in sdhci_msm_probe()
2621 msm_host->bulk_clks[2].clk = clk; in sdhci_msm_probe()
2623 clk = devm_clk_get(&pdev->dev, "sleep"); in sdhci_msm_probe()
2626 msm_host->bulk_clks[3].clk = clk; in sdhci_msm_probe()
2628 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2629 msm_host->bulk_clks); in sdhci_msm_probe()
2637 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); in sdhci_msm_probe()
2638 if (IS_ERR(msm_host->xo_clk)) { in sdhci_msm_probe()
2639 ret = PTR_ERR(msm_host->xo_clk); in sdhci_msm_probe()
2640 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); in sdhci_msm_probe()
2643 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2644 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); in sdhci_msm_probe()
2645 if (IS_ERR(msm_host->core_mem)) { in sdhci_msm_probe()
2646 ret = PTR_ERR(msm_host->core_mem); in sdhci_msm_probe()
2653 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_probe()
2655 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2658 msm_offset->core_hc_mode); in sdhci_msm_probe()
2660 msm_offset->core_hc_mode); in sdhci_msm_probe()
2663 msm_offset->core_hc_mode); in sdhci_msm_probe()
2666 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); in sdhci_msm_probe()
2667 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", in sdhci_msm_probe()
2672 msm_offset->core_mci_version); in sdhci_msm_probe()
2676 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", in sdhci_msm_probe()
2680 msm_host->use_14lpp_dll_reset = true; in sdhci_msm_probe()
2687 msm_host->use_cdclp533 = true; in sdhci_msm_probe()
2694 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); in sdhci_msm_probe()
2696 writel_relaxed(config, host->ioaddr + in sdhci_msm_probe()
2697 msm_offset->core_vendor_spec_capabilities0); in sdhci_msm_probe()
2701 msm_host->updated_ddr_cfg = true; in sdhci_msm_probe()
2704 msm_host->uses_tassadar_dll = true; in sdhci_msm_probe()
2726 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); in sdhci_msm_probe()
2727 if (msm_host->pwr_irq < 0) { in sdhci_msm_probe()
2728 ret = msm_host->pwr_irq; in sdhci_msm_probe()
2735 msm_offset->core_pwrctl_mask); in sdhci_msm_probe()
2737 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, in sdhci_msm_probe()
2739 dev_name(&pdev->dev), host); in sdhci_msm_probe()
2741 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); in sdhci_msm_probe()
2745 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_msm_probe()
2748 host->max_timeout_count = 0xF; in sdhci_msm_probe()
2750 pm_runtime_get_noresume(&pdev->dev); in sdhci_msm_probe()
2751 pm_runtime_set_active(&pdev->dev); in sdhci_msm_probe()
2752 pm_runtime_enable(&pdev->dev); in sdhci_msm_probe()
2753 pm_runtime_set_autosuspend_delay(&pdev->dev, in sdhci_msm_probe()
2755 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_msm_probe()
2757 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_msm_probe()
2759 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; in sdhci_msm_probe()
2760 if (of_property_read_bool(node, "supports-cqe")) in sdhci_msm_probe()
2767 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_msm_probe()
2772 pm_runtime_disable(&pdev->dev); in sdhci_msm_probe()
2773 pm_runtime_set_suspended(&pdev->dev); in sdhci_msm_probe()
2774 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_probe()
2776 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2777 msm_host->bulk_clks); in sdhci_msm_probe()
2779 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_probe()
2780 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_probe()
2789 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == in sdhci_msm_remove()
2794 pm_runtime_get_sync(&pdev->dev); in sdhci_msm_remove()
2795 pm_runtime_disable(&pdev->dev); in sdhci_msm_remove()
2796 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_remove()
2798 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_remove()
2799 msm_host->bulk_clks); in sdhci_msm_remove()
2800 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_remove()
2801 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_remove()
2811 spin_lock_irqsave(&host->lock, flags); in sdhci_msm_runtime_suspend()
2812 host->runtime_suspended = true; in sdhci_msm_runtime_suspend()
2813 spin_unlock_irqrestore(&host->lock, flags); in sdhci_msm_runtime_suspend()
2817 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_suspend()
2818 msm_host->bulk_clks); in sdhci_msm_runtime_suspend()
2831 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_resume()
2832 msm_host->bulk_clks); in sdhci_msm_runtime_resume()
2836 * Whenever core-clock is gated dynamically, it's needed to in sdhci_msm_runtime_resume()
2839 if (msm_host->restore_dll_config && msm_host->clk_rate) { in sdhci_msm_runtime_resume()
2845 dev_pm_opp_set_rate(dev, msm_host->clk_rate); in sdhci_msm_runtime_resume()
2851 spin_lock_irqsave(&host->lock, flags); in sdhci_msm_runtime_resume()
2852 host->runtime_suspended = false; in sdhci_msm_runtime_resume()
2853 spin_unlock_irqrestore(&host->lock, flags); in sdhci_msm_runtime_resume()