Lines Matching +full:mt6795 +full:- +full:power
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
11 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
41 /*--------------------------------------------------------------------------*/
43 /*--------------------------------------------------------------------------*/
50 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
90 /*--------------------------------------------------------------------------*/
92 /*--------------------------------------------------------------------------*/
98 /*--------------------------------------------------------------------------*/
100 /*--------------------------------------------------------------------------*/
350 /*--------------------------------------------------------------------------*/
352 /*--------------------------------------------------------------------------*/
495 bool internal_cd; /* Use internal card-detect logic */
670 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
671 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
672 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
673 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
674 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
675 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
676 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
677 { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat},
678 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
679 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
680 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
681 { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
682 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
709 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
717 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
724 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
725 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
727 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
728 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
731 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
732 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
752 return 0xff - (u8) sum; in msdc_dma_calcs()
765 sg = data->sg; in msdc_dma_setup()
767 gpd = dma->gpd; in msdc_dma_setup()
768 bd = dma->bd; in msdc_dma_setup()
771 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
772 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
774 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
775 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
778 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
786 if (host->dev_comp->support_64g) { in msdc_dma_setup()
792 if (host->dev_comp->support_64g) { in msdc_dma_setup()
800 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
810 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
811 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
814 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
815 if (host->dev_comp->support_64g) in msdc_dma_setup()
816 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
817 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
818 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
823 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
824 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
825 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
832 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
835 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
836 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
838 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
848 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
851 clk_ns = 1000000000U / mmc->actual_clock; in msdc_timeout_cal()
852 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
857 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
858 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
861 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
865 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
875 host->timeout_ns = ns; in msdc_set_timeout()
876 host->timeout_clks = clks; in msdc_set_timeout()
879 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
888 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
894 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
895 clk_disable_unprepare(host->crypto_clk); in msdc_gate_clock()
896 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
897 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
898 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
899 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
907 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
908 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
909 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
910 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
911 clk_prepare_enable(host->crypto_clk); in msdc_ungate_clock()
912 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
914 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
918 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
924 if (!host->top_base) in msdc_new_tx_setting()
927 sdr_set_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
929 sdr_set_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
931 sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
934 switch (host->timing) { in msdc_new_tx_setting()
942 sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
949 sdr_set_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
964 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
969 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
970 host->mclk = 0; in msdc_set_mclk()
971 mmc->actual_clock = 0; in msdc_set_mclk()
972 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
976 if (host->timing != timing) in msdc_set_mclk()
981 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
982 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
983 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
984 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
986 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
996 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
998 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
1000 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
1001 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
1006 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
1007 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
1008 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1011 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1013 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
1016 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
1019 sclk = host->src_clk_freq; in msdc_set_mclk()
1022 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
1024 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
1026 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
1027 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
1030 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1032 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
1033 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
1034 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
1038 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
1042 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
1043 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
1044 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1045 mmc->actual_clock = sclk; in msdc_set_mclk()
1046 host->mclk = hz; in msdc_set_mclk()
1047 host->timing = timing; in msdc_set_mclk()
1049 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
1050 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
1056 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
1057 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
1058 if (host->top_base) { in msdc_set_mclk()
1059 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
1060 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
1061 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
1062 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
1064 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
1065 host->base + tune_reg); in msdc_set_mclk()
1068 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
1069 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
1070 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
1071 if (host->top_base) { in msdc_set_mclk()
1072 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
1073 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
1074 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
1075 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
1077 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
1078 host->base + tune_reg); in msdc_set_mclk()
1083 host->dev_comp->hs400_tune) in msdc_set_mclk()
1084 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
1086 host->hs400_cmd_int_delay); in msdc_set_mclk()
1087 if (host->dev_comp->support_new_tx && timing_changed) in msdc_set_mclk()
1090 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1130 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
1134 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1136 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
1148 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
1149 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1152 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1153 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1157 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1158 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1160 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1165 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1167 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1168 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1169 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1170 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1172 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1182 WARN_ON(host->data); in msdc_start_data()
1183 host->data = data; in msdc_start_data()
1184 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1186 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1187 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1188 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1189 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1190 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1191 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1192 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1198 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1200 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1203 cmd->error = 0; in msdc_auto_cmd_done()
1207 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1208 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1210 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1211 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1213 dev_err(host->dev, in msdc_auto_cmd_done()
1215 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1217 return cmd->error; in msdc_auto_cmd_done()
1221 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1232 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1233 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1235 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1236 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1248 if (host->error && in msdc_track_cmd_data()
1249 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) || in msdc_track_cmd_data()
1250 cmd->error == -ETIMEDOUT)) in msdc_track_cmd_data()
1251 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1252 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1265 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1275 * Note that non-HSQ requests will still be happening at times, even in msdc_request_done()
1276 * though it is enabled, and that's what is going to reset host->mrq. in msdc_request_done()
1281 hsq_req_done = host->hsq_en ? mmc_hsq_finalize_request(mmc, mrq) : false; in msdc_request_done()
1283 if (host->error) in msdc_request_done()
1288 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1289 host->mrq = NULL; in msdc_request_done()
1290 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1292 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1293 if (mrq->data) in msdc_request_done()
1294 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1295 if (host->error) in msdc_request_done()
1298 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1311 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1314 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1316 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1323 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1324 done = !host->cmd; in msdc_cmd_done()
1325 host->cmd = NULL; in msdc_cmd_done()
1326 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1330 rsp = cmd->resp; in msdc_cmd_done()
1332 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1334 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1335 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1336 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1337 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1338 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1339 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1341 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1346 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) || in msdc_cmd_done()
1347 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) in msdc_cmd_done()
1355 cmd->error = -EILSEQ; in msdc_cmd_done()
1356 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1358 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1359 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1362 if (cmd->error) in msdc_cmd_done()
1363 dev_dbg(host->dev, in msdc_cmd_done()
1365 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1366 cmd->error); in msdc_cmd_done()
1383 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1386 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1387 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1392 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1394 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1397 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1398 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1412 WARN_ON(host->cmd); in msdc_start_command()
1413 host->cmd = cmd; in msdc_start_command()
1415 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1419 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1420 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1421 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1425 cmd->error = 0; in msdc_start_command()
1428 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1429 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1430 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1432 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1433 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1439 if ((cmd->error && !host->hs400_tuning && in msdc_cmd_next()
1440 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1441 mmc_op_tuning(cmd->opcode))) || in msdc_cmd_next()
1442 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1444 else if (cmd == mrq->sbc) in msdc_cmd_next()
1445 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1446 else if (!cmd->data) in msdc_cmd_next()
1449 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1456 host->error = 0; in msdc_ops_request()
1457 WARN_ON(!host->hsq_en && host->mrq); in msdc_ops_request()
1458 host->mrq = mrq; in msdc_ops_request()
1460 if (mrq->data) in msdc_ops_request()
1461 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1467 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1468 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1469 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1471 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1477 struct mmc_data *data = mrq->data; in msdc_pre_req()
1483 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1490 struct mmc_data *data = mrq->data; in msdc_post_req()
1495 if (data->host_cookie) { in msdc_post_req()
1496 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1503 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1504 !mrq->sbc) in msdc_data_xfer_next()
1505 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1523 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1524 done = !host->data; in msdc_data_xfer_done()
1526 host->data = NULL; in msdc_data_xfer_done()
1527 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1531 stop = data->stop; in msdc_data_xfer_done()
1533 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1534 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1535 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1536 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1539 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1542 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1544 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1547 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1549 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1550 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1552 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1553 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1555 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1557 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1558 data->bytes_xfered = 0; in msdc_data_xfer_done()
1561 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1563 data->error = -EILSEQ; in msdc_data_xfer_done()
1565 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1566 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1567 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1568 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1577 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1594 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1595 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1603 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1604 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1605 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1606 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1607 return -EINVAL; in msdc_ops_switch_volt()
1612 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1613 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1618 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1619 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1621 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1629 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1641 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1642 if (host->mrq) { in msdc_request_timeout()
1643 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1644 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1645 if (host->cmd) { in msdc_request_timeout()
1646 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1647 __func__, host->cmd->opcode); in msdc_request_timeout()
1648 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1649 host->cmd); in msdc_request_timeout()
1650 } else if (host->data) { in msdc_request_timeout()
1651 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1652 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1653 host->data->blocks); in msdc_request_timeout()
1654 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1655 host->data); in msdc_request_timeout()
1663 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1664 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1665 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1668 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1669 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1679 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1681 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1683 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1691 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1692 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1695 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1696 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1697 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1699 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1702 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1704 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1708 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1709 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1710 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1712 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1723 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1724 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1726 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1727 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1731 dat_err = -EILSEQ; in msdc_cmdq_irq()
1732 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1734 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1735 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1739 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x", in msdc_cmdq_irq()
1757 spin_lock(&host->lock); in msdc_irq()
1758 events = readl(host->base + MSDC_INT); in msdc_irq()
1759 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1763 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1765 mrq = host->mrq; in msdc_irq()
1766 cmd = host->cmd; in msdc_irq()
1767 data = host->data; in msdc_irq()
1768 spin_unlock(&host->lock); in msdc_irq()
1774 if (host->internal_cd) in msdc_irq()
1782 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1786 writel(events, host->base + MSDC_INT); in msdc_irq()
1791 dev_err(host->dev, in msdc_irq()
1798 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1812 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1815 if (host->reset) { in msdc_init_hw()
1816 reset_control_assert(host->reset); in msdc_init_hw()
1818 reset_control_deassert(host->reset); in msdc_init_hw()
1821 /* New tx/rx enable bit need to be 0->1 for hardware check */ in msdc_init_hw()
1822 if (host->dev_comp->support_new_tx) { in msdc_init_hw()
1823 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_init_hw()
1824 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_init_hw()
1827 if (host->dev_comp->support_new_rx) { in msdc_init_hw()
1828 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_init_hw()
1829 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_init_hw()
1833 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1839 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1840 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1841 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1844 if (host->internal_cd) { in msdc_init_hw()
1845 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1847 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1848 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1849 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1851 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1852 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1853 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1856 if (host->top_base) { in msdc_init_hw()
1857 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1858 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1860 writel(0, host->base + tune_reg); in msdc_init_hw()
1862 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1863 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1864 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1865 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1866 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1867 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1869 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1870 if (host->dev_comp->stop_dly_sel) in msdc_init_hw()
1871 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1873 host->dev_comp->stop_dly_sel); in msdc_init_hw()
1875 if (host->dev_comp->pop_en_cnt) in msdc_init_hw()
1876 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1878 host->dev_comp->pop_en_cnt); in msdc_init_hw()
1880 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1882 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1886 if (host->dev_comp->busy_check) in msdc_init_hw()
1887 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); in msdc_init_hw()
1889 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1890 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1892 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1893 if (host->top_base) in msdc_init_hw()
1894 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1897 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1900 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1902 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1906 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1908 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1912 if (host->dev_comp->support_64g) in msdc_init_hw()
1913 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1915 if (host->dev_comp->data_tune) { in msdc_init_hw()
1916 if (host->top_base) { in msdc_init_hw()
1917 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1919 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1921 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1923 if (host->tuning_step > PAD_DELAY_HALF) { in msdc_init_hw()
1924 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1926 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1930 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1933 if (host->tuning_step > PAD_DELAY_HALF) in msdc_init_hw()
1934 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_init_hw()
1940 if (host->top_base) in msdc_init_hw()
1941 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1944 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1948 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_init_hw()
1949 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1950 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
1951 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1954 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1957 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1958 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1962 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1964 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1965 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1966 if (host->top_base) { in msdc_init_hw()
1967 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1968 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1969 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1970 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1971 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1972 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1973 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1974 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1976 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1977 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1979 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1986 if (host->internal_cd) { in msdc_deinit_hw()
1987 /* Disabled card-detect */ in msdc_deinit_hw()
1988 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1989 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
1993 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
1995 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
1996 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
2002 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
2003 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
2009 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
2010 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
2011 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
2014 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
2015 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2016 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
2018 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
2019 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
2020 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2021 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
2024 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
2025 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
2027 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2037 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
2039 /* Suspend/Resume will do power off/on */ in msdc_ops_set_ios()
2040 switch (ios->power_mode) { in msdc_ops_set_ios()
2042 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
2044 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
2045 ios->vdd); in msdc_ops_set_ios()
2047 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
2053 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
2054 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
2056 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
2058 host->vqmmc_enabled = true; in msdc_ops_set_ios()
2062 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
2063 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
2065 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
2066 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
2067 host->vqmmc_enabled = false; in msdc_ops_set_ios()
2074 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
2075 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
2088 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) { in get_delay_len()
2092 return PAD_DELAY_FULL - start_bit; in get_delay_len()
2103 dev_err(host->dev, "phase error: [map:%016llx]\n", delay); in get_best_delay()
2124 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n", in get_best_delay()
2135 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
2137 if (host->top_base) { in msdc_set_cmd_delay()
2139 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value); in msdc_set_cmd_delay()
2140 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0); in msdc_set_cmd_delay()
2142 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
2143 PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2144 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, in msdc_set_cmd_delay()
2145 value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2149 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value); in msdc_set_cmd_delay()
2150 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2153 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
2154 PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2155 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2156 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2163 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
2165 if (host->top_base) { in msdc_set_data_delay()
2167 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2169 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2172 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2173 PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2174 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2175 PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2179 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value); in msdc_set_data_delay()
2180 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2183 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2184 PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2185 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2186 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2195 if (host->dev_comp->support_new_rx) { in msdc_set_data_sample_edge()
2196 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value); in msdc_set_data_sample_edge()
2197 sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value); in msdc_set_data_sample_edge()
2199 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value); in msdc_set_data_sample_edge()
2200 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value); in msdc_set_data_sample_edge()
2212 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2216 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
2217 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
2218 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2220 host->hs200_cmd_int_delay); in msdc_tune_response()
2222 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2223 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2246 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2247 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2271 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2274 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2279 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2282 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2283 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2289 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2291 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2294 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2295 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2308 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2309 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2311 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2312 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2313 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2315 host->hs200_cmd_int_delay); in hs400_tune_response()
2317 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2318 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2320 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2323 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2341 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2345 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2346 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2357 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2358 host->latch_ck); in msdc_tune_data()
2360 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2373 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2392 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2393 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2408 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2409 host->latch_ck); in msdc_tune_together()
2411 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2413 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2426 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2428 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2440 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2444 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2452 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2453 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2460 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2462 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2464 if (host->hs400_mode) { in msdc_execute_tuning()
2470 if (host->hs400_mode && in msdc_execute_tuning()
2471 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2475 if (ret == -EIO) { in msdc_execute_tuning()
2476 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2479 if (host->hs400_mode == false) { in msdc_execute_tuning()
2481 if (ret == -EIO) in msdc_execute_tuning()
2482 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2486 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2487 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2488 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2489 if (host->top_base) { in msdc_execute_tuning()
2490 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2492 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2501 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2503 if (host->top_base) in msdc_prepare_hs400_tuning()
2504 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2505 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2507 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2509 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2511 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2524 if (host->top_base) { in msdc_execute_hs400_tuning()
2525 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2527 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2528 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2529 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2531 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2532 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2533 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2534 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2537 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2539 if (host->top_base) in msdc_execute_hs400_tuning()
2540 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2543 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2551 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2555 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2558 if (host->top_base) in msdc_execute_hs400_tuning()
2559 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2562 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2565 if (host->top_base) in msdc_execute_hs400_tuning()
2566 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2568 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2570 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2575 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2576 return -EIO; in msdc_execute_hs400_tuning()
2583 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2585 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2593 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2595 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2603 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2606 if (!host->internal_cd) in msdc_get_cd()
2609 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2610 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2621 if (ios->enhanced_strobe) { in msdc_hs400_enhanced_strobe()
2623 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2624 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2625 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2627 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2628 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2629 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2631 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2632 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2633 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2635 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2636 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2637 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2644 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_cit_cal()
2653 hclk_freq = (u64)clk_get_rate(host->h_clk); in msdc_cqe_cit_cal()
2671 host->cq_ssc1_time = 0x40; in msdc_cqe_cit_cal()
2677 host->cq_ssc1_time = value; in msdc_cqe_cit_cal()
2683 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_enable()
2686 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2688 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2695 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); in msdc_cqe_enable()
2704 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2706 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2708 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2709 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2712 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2714 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2717 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2726 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2736 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2774 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2775 &host->latch_ck); in msdc_of_property_parse()
2777 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2778 &host->hs400_ds_delay); in msdc_of_property_parse()
2780 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", in msdc_of_property_parse()
2781 &host->hs400_ds_dly3); in msdc_of_property_parse()
2783 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2784 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2786 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2787 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2789 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2790 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2791 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2793 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2795 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step", in msdc_of_property_parse()
2796 &host->tuning_step)) { in msdc_of_property_parse()
2797 if (mmc->caps2 & MMC_CAP2_NO_MMC) in msdc_of_property_parse()
2798 host->tuning_step = PAD_DELAY_FULL; in msdc_of_property_parse()
2800 host->tuning_step = PAD_DELAY_HALF; in msdc_of_property_parse()
2803 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2804 "supports-cqe")) in msdc_of_property_parse()
2805 host->cqhci = true; in msdc_of_property_parse()
2807 host->cqhci = false; in msdc_of_property_parse()
2815 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2816 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2817 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2819 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2820 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2821 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2823 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2824 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2825 host->bus_clk = NULL; in msdc_of_clock_parse()
2828 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2829 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2830 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2833 * Fallback for legacy device-trees: src_clk and HCLK use the same in msdc_of_clock_parse()
2839 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2840 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2841 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2842 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2846 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2847 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2848 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2850 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2851 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2852 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2853 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, in msdc_of_clock_parse()
2854 host->bulk_clks); in msdc_of_clock_parse()
2856 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); in msdc_of_clock_parse()
2869 if (!pdev->dev.of_node) { in msdc_drv_probe()
2870 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2871 return -EINVAL; in msdc_drv_probe()
2875 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host)); in msdc_drv_probe()
2877 return -ENOMEM; in msdc_drv_probe()
2884 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2885 if (IS_ERR(host->base)) in msdc_drv_probe()
2886 return PTR_ERR(host->base); in msdc_drv_probe()
2888 host->top_base = devm_platform_ioremap_resource(pdev, 1); in msdc_drv_probe()
2889 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2890 host->top_base = NULL; in msdc_drv_probe()
2900 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2902 if (IS_ERR(host->reset)) in msdc_drv_probe()
2903 return PTR_ERR(host->reset); in msdc_drv_probe()
2906 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { in msdc_drv_probe()
2907 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); in msdc_drv_probe()
2908 if (IS_ERR(host->crypto_clk)) in msdc_drv_probe()
2909 return PTR_ERR(host->crypto_clk); in msdc_drv_probe()
2910 else if (host->crypto_clk) in msdc_drv_probe()
2911 mmc->caps2 |= MMC_CAP2_CRYPTO; in msdc_drv_probe()
2914 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2915 if (host->irq < 0) in msdc_drv_probe()
2916 return host->irq; in msdc_drv_probe()
2918 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2919 if (IS_ERR(host->pinctrl)) in msdc_drv_probe()
2920 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl), in msdc_drv_probe()
2923 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2924 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2925 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
2926 return PTR_ERR(host->pins_default); in msdc_drv_probe()
2929 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2930 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2931 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
2932 return PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2936 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { in msdc_drv_probe()
2937 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); in msdc_drv_probe()
2938 if (host->eint_irq > 0) { in msdc_drv_probe()
2939 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
2940 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
2941 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); in msdc_drv_probe()
2942 host->pins_eint = NULL; in msdc_drv_probe()
2944 device_init_wakeup(&pdev->dev, true); in msdc_drv_probe()
2951 host->dev = &pdev->dev; in msdc_drv_probe()
2952 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2953 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2955 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
2956 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2957 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2959 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2961 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
2963 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2968 host->internal_cd = true; in msdc_drv_probe()
2971 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
2972 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
2974 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
2975 if (host->cqhci) in msdc_drv_probe()
2976 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
2978 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
2979 if (host->dev_comp->support_64g) in msdc_drv_probe()
2980 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
2982 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
2983 mmc->max_blk_size = 2048; in msdc_drv_probe()
2984 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
2985 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
2986 if (host->dev_comp->support_64g) in msdc_drv_probe()
2987 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
2989 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
2990 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
2992 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
2993 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2995 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
2996 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2998 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
2999 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
3000 ret = -ENOMEM; in msdc_drv_probe()
3003 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
3004 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
3005 spin_lock_init(&host->lock); in msdc_drv_probe()
3010 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); in msdc_drv_probe()
3015 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
3016 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
3017 sizeof(*host->cq_host), in msdc_drv_probe()
3019 if (!host->cq_host) { in msdc_drv_probe()
3020 ret = -ENOMEM; in msdc_drv_probe()
3023 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
3024 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
3025 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
3026 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
3029 mmc->max_segs = 128; in msdc_drv_probe()
3031 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
3032 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
3035 } else if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_drv_probe()
3037 struct mmc_hsq *hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); in msdc_drv_probe()
3039 ret = -ENOMEM; in msdc_drv_probe()
3047 host->hsq_en = true; in msdc_drv_probe()
3050 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
3051 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
3055 pm_runtime_set_active(host->dev); in msdc_drv_probe()
3056 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
3057 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
3058 pm_runtime_enable(host->dev); in msdc_drv_probe()
3066 pm_runtime_disable(host->dev); in msdc_drv_probe()
3073 device_init_wakeup(&pdev->dev, false); in msdc_drv_probe()
3074 if (host->dma.gpd) in msdc_drv_probe()
3075 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
3077 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
3078 if (host->dma.bd) in msdc_drv_probe()
3079 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
3081 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
3093 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
3100 pm_runtime_disable(host->dev); in msdc_drv_remove()
3101 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
3102 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
3104 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
3105 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
3106 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
3107 device_init_wakeup(&pdev->dev, false); in msdc_drv_remove()
3112 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
3114 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
3115 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
3116 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
3117 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
3118 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
3119 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
3120 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
3121 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
3122 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
3123 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
3124 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
3125 if (host->top_base) { in msdc_save_reg()
3126 host->save_para.emmc_top_control = in msdc_save_reg()
3127 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
3128 host->save_para.emmc_top_cmd = in msdc_save_reg()
3129 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
3130 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
3131 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
3132 host->save_para.loop_test_control = in msdc_save_reg()
3133 readl(host->top_base + LOOP_TEST_CONTROL); in msdc_save_reg()
3135 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
3142 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
3144 if (host->dev_comp->support_new_tx) { in msdc_restore_reg()
3145 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_restore_reg()
3146 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_restore_reg()
3148 if (host->dev_comp->support_new_rx) { in msdc_restore_reg()
3149 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_restore_reg()
3150 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_restore_reg()
3153 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
3154 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
3155 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
3156 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
3157 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
3158 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
3159 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
3160 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
3161 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
3162 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
3163 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
3164 if (host->top_base) { in msdc_restore_reg()
3165 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
3166 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
3167 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
3168 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
3169 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
3170 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
3171 writel(host->save_para.loop_test_control, in msdc_restore_reg()
3172 host->top_base + LOOP_TEST_CONTROL); in msdc_restore_reg()
3174 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
3186 if (host->hsq_en) in msdc_runtime_suspend()
3192 if (host->pins_eint) { in msdc_runtime_suspend()
3193 disable_irq(host->irq); in msdc_runtime_suspend()
3194 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
3215 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
3216 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
3217 enable_irq(host->irq); in msdc_runtime_resume()
3220 if (host->hsq_en) in msdc_runtime_resume()
3233 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
3237 val = readl(host->base + MSDC_INT); in msdc_suspend()
3238 writel(val, host->base + MSDC_INT); in msdc_suspend()
3242 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will in msdc_suspend()
3245 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
3256 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()
3271 .name = "mtk-msdc",