Lines Matching +full:mt6779 +full:- +full:pinctrl
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
12 #include <linux/dma-mapping.h>
17 #include <linux/pinctrl/consumer.h>
34 #include <linux/mmc/slot-gpio.h>
42 /*--------------------------------------------------------------------------*/
44 /*--------------------------------------------------------------------------*/
51 /*--------------------------------------------------------------------------*/
53 /*--------------------------------------------------------------------------*/
92 /*--------------------------------------------------------------------------*/
94 /*--------------------------------------------------------------------------*/
100 /*--------------------------------------------------------------------------*/
102 /*--------------------------------------------------------------------------*/
371 /*--------------------------------------------------------------------------*/
373 /*--------------------------------------------------------------------------*/
487 struct pinctrl *pinctrl; member
517 bool internal_cd; /* Use internal card-detect logic */
695 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
696 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
697 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
698 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
699 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
700 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
701 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
702 { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat},
703 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
704 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
705 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
706 { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
707 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
734 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
742 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
749 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
750 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
752 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
753 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
756 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
757 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
777 return 0xff - (u8) sum; in msdc_dma_calcs()
790 sg = data->sg; in msdc_dma_setup()
792 gpd = dma->gpd; in msdc_dma_setup()
793 bd = dma->bd; in msdc_dma_setup()
796 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
797 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
799 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
800 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
803 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
811 if (host->dev_comp->support_64g) { in msdc_dma_setup()
817 if (host->dev_comp->support_64g) { in msdc_dma_setup()
825 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
835 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
836 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
839 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
840 if (host->dev_comp->support_64g) in msdc_dma_setup()
841 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
842 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
843 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
848 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
849 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
851 if (data->sg_count) in msdc_prepare_data()
852 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
858 return data->host_cookie & MSDC_PREPARE_FLAG; in msdc_data_prepared()
863 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
866 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
867 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
869 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
879 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
882 clk_ns = 1000000000U / mmc->actual_clock; in msdc_timeout_cal()
883 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
888 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
889 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
892 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
896 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
906 host->timeout_ns = ns; in msdc_set_timeout()
907 host->timeout_clks = clks; in msdc_set_timeout()
910 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
919 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
925 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
926 clk_disable_unprepare(host->crypto_clk); in msdc_gate_clock()
927 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
928 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
929 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
930 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
938 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
939 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
940 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
941 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
942 clk_prepare_enable(host->crypto_clk); in msdc_ungate_clock()
943 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
945 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
949 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
957 if (!host->top_base) in msdc_new_tx_setting()
960 val = readl(host->top_base + LOOP_TEST_CONTROL); in msdc_new_tx_setting()
965 switch (host->timing) { in msdc_new_tx_setting()
984 writel(val, host->top_base + LOOP_TEST_CONTROL); in msdc_new_tx_setting()
994 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
999 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
1000 host->mclk = 0; in msdc_set_mclk()
1001 mmc->actual_clock = 0; in msdc_set_mclk()
1002 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1006 if (host->timing != timing) in msdc_set_mclk()
1011 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
1012 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
1013 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
1014 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
1016 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1026 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
1028 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
1030 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
1031 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
1036 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
1037 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
1038 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1041 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1043 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
1046 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
1049 sclk = host->src_clk_freq; in msdc_set_mclk()
1052 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
1054 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
1056 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
1057 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
1060 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1062 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
1063 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
1064 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
1068 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
1072 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
1073 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
1074 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1075 mmc->actual_clock = sclk; in msdc_set_mclk()
1076 host->mclk = hz; in msdc_set_mclk()
1077 host->timing = timing; in msdc_set_mclk()
1079 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
1080 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
1086 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
1087 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
1088 if (host->top_base) { in msdc_set_mclk()
1089 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
1090 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
1091 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
1092 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
1094 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
1095 host->base + tune_reg); in msdc_set_mclk()
1098 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
1099 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
1100 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
1101 if (host->top_base) { in msdc_set_mclk()
1102 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
1103 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
1104 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
1105 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
1107 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
1108 host->base + tune_reg); in msdc_set_mclk()
1113 host->dev_comp->hs400_tune) in msdc_set_mclk()
1114 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
1116 host->hs400_cmd_int_delay); in msdc_set_mclk()
1117 if (host->dev_comp->support_new_tx && timing_changed) in msdc_set_mclk()
1120 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1161 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
1165 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1167 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
1179 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
1180 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1183 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1184 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1188 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1189 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1191 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1196 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1198 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1199 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1200 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1201 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1203 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1213 WARN_ON(host->data); in msdc_start_data()
1214 host->data = data; in msdc_start_data()
1215 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1217 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1218 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1219 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1220 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1221 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1222 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1223 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1229 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1231 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1234 cmd->error = 0; in msdc_auto_cmd_done()
1238 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1239 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1241 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1242 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1244 dev_err(host->dev, in msdc_auto_cmd_done()
1246 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1248 return cmd->error; in msdc_auto_cmd_done()
1252 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1263 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1264 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1266 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1267 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1279 if (host->error && in msdc_track_cmd_data()
1280 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) || in msdc_track_cmd_data()
1281 cmd->error == -ETIMEDOUT)) in msdc_track_cmd_data()
1282 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1283 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1296 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1306 * Note that non-HSQ requests will still be happening at times, even in msdc_request_done()
1307 * though it is enabled, and that's what is going to reset host->mrq. in msdc_request_done()
1312 hsq_req_done = host->hsq_en ? mmc_hsq_finalize_request(mmc, mrq) : false; in msdc_request_done()
1314 if (host->error) in msdc_request_done()
1319 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1320 host->mrq = NULL; in msdc_request_done()
1321 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1323 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1324 if (mrq->data) in msdc_request_done()
1325 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1326 if (host->error) in msdc_request_done()
1329 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1342 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1345 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1347 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1354 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1355 done = !host->cmd; in msdc_cmd_done()
1356 host->cmd = NULL; in msdc_cmd_done()
1357 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1361 rsp = cmd->resp; in msdc_cmd_done()
1363 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1365 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1366 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1367 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1368 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1369 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1370 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1372 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1377 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) || in msdc_cmd_done()
1378 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) in msdc_cmd_done()
1387 cmd->error = -EILSEQ; in msdc_cmd_done()
1388 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1390 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1391 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1394 if (cmd->error) in msdc_cmd_done()
1395 dev_dbg(host->dev, in msdc_cmd_done()
1397 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1398 cmd->error); in msdc_cmd_done()
1415 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1418 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1419 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1424 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1426 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1429 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1430 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1444 WARN_ON(host->cmd); in msdc_start_command()
1445 host->cmd = cmd; in msdc_start_command()
1447 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1451 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1452 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1453 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1457 cmd->error = 0; in msdc_start_command()
1460 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1461 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1462 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1464 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1465 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1471 if ((cmd->error && !host->hs400_tuning && in msdc_cmd_next()
1472 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1473 mmc_op_tuning(cmd->opcode))) || in msdc_cmd_next()
1474 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1476 else if (cmd == mrq->sbc) in msdc_cmd_next()
1477 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1478 else if (!cmd->data) in msdc_cmd_next()
1481 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1488 host->error = 0; in msdc_ops_request()
1489 WARN_ON(!host->hsq_en && host->mrq); in msdc_ops_request()
1490 host->mrq = mrq; in msdc_ops_request()
1492 if (mrq->data) { in msdc_ops_request()
1493 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1494 if (!msdc_data_prepared(mrq->data)) { in msdc_ops_request()
1495 host->mrq = NULL; in msdc_ops_request()
1500 mrq->cmd->error = -ENOSPC; in msdc_ops_request()
1510 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1511 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1512 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1514 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1520 struct mmc_data *data = mrq->data; in msdc_pre_req()
1526 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1533 struct mmc_data *data = mrq->data; in msdc_post_req()
1538 if (data->host_cookie) { in msdc_post_req()
1539 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1546 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1547 !mrq->sbc) in msdc_data_xfer_next()
1548 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1566 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1567 done = !host->data; in msdc_data_xfer_done()
1569 host->data = NULL; in msdc_data_xfer_done()
1570 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1574 stop = data->stop; in msdc_data_xfer_done()
1576 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1577 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1578 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1579 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1582 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1585 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1587 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1590 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1592 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1593 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1595 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1596 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1598 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1600 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1601 data->bytes_xfered = 0; in msdc_data_xfer_done()
1604 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1606 data->error = -EILSEQ; in msdc_data_xfer_done()
1608 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1609 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1610 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1611 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1620 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1637 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1638 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1646 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1647 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1648 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1649 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1650 return -EINVAL; in msdc_ops_switch_volt()
1655 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1656 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1660 /* Apply different pinctrl settings for different signal voltage */ in msdc_ops_switch_volt()
1661 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1662 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1664 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1672 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1684 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1685 if (host->mrq) { in msdc_request_timeout()
1686 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1687 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1688 if (host->cmd) { in msdc_request_timeout()
1689 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1690 __func__, host->cmd->opcode); in msdc_request_timeout()
1691 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1692 host->cmd); in msdc_request_timeout()
1693 } else if (host->data) { in msdc_request_timeout()
1694 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1695 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1696 host->data->blocks); in msdc_request_timeout()
1697 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1698 host->data); in msdc_request_timeout()
1706 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1707 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1708 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1711 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1712 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1722 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1724 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1726 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1731 * Since the current pinstate is pins_uhs, to ensure pinctrl select take in msdc_enable_sdio_irq()
1734 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1735 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1738 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1739 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1740 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1742 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1745 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1747 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1751 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1752 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1753 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1755 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1766 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1767 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1769 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1770 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1774 dat_err = -EILSEQ; in msdc_cmdq_irq()
1775 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1777 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1778 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1782 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x", in msdc_cmdq_irq()
1800 spin_lock(&host->lock); in msdc_irq()
1801 events = readl(host->base + MSDC_INT); in msdc_irq()
1802 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1806 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1808 mrq = host->mrq; in msdc_irq()
1809 cmd = host->cmd; in msdc_irq()
1810 data = host->data; in msdc_irq()
1811 spin_unlock(&host->lock); in msdc_irq()
1817 if (host->internal_cd) in msdc_irq()
1825 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1829 writel(events, host->base + MSDC_INT); in msdc_irq()
1834 dev_err(host->dev, in msdc_irq()
1841 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1855 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1858 if (host->reset) { in msdc_init_hw()
1859 reset_control_assert(host->reset); in msdc_init_hw()
1861 reset_control_deassert(host->reset); in msdc_init_hw()
1864 /* New tx/rx enable bit need to be 0->1 for hardware check */ in msdc_init_hw()
1865 if (host->dev_comp->support_new_tx) { in msdc_init_hw()
1866 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_init_hw()
1867 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_init_hw()
1870 if (host->dev_comp->support_new_rx) { in msdc_init_hw()
1871 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_init_hw()
1872 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_init_hw()
1876 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1882 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1883 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1884 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1887 if (host->internal_cd) { in msdc_init_hw()
1888 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1890 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1891 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1892 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1894 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1895 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1896 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1899 if (host->top_base) { in msdc_init_hw()
1900 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1901 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1903 writel(0, host->base + tune_reg); in msdc_init_hw()
1905 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1906 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1913 pb2_val = readl(host->base + MSDC_PATCH_BIT2); in msdc_init_hw()
1915 /* Enable odd number support for 8-bit data bus */ in msdc_init_hw()
1934 writel(val, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1942 sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val); in msdc_init_hw()
1954 if (!host->dev_comp->busy_check) in msdc_init_hw()
1957 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1958 if (host->dev_comp->stop_dly_sel) in msdc_init_hw()
1960 host->dev_comp->stop_dly_sel); in msdc_init_hw()
1962 if (host->dev_comp->pop_en_cnt) { in msdc_init_hw()
1965 host->dev_comp->pop_en_cnt); in msdc_init_hw()
1968 sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_WRVALIDSEL); in msdc_init_hw()
1969 sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_RDVALIDSEL); in msdc_init_hw()
1972 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1981 if (!host->dev_comp->enhance_rx) { in msdc_init_hw()
1986 } else if (host->top_base) { in msdc_init_hw()
1987 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, SDC_RX_ENH_EN); in msdc_init_hw()
1989 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_RX_ENHANCE_EN); in msdc_init_hw()
1993 if (host->dev_comp->support_64g) in msdc_init_hw()
1997 writel(pb1_val, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1998 writel(pb2_val, host->base + MSDC_PATCH_BIT2); in msdc_init_hw()
1999 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
2001 if (host->dev_comp->data_tune) { in msdc_init_hw()
2002 if (host->top_base) { in msdc_init_hw()
2003 u32 top_ctl_val = readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
2004 u32 top_cmd_val = readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
2009 if (host->tuning_step > PAD_DELAY_HALF) { in msdc_init_hw()
2014 writel(top_ctl_val, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
2015 writel(top_cmd_val, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
2017 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
2020 if (host->tuning_step > PAD_DELAY_HALF) in msdc_init_hw()
2021 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_init_hw()
2027 if (host->top_base) in msdc_init_hw()
2028 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
2031 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
2035 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_init_hw()
2036 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
2037 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
2038 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
2041 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
2044 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
2045 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
2049 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
2051 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
2052 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
2053 if (host->top_base) { in msdc_init_hw()
2054 host->def_tune_para.emmc_top_control = in msdc_init_hw()
2055 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
2056 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
2057 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
2058 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
2059 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
2060 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
2061 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
2063 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
2064 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
2066 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
2073 if (host->internal_cd) { in msdc_deinit_hw()
2074 /* Disabled card-detect */ in msdc_deinit_hw()
2075 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
2076 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
2080 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
2082 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
2083 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
2089 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
2090 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
2096 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
2097 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
2098 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
2101 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
2102 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2103 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
2105 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
2106 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
2107 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2108 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
2111 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
2112 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
2114 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2124 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
2127 switch (ios->power_mode) { in msdc_ops_set_ios()
2129 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
2131 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
2132 ios->vdd); in msdc_ops_set_ios()
2134 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
2140 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
2141 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
2143 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
2145 host->vqmmc_enabled = true; in msdc_ops_set_ios()
2149 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
2150 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
2152 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
2153 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
2154 host->vqmmc_enabled = false; in msdc_ops_set_ios()
2161 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
2162 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
2175 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) { in get_delay_len()
2179 return PAD_DELAY_FULL - start_bit; in get_delay_len()
2190 dev_err(host->dev, "phase error: [map:%016llx]\n", delay); in get_best_delay()
2211 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n", in get_best_delay()
2222 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
2224 if (host->top_base) { in msdc_set_cmd_delay()
2225 u32 regval = readl(host->top_base + EMMC_TOP_CMD); in msdc_set_cmd_delay()
2232 regval |= FIELD_PREP(PAD_CMD_RXDLY, PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2233 regval |= FIELD_PREP(PAD_CMD_RXDLY2, value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2235 writel(regval, host->top_base + EMMC_TOP_CMD); in msdc_set_cmd_delay()
2238 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value); in msdc_set_cmd_delay()
2239 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2242 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
2243 PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2244 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2245 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2252 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
2254 if (host->top_base) { in msdc_set_data_delay()
2255 u32 regval = readl(host->top_base + EMMC_TOP_CONTROL); in msdc_set_data_delay()
2263 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2264 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2266 writel(regval, host->top_base + EMMC_TOP_CONTROL); in msdc_set_data_delay()
2269 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value); in msdc_set_data_delay()
2270 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2273 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2274 PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2275 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2276 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2285 if (host->dev_comp->support_new_rx) { in msdc_set_data_sample_edge()
2286 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value); in msdc_set_data_sample_edge()
2287 sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value); in msdc_set_data_sample_edge()
2289 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value); in msdc_set_data_sample_edge()
2290 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value); in msdc_set_data_sample_edge()
2302 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2306 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
2307 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
2308 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2310 host->hs200_cmd_int_delay); in msdc_tune_response()
2312 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2313 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2336 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2337 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2361 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2364 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2369 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2372 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2373 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2379 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2381 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2384 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2385 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2398 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2399 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2401 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2402 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2403 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2405 host->hs200_cmd_int_delay); in hs400_tune_response()
2407 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2408 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2410 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2413 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2431 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2435 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2436 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2447 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2448 host->latch_ck); in msdc_tune_data()
2450 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2463 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2482 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2483 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2498 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2499 host->latch_ck); in msdc_tune_together()
2501 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2503 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2516 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2518 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2530 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2534 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2542 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2543 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2550 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2552 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2554 if (host->hs400_mode) { in msdc_execute_tuning()
2560 if (host->hs400_mode && in msdc_execute_tuning()
2561 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2565 if (ret == -EIO) { in msdc_execute_tuning()
2566 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2569 if (host->hs400_mode == false) { in msdc_execute_tuning()
2571 if (ret == -EIO) in msdc_execute_tuning()
2572 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2576 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2577 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2578 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2579 if (host->top_base) { in msdc_execute_tuning()
2580 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2582 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2592 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2594 if (host->top_base) { in msdc_prepare_hs400_tuning()
2595 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2596 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2597 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2598 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2599 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2600 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2602 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2603 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2604 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2605 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2606 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2609 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2611 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2624 if (host->top_base) { in msdc_execute_hs400_tuning()
2625 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2627 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2630 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2631 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL); in msdc_execute_hs400_tuning()
2634 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2636 if (host->top_base) in msdc_execute_hs400_tuning()
2637 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2640 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2648 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2652 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2655 if (host->top_base) in msdc_execute_hs400_tuning()
2656 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2659 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2662 if (host->top_base) in msdc_execute_hs400_tuning()
2663 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2665 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2667 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2672 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2673 return -EIO; in msdc_execute_hs400_tuning()
2680 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2682 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2690 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2692 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2700 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2703 if (!host->internal_cd) in msdc_get_cd()
2706 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2707 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2718 if (ios->enhanced_strobe) { in msdc_hs400_enhanced_strobe()
2720 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2721 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2722 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2724 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2725 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2726 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2728 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2729 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2730 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2732 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2733 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2734 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2741 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_cit_cal()
2750 hclk_freq = (u64)clk_get_rate(host->h_clk); in msdc_cqe_cit_cal()
2768 host->cq_ssc1_time = 0x40; in msdc_cqe_cit_cal()
2774 host->cq_ssc1_time = value; in msdc_cqe_cit_cal()
2780 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_enable()
2783 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2785 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2792 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); in msdc_cqe_enable()
2801 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2803 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2805 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2806 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2809 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2811 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2814 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2823 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2833 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2871 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2872 &host->latch_ck); in msdc_of_property_parse()
2874 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2875 &host->hs400_ds_delay); in msdc_of_property_parse()
2877 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", in msdc_of_property_parse()
2878 &host->hs400_ds_dly3); in msdc_of_property_parse()
2880 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2881 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2883 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2884 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2886 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2887 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2888 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2890 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2892 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step", in msdc_of_property_parse()
2893 &host->tuning_step)) { in msdc_of_property_parse()
2894 if (mmc->caps2 & MMC_CAP2_NO_MMC) in msdc_of_property_parse()
2895 host->tuning_step = PAD_DELAY_FULL; in msdc_of_property_parse()
2897 host->tuning_step = PAD_DELAY_HALF; in msdc_of_property_parse()
2900 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2901 "supports-cqe")) in msdc_of_property_parse()
2902 host->cqhci = true; in msdc_of_property_parse()
2904 host->cqhci = false; in msdc_of_property_parse()
2912 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2913 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2914 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2916 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2917 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2918 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2920 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2921 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2922 host->bus_clk = NULL; in msdc_of_clock_parse()
2925 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2926 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2927 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2930 * Fallback for legacy device-trees: src_clk and HCLK use the same in msdc_of_clock_parse()
2936 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2937 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2938 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2939 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2943 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2944 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2945 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2947 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2948 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2949 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2950 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, in msdc_of_clock_parse()
2951 host->bulk_clks); in msdc_of_clock_parse()
2953 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); in msdc_of_clock_parse()
2966 if (!pdev->dev.of_node) { in msdc_drv_probe()
2967 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2968 return -EINVAL; in msdc_drv_probe()
2972 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host)); in msdc_drv_probe()
2974 return -ENOMEM; in msdc_drv_probe()
2981 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2982 if (IS_ERR(host->base)) in msdc_drv_probe()
2983 return PTR_ERR(host->base); in msdc_drv_probe()
2985 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2987 if (host->dev_comp->needs_top_base) { in msdc_drv_probe()
2988 host->top_base = devm_platform_ioremap_resource(pdev, 1); in msdc_drv_probe()
2989 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2990 return PTR_ERR(host->top_base); in msdc_drv_probe()
3001 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
3003 if (IS_ERR(host->reset)) in msdc_drv_probe()
3004 return PTR_ERR(host->reset); in msdc_drv_probe()
3007 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { in msdc_drv_probe()
3008 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); in msdc_drv_probe()
3009 if (IS_ERR(host->crypto_clk)) in msdc_drv_probe()
3010 return PTR_ERR(host->crypto_clk); in msdc_drv_probe()
3011 else if (host->crypto_clk) in msdc_drv_probe()
3012 mmc->caps2 |= MMC_CAP2_CRYPTO; in msdc_drv_probe()
3015 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
3016 if (host->irq < 0) in msdc_drv_probe()
3017 return host->irq; in msdc_drv_probe()
3019 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
3020 if (IS_ERR(host->pinctrl)) in msdc_drv_probe()
3021 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl), in msdc_drv_probe()
3022 "Cannot find pinctrl"); in msdc_drv_probe()
3024 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
3025 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
3026 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
3027 return PTR_ERR(host->pins_default); in msdc_drv_probe()
3030 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
3031 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
3032 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
3033 return PTR_ERR(host->pins_uhs); in msdc_drv_probe()
3037 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { in msdc_drv_probe()
3038 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); in msdc_drv_probe()
3039 if (host->eint_irq > 0) { in msdc_drv_probe()
3040 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
3041 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
3042 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); in msdc_drv_probe()
3043 host->pins_eint = NULL; in msdc_drv_probe()
3045 device_init_wakeup(&pdev->dev, true); in msdc_drv_probe()
3052 host->dev = &pdev->dev; in msdc_drv_probe()
3053 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
3055 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
3056 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
3057 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
3059 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
3061 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
3063 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
3068 host->internal_cd = true; in msdc_drv_probe()
3071 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
3072 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
3074 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
3075 if (host->cqhci) in msdc_drv_probe()
3076 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
3078 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
3079 if (host->dev_comp->support_64g) in msdc_drv_probe()
3080 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
3082 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
3083 mmc->max_blk_size = 2048; in msdc_drv_probe()
3084 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
3085 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
3086 if (host->dev_comp->support_64g) in msdc_drv_probe()
3087 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
3089 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
3090 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
3092 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
3093 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
3095 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
3096 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
3098 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
3099 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
3100 ret = -ENOMEM; in msdc_drv_probe()
3103 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
3104 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
3105 spin_lock_init(&host->lock); in msdc_drv_probe()
3110 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); in msdc_drv_probe()
3115 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
3116 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
3117 sizeof(*host->cq_host), in msdc_drv_probe()
3119 if (!host->cq_host) { in msdc_drv_probe()
3120 ret = -ENOMEM; in msdc_drv_probe()
3123 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
3124 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
3125 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
3126 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
3129 mmc->max_segs = 128; in msdc_drv_probe()
3131 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
3132 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
3135 } else if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_drv_probe()
3137 struct mmc_hsq *hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); in msdc_drv_probe()
3139 ret = -ENOMEM; in msdc_drv_probe()
3147 host->hsq_en = true; in msdc_drv_probe()
3150 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
3151 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
3155 pm_runtime_set_active(host->dev); in msdc_drv_probe()
3156 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
3157 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
3158 pm_runtime_enable(host->dev); in msdc_drv_probe()
3166 pm_runtime_disable(host->dev); in msdc_drv_probe()
3173 device_init_wakeup(&pdev->dev, false); in msdc_drv_probe()
3174 if (host->dma.gpd) in msdc_drv_probe()
3175 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
3177 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
3178 if (host->dma.bd) in msdc_drv_probe()
3179 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
3181 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
3193 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
3200 pm_runtime_disable(host->dev); in msdc_drv_remove()
3201 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
3202 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
3204 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
3205 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
3206 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
3207 device_init_wakeup(&pdev->dev, false); in msdc_drv_remove()
3212 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
3214 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
3215 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
3216 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
3217 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
3218 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
3219 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
3220 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
3221 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
3222 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
3223 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
3224 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
3225 if (host->top_base) { in msdc_save_reg()
3226 host->save_para.emmc_top_control = in msdc_save_reg()
3227 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
3228 host->save_para.emmc_top_cmd = in msdc_save_reg()
3229 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
3230 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
3231 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
3232 host->save_para.loop_test_control = in msdc_save_reg()
3233 readl(host->top_base + LOOP_TEST_CONTROL); in msdc_save_reg()
3235 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
3242 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
3244 if (host->dev_comp->support_new_tx) { in msdc_restore_reg()
3245 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_restore_reg()
3246 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_restore_reg()
3248 if (host->dev_comp->support_new_rx) { in msdc_restore_reg()
3249 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_restore_reg()
3250 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_restore_reg()
3253 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
3254 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
3255 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
3256 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
3257 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
3258 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
3259 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
3260 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
3261 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
3262 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
3263 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
3264 if (host->top_base) { in msdc_restore_reg()
3265 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
3266 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
3267 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
3268 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
3269 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
3270 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
3271 writel(host->save_para.loop_test_control, in msdc_restore_reg()
3272 host->top_base + LOOP_TEST_CONTROL); in msdc_restore_reg()
3274 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
3286 if (host->hsq_en) in msdc_runtime_suspend()
3292 if (host->pins_eint) { in msdc_runtime_suspend()
3293 disable_irq(host->irq); in msdc_runtime_suspend()
3294 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
3315 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
3316 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
3317 enable_irq(host->irq); in msdc_runtime_resume()
3320 if (host->hsq_en) in msdc_runtime_resume()
3333 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
3337 val = readl(host->base + MSDC_INT); in msdc_suspend()
3338 writel(val, host->base + MSDC_INT); in msdc_suspend()
3342 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will in msdc_suspend()
3345 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
3356 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()
3371 .name = "mtk-msdc",