Lines Matching +full:ddr +full:- +full:sel +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
11 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
41 /*--------------------------------------------------------------------------*/
43 /*--------------------------------------------------------------------------*/
50 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
90 /*--------------------------------------------------------------------------*/
92 /*--------------------------------------------------------------------------*/
98 /*--------------------------------------------------------------------------*/
100 /*--------------------------------------------------------------------------*/
352 /*--------------------------------------------------------------------------*/
354 /*--------------------------------------------------------------------------*/
498 bool internal_cd; /* Use internal card-detect logic */
676 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
677 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
678 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
679 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
680 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
681 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
682 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
683 { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat},
684 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
685 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
686 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
687 { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
688 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
715 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
723 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
730 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
731 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
733 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
734 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
737 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
738 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
758 return 0xff - (u8) sum; in msdc_dma_calcs()
771 sg = data->sg; in msdc_dma_setup()
773 gpd = dma->gpd; in msdc_dma_setup()
774 bd = dma->bd; in msdc_dma_setup()
777 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
778 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
780 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
781 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
784 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
792 if (host->dev_comp->support_64g) { in msdc_dma_setup()
798 if (host->dev_comp->support_64g) { in msdc_dma_setup()
806 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
816 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
817 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
820 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
821 if (host->dev_comp->support_64g) in msdc_dma_setup()
822 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
823 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
824 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
829 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
830 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
831 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
838 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
841 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
842 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
844 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
854 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
857 clk_ns = 1000000000U / mmc->actual_clock; in msdc_timeout_cal()
858 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
863 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
864 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
867 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
869 /*DDR mode will double the clk cycles for data timeout */ in msdc_timeout_cal()
871 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
881 host->timeout_ns = ns; in msdc_set_timeout()
882 host->timeout_clks = clks; in msdc_set_timeout()
885 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
894 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
900 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
901 clk_disable_unprepare(host->crypto_clk); in msdc_gate_clock()
902 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
903 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
904 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
905 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
913 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
914 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
915 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
916 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
917 clk_prepare_enable(host->crypto_clk); in msdc_ungate_clock()
918 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
920 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
924 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
930 if (!host->top_base) in msdc_new_tx_setting()
933 sdr_set_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
935 sdr_set_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
937 sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
940 switch (host->timing) { in msdc_new_tx_setting()
948 sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
955 sdr_set_bits(host->top_base + LOOP_TEST_CONTROL, in msdc_new_tx_setting()
970 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
975 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
976 host->mclk = 0; in msdc_set_mclk()
977 mmc->actual_clock = 0; in msdc_set_mclk()
978 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
982 if (host->timing != timing) in msdc_set_mclk()
987 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
988 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
989 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
990 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
992 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1000 mode = 0x2; /* ddr mode and use divisor */ in msdc_set_mclk()
1002 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
1004 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
1006 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
1007 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
1012 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
1013 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
1014 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1017 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
1019 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
1022 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
1025 sclk = host->src_clk_freq; in msdc_set_mclk()
1028 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
1030 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
1032 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
1033 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
1036 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1038 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
1039 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
1040 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
1044 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
1048 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
1049 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
1050 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1051 mmc->actual_clock = sclk; in msdc_set_mclk()
1052 host->mclk = hz; in msdc_set_mclk()
1053 host->timing = timing; in msdc_set_mclk()
1055 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
1056 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
1062 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
1063 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
1064 if (host->top_base) { in msdc_set_mclk()
1065 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
1066 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
1067 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
1068 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
1070 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
1071 host->base + tune_reg); in msdc_set_mclk()
1074 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
1075 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
1076 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
1077 if (host->top_base) { in msdc_set_mclk()
1078 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
1079 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
1080 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
1081 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
1083 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
1084 host->base + tune_reg); in msdc_set_mclk()
1089 host->dev_comp->hs400_tune) in msdc_set_mclk()
1090 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
1092 host->hs400_cmd_int_delay); in msdc_set_mclk()
1093 if (host->dev_comp->support_new_tx && timing_changed) in msdc_set_mclk()
1096 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1137 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
1141 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1143 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
1155 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
1156 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1159 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1160 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1164 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1165 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1167 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1172 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1174 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1175 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1176 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1177 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1179 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1189 WARN_ON(host->data); in msdc_start_data()
1190 host->data = data; in msdc_start_data()
1191 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1193 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1194 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1195 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1196 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1197 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1198 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1199 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1205 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1207 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1210 cmd->error = 0; in msdc_auto_cmd_done()
1214 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1215 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1217 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1218 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1220 dev_err(host->dev, in msdc_auto_cmd_done()
1222 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1224 return cmd->error; in msdc_auto_cmd_done()
1228 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1239 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1240 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1242 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1243 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1255 if (host->error && in msdc_track_cmd_data()
1256 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) || in msdc_track_cmd_data()
1257 cmd->error == -ETIMEDOUT)) in msdc_track_cmd_data()
1258 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1259 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1272 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1282 * Note that non-HSQ requests will still be happening at times, even in msdc_request_done()
1283 * though it is enabled, and that's what is going to reset host->mrq. in msdc_request_done()
1288 hsq_req_done = host->hsq_en ? mmc_hsq_finalize_request(mmc, mrq) : false; in msdc_request_done()
1290 if (host->error) in msdc_request_done()
1295 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1296 host->mrq = NULL; in msdc_request_done()
1297 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1299 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1300 if (mrq->data) in msdc_request_done()
1301 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1302 if (host->error) in msdc_request_done()
1305 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1318 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1321 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1323 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1330 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1331 done = !host->cmd; in msdc_cmd_done()
1332 host->cmd = NULL; in msdc_cmd_done()
1333 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1337 rsp = cmd->resp; in msdc_cmd_done()
1339 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1341 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1342 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1343 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1344 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1345 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1346 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1348 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1353 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) || in msdc_cmd_done()
1354 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) in msdc_cmd_done()
1363 cmd->error = -EILSEQ; in msdc_cmd_done()
1364 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1366 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1367 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1370 if (cmd->error) in msdc_cmd_done()
1371 dev_dbg(host->dev, in msdc_cmd_done()
1373 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1374 cmd->error); in msdc_cmd_done()
1391 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1394 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1395 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1400 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1402 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1405 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1406 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1420 WARN_ON(host->cmd); in msdc_start_command()
1421 host->cmd = cmd; in msdc_start_command()
1423 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1427 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1428 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1429 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1433 cmd->error = 0; in msdc_start_command()
1436 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1437 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1438 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1440 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1441 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1447 if ((cmd->error && !host->hs400_tuning && in msdc_cmd_next()
1448 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1449 mmc_op_tuning(cmd->opcode))) || in msdc_cmd_next()
1450 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1452 else if (cmd == mrq->sbc) in msdc_cmd_next()
1453 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1454 else if (!cmd->data) in msdc_cmd_next()
1457 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1464 host->error = 0; in msdc_ops_request()
1465 WARN_ON(!host->hsq_en && host->mrq); in msdc_ops_request()
1466 host->mrq = mrq; in msdc_ops_request()
1468 if (mrq->data) in msdc_ops_request()
1469 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1475 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1476 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1477 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1479 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1485 struct mmc_data *data = mrq->data; in msdc_pre_req()
1491 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1498 struct mmc_data *data = mrq->data; in msdc_post_req()
1503 if (data->host_cookie) { in msdc_post_req()
1504 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1511 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1512 !mrq->sbc) in msdc_data_xfer_next()
1513 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1531 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1532 done = !host->data; in msdc_data_xfer_done()
1534 host->data = NULL; in msdc_data_xfer_done()
1535 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1539 stop = data->stop; in msdc_data_xfer_done()
1541 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1542 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1543 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1544 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1547 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1550 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1552 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1555 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1557 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1558 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1560 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1561 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1563 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1565 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1566 data->bytes_xfered = 0; in msdc_data_xfer_done()
1569 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1571 data->error = -EILSEQ; in msdc_data_xfer_done()
1573 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1574 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1575 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1576 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1585 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1602 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1603 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1611 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1612 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1613 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1614 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1615 return -EINVAL; in msdc_ops_switch_volt()
1620 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1621 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1626 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1627 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1629 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1637 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1639 /* only check if data0 is low */ in msdc_card_busy()
1649 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1650 if (host->mrq) { in msdc_request_timeout()
1651 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1652 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1653 if (host->cmd) { in msdc_request_timeout()
1654 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1655 __func__, host->cmd->opcode); in msdc_request_timeout()
1656 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1657 host->cmd); in msdc_request_timeout()
1658 } else if (host->data) { in msdc_request_timeout()
1659 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1660 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1661 host->data->blocks); in msdc_request_timeout()
1662 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1663 host->data); in msdc_request_timeout()
1671 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1672 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1673 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1676 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1677 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1687 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1689 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1691 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1699 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1700 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1703 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1704 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1705 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1707 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1710 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1712 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1716 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1717 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1718 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1720 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1731 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1732 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1734 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1735 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1739 dat_err = -EILSEQ; in msdc_cmdq_irq()
1740 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1742 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1743 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1747 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x", in msdc_cmdq_irq()
1765 spin_lock(&host->lock); in msdc_irq()
1766 events = readl(host->base + MSDC_INT); in msdc_irq()
1767 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1771 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1773 mrq = host->mrq; in msdc_irq()
1774 cmd = host->cmd; in msdc_irq()
1775 data = host->data; in msdc_irq()
1776 spin_unlock(&host->lock); in msdc_irq()
1782 if (host->internal_cd) in msdc_irq()
1790 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1794 writel(events, host->base + MSDC_INT); in msdc_irq()
1799 dev_err(host->dev, in msdc_irq()
1806 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1820 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1823 if (host->reset) { in msdc_init_hw()
1824 reset_control_assert(host->reset); in msdc_init_hw()
1826 reset_control_deassert(host->reset); in msdc_init_hw()
1829 /* New tx/rx enable bit need to be 0->1 for hardware check */ in msdc_init_hw()
1830 if (host->dev_comp->support_new_tx) { in msdc_init_hw()
1831 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_init_hw()
1832 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_init_hw()
1835 if (host->dev_comp->support_new_rx) { in msdc_init_hw()
1836 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_init_hw()
1837 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_init_hw()
1841 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1847 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1848 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1849 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1852 if (host->internal_cd) { in msdc_init_hw()
1853 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1855 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1856 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1857 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1859 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1860 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1861 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1864 if (host->top_base) { in msdc_init_hw()
1865 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1866 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1868 writel(0, host->base + tune_reg); in msdc_init_hw()
1870 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1871 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1872 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1873 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1874 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1875 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1877 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1878 if (host->dev_comp->stop_dly_sel) in msdc_init_hw()
1879 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1881 host->dev_comp->stop_dly_sel); in msdc_init_hw()
1883 if (host->dev_comp->pop_en_cnt) in msdc_init_hw()
1884 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1886 host->dev_comp->pop_en_cnt); in msdc_init_hw()
1888 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1890 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1894 if (host->dev_comp->busy_check) in msdc_init_hw()
1895 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); in msdc_init_hw()
1897 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1898 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1900 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1901 if (host->top_base) in msdc_init_hw()
1902 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1905 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1908 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1910 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1914 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1916 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1920 if (host->dev_comp->support_64g) in msdc_init_hw()
1921 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1923 if (host->dev_comp->data_tune) { in msdc_init_hw()
1924 if (host->top_base) { in msdc_init_hw()
1925 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1927 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1929 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1931 if (host->tuning_step > PAD_DELAY_HALF) { in msdc_init_hw()
1932 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1934 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1938 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1941 if (host->tuning_step > PAD_DELAY_HALF) in msdc_init_hw()
1942 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_init_hw()
1948 if (host->top_base) in msdc_init_hw()
1949 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1952 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1956 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_init_hw()
1957 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1958 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
1959 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1962 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1965 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1966 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1970 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1972 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1973 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1974 if (host->top_base) { in msdc_init_hw()
1975 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1976 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1977 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1978 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1979 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1980 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1981 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1982 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1984 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1985 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1987 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1994 if (host->internal_cd) { in msdc_deinit_hw()
1995 /* Disabled card-detect */ in msdc_deinit_hw()
1996 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1997 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
2001 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
2003 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
2004 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
2010 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
2011 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
2017 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
2018 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
2019 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
2022 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
2023 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2024 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
2026 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
2027 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
2028 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2029 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
2032 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
2033 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
2035 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
2045 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
2048 switch (ios->power_mode) { in msdc_ops_set_ios()
2050 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
2052 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
2053 ios->vdd); in msdc_ops_set_ios()
2055 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
2061 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
2062 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
2064 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
2066 host->vqmmc_enabled = true; in msdc_ops_set_ios()
2070 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
2071 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
2073 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
2074 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
2075 host->vqmmc_enabled = false; in msdc_ops_set_ios()
2082 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
2083 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
2096 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) { in get_delay_len()
2100 return PAD_DELAY_FULL - start_bit; in get_delay_len()
2111 dev_err(host->dev, "phase error: [map:%016llx]\n", delay); in get_best_delay()
2132 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n", in get_best_delay()
2143 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
2145 if (host->top_base) { in msdc_set_cmd_delay()
2147 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value); in msdc_set_cmd_delay()
2148 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0); in msdc_set_cmd_delay()
2150 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
2151 PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2152 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, in msdc_set_cmd_delay()
2153 value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2157 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value); in msdc_set_cmd_delay()
2158 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2161 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
2162 PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2163 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2164 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2171 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
2173 if (host->top_base) { in msdc_set_data_delay()
2175 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2177 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2180 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2181 PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2182 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2183 PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2187 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value); in msdc_set_data_delay()
2188 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2191 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2192 PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2193 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2194 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2203 if (host->dev_comp->support_new_rx) { in msdc_set_data_sample_edge()
2204 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value); in msdc_set_data_sample_edge()
2205 sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value); in msdc_set_data_sample_edge()
2207 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value); in msdc_set_data_sample_edge()
2208 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value); in msdc_set_data_sample_edge()
2220 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2224 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
2225 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
2226 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2228 host->hs200_cmd_int_delay); in msdc_tune_response()
2230 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2231 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2254 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2255 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2279 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2282 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2287 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2290 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2291 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2297 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2299 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2302 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2303 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2316 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2317 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2319 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2320 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2321 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2323 host->hs200_cmd_int_delay); in hs400_tune_response()
2325 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2326 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2328 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2331 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2349 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2353 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2354 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2365 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2366 host->latch_ck); in msdc_tune_data()
2368 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2381 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2400 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2401 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2416 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2417 host->latch_ck); in msdc_tune_together()
2419 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2421 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2434 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2436 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2448 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2452 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2460 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2461 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2468 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2470 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2472 if (host->hs400_mode) { in msdc_execute_tuning()
2478 if (host->hs400_mode && in msdc_execute_tuning()
2479 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2483 if (ret == -EIO) { in msdc_execute_tuning()
2484 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2487 if (host->hs400_mode == false) { in msdc_execute_tuning()
2489 if (ret == -EIO) in msdc_execute_tuning()
2490 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2494 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2495 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2496 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2497 if (host->top_base) { in msdc_execute_tuning()
2498 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2500 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2510 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2512 if (host->top_base) { in msdc_prepare_hs400_tuning()
2513 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2514 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2515 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2516 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2517 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2518 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2520 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2521 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2522 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2523 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2524 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2527 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2529 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2542 if (host->top_base) { in msdc_execute_hs400_tuning()
2543 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2545 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2548 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2549 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL); in msdc_execute_hs400_tuning()
2552 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2554 if (host->top_base) in msdc_execute_hs400_tuning()
2555 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2558 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2566 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2570 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2573 if (host->top_base) in msdc_execute_hs400_tuning()
2574 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2577 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2580 if (host->top_base) in msdc_execute_hs400_tuning()
2581 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2583 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2585 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2590 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2591 return -EIO; in msdc_execute_hs400_tuning()
2598 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2600 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2608 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2610 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2618 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2621 if (!host->internal_cd) in msdc_get_cd()
2624 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2625 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2636 if (ios->enhanced_strobe) { in msdc_hs400_enhanced_strobe()
2638 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2639 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2640 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2642 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2643 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2644 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2646 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2647 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2648 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2650 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2651 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2652 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2659 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_cit_cal()
2668 hclk_freq = (u64)clk_get_rate(host->h_clk); in msdc_cqe_cit_cal()
2686 host->cq_ssc1_time = 0x40; in msdc_cqe_cit_cal()
2692 host->cq_ssc1_time = value; in msdc_cqe_cit_cal()
2698 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_enable()
2701 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2703 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2710 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); in msdc_cqe_enable()
2719 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2721 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2723 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2724 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2727 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2729 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2732 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2741 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2751 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2789 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2790 &host->latch_ck); in msdc_of_property_parse()
2792 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2793 &host->hs400_ds_delay); in msdc_of_property_parse()
2795 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", in msdc_of_property_parse()
2796 &host->hs400_ds_dly3); in msdc_of_property_parse()
2798 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2799 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2801 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2802 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2804 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2805 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2806 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2808 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2810 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step", in msdc_of_property_parse()
2811 &host->tuning_step)) { in msdc_of_property_parse()
2812 if (mmc->caps2 & MMC_CAP2_NO_MMC) in msdc_of_property_parse()
2813 host->tuning_step = PAD_DELAY_FULL; in msdc_of_property_parse()
2815 host->tuning_step = PAD_DELAY_HALF; in msdc_of_property_parse()
2818 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2819 "supports-cqe")) in msdc_of_property_parse()
2820 host->cqhci = true; in msdc_of_property_parse()
2822 host->cqhci = false; in msdc_of_property_parse()
2830 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2831 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2832 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2834 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2835 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2836 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2838 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2839 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2840 host->bus_clk = NULL; in msdc_of_clock_parse()
2843 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2844 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2845 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2848 * Fallback for legacy device-trees: src_clk and HCLK use the same in msdc_of_clock_parse()
2854 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2855 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2856 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2857 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2861 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2862 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2863 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2865 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2866 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2867 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2868 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, in msdc_of_clock_parse()
2869 host->bulk_clks); in msdc_of_clock_parse()
2871 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); in msdc_of_clock_parse()
2884 if (!pdev->dev.of_node) { in msdc_drv_probe()
2885 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2886 return -EINVAL; in msdc_drv_probe()
2890 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host)); in msdc_drv_probe()
2892 return -ENOMEM; in msdc_drv_probe()
2899 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2900 if (IS_ERR(host->base)) in msdc_drv_probe()
2901 return PTR_ERR(host->base); in msdc_drv_probe()
2903 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2905 if (host->dev_comp->needs_top_base) { in msdc_drv_probe()
2906 host->top_base = devm_platform_ioremap_resource(pdev, 1); in msdc_drv_probe()
2907 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2908 return PTR_ERR(host->top_base); in msdc_drv_probe()
2919 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2921 if (IS_ERR(host->reset)) in msdc_drv_probe()
2922 return PTR_ERR(host->reset); in msdc_drv_probe()
2925 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { in msdc_drv_probe()
2926 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); in msdc_drv_probe()
2927 if (IS_ERR(host->crypto_clk)) in msdc_drv_probe()
2928 return PTR_ERR(host->crypto_clk); in msdc_drv_probe()
2929 else if (host->crypto_clk) in msdc_drv_probe()
2930 mmc->caps2 |= MMC_CAP2_CRYPTO; in msdc_drv_probe()
2933 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2934 if (host->irq < 0) in msdc_drv_probe()
2935 return host->irq; in msdc_drv_probe()
2937 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2938 if (IS_ERR(host->pinctrl)) in msdc_drv_probe()
2939 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl), in msdc_drv_probe()
2942 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2943 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2944 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
2945 return PTR_ERR(host->pins_default); in msdc_drv_probe()
2948 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2949 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2950 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
2951 return PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2955 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { in msdc_drv_probe()
2956 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); in msdc_drv_probe()
2957 if (host->eint_irq > 0) { in msdc_drv_probe()
2958 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
2959 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
2960 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); in msdc_drv_probe()
2961 host->pins_eint = NULL; in msdc_drv_probe()
2963 device_init_wakeup(&pdev->dev, true); in msdc_drv_probe()
2970 host->dev = &pdev->dev; in msdc_drv_probe()
2971 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2973 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
2974 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2975 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2977 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2979 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
2981 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2986 host->internal_cd = true; in msdc_drv_probe()
2989 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
2990 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
2992 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
2993 if (host->cqhci) in msdc_drv_probe()
2994 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
2996 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
2997 if (host->dev_comp->support_64g) in msdc_drv_probe()
2998 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
3000 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
3001 mmc->max_blk_size = 2048; in msdc_drv_probe()
3002 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
3003 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
3004 if (host->dev_comp->support_64g) in msdc_drv_probe()
3005 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
3007 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
3008 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
3010 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
3011 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
3013 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
3014 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
3016 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
3017 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
3018 ret = -ENOMEM; in msdc_drv_probe()
3021 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
3022 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
3023 spin_lock_init(&host->lock); in msdc_drv_probe()
3028 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); in msdc_drv_probe()
3033 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
3034 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
3035 sizeof(*host->cq_host), in msdc_drv_probe()
3037 if (!host->cq_host) { in msdc_drv_probe()
3038 ret = -ENOMEM; in msdc_drv_probe()
3041 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
3042 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
3043 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
3044 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
3047 mmc->max_segs = 128; in msdc_drv_probe()
3049 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
3050 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
3053 } else if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_drv_probe()
3055 struct mmc_hsq *hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); in msdc_drv_probe()
3057 ret = -ENOMEM; in msdc_drv_probe()
3065 host->hsq_en = true; in msdc_drv_probe()
3068 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
3069 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
3073 pm_runtime_set_active(host->dev); in msdc_drv_probe()
3074 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
3075 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
3076 pm_runtime_enable(host->dev); in msdc_drv_probe()
3084 pm_runtime_disable(host->dev); in msdc_drv_probe()
3091 device_init_wakeup(&pdev->dev, false); in msdc_drv_probe()
3092 if (host->dma.gpd) in msdc_drv_probe()
3093 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
3095 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
3096 if (host->dma.bd) in msdc_drv_probe()
3097 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
3099 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
3111 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
3118 pm_runtime_disable(host->dev); in msdc_drv_remove()
3119 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
3120 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
3122 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
3123 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
3124 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
3125 device_init_wakeup(&pdev->dev, false); in msdc_drv_remove()
3130 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
3132 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
3133 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
3134 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
3135 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
3136 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
3137 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
3138 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
3139 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
3140 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
3141 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
3142 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
3143 if (host->top_base) { in msdc_save_reg()
3144 host->save_para.emmc_top_control = in msdc_save_reg()
3145 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
3146 host->save_para.emmc_top_cmd = in msdc_save_reg()
3147 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
3148 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
3149 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
3150 host->save_para.loop_test_control = in msdc_save_reg()
3151 readl(host->top_base + LOOP_TEST_CONTROL); in msdc_save_reg()
3153 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
3160 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
3162 if (host->dev_comp->support_new_tx) { in msdc_restore_reg()
3163 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_restore_reg()
3164 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN); in msdc_restore_reg()
3166 if (host->dev_comp->support_new_rx) { in msdc_restore_reg()
3167 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_restore_reg()
3168 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL); in msdc_restore_reg()
3171 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
3172 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
3173 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
3174 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
3175 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
3176 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
3177 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
3178 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
3179 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
3180 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
3181 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
3182 if (host->top_base) { in msdc_restore_reg()
3183 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
3184 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
3185 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
3186 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
3187 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
3188 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
3189 writel(host->save_para.loop_test_control, in msdc_restore_reg()
3190 host->top_base + LOOP_TEST_CONTROL); in msdc_restore_reg()
3192 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
3204 if (host->hsq_en) in msdc_runtime_suspend()
3210 if (host->pins_eint) { in msdc_runtime_suspend()
3211 disable_irq(host->irq); in msdc_runtime_suspend()
3212 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
3233 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
3234 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
3235 enable_irq(host->irq); in msdc_runtime_resume()
3238 if (host->hsq_en) in msdc_runtime_resume()
3251 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
3255 val = readl(host->base + MSDC_INT); in msdc_suspend()
3256 writel(val, host->base + MSDC_INT); in msdc_suspend()
3260 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will in msdc_suspend()
3263 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
3274 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()
3289 .name = "mtk-msdc",