Lines Matching +full:ckin +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
6 * Copyright (C) 2010 ST-Ericsson SA
26 #include <linux/mmc/slot-gpio.h>
33 #include <linux/dma-mapping.h>
47 #define DRIVER_NAME "mmci-pl18x"
377 spin_lock_irqsave(&host->lock, flags); in mmci_card_busy()
378 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) in mmci_card_busy()
380 spin_unlock_irqrestore(&host->lock, flags); in mmci_card_busy()
394 if (host->cclk < 25000000) in mmci_reg_delay()
401 * This must be called with host->lock held
405 if (host->clk_reg != clk) { in mmci_write_clkreg()
406 host->clk_reg = clk; in mmci_write_clkreg()
407 writel(clk, host->base + MMCICLOCK); in mmci_write_clkreg()
412 * This must be called with host->lock held
416 if (host->pwr_reg != pwr) { in mmci_write_pwrreg()
417 host->pwr_reg = pwr; in mmci_write_pwrreg()
418 writel(pwr, host->base + MMCIPOWER); in mmci_write_pwrreg()
423 * This must be called with host->lock held
428 datactrl |= host->datactrl_reg & (host->variant->busy_dpsm_flag | in mmci_write_datactrlreg()
429 host->variant->datactrl_mask_sdio); in mmci_write_datactrlreg()
431 if (host->datactrl_reg != datactrl) { in mmci_write_datactrlreg()
432 host->datactrl_reg = datactrl; in mmci_write_datactrlreg()
433 writel(datactrl, host->base + MMCIDATACTRL); in mmci_write_datactrlreg()
438 * This must be called with host->lock held
442 struct variant_data *variant = host->variant; in mmci_set_clkreg()
443 u32 clk = variant->clkreg; in mmci_set_clkreg()
446 host->cclk = 0; in mmci_set_clkreg()
449 if (variant->explicit_mclk_control) { in mmci_set_clkreg()
450 host->cclk = host->mclk; in mmci_set_clkreg()
451 } else if (desired >= host->mclk) { in mmci_set_clkreg()
453 if (variant->st_clkdiv) in mmci_set_clkreg()
455 host->cclk = host->mclk; in mmci_set_clkreg()
456 } else if (variant->st_clkdiv) { in mmci_set_clkreg()
459 * => clkdiv = (mclk / f) - 2 in mmci_set_clkreg()
463 clk = DIV_ROUND_UP(host->mclk, desired) - 2; in mmci_set_clkreg()
466 host->cclk = host->mclk / (clk + 2); in mmci_set_clkreg()
470 * => clkdiv = mclk / (2 * f) - 1 in mmci_set_clkreg()
472 clk = host->mclk / (2 * desired) - 1; in mmci_set_clkreg()
475 host->cclk = host->mclk / (2 * (clk + 1)); in mmci_set_clkreg()
478 clk |= variant->clkreg_enable; in mmci_set_clkreg()
485 host->mmc->actual_clock = host->cclk; in mmci_set_clkreg()
487 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) in mmci_set_clkreg()
489 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) in mmci_set_clkreg()
490 clk |= variant->clkreg_8bit_bus_enable; in mmci_set_clkreg()
492 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_set_clkreg()
493 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) in mmci_set_clkreg()
494 clk |= variant->clkreg_neg_edge_enable; in mmci_set_clkreg()
501 if (host->ops && host->ops->dma_release) in mmci_dma_release()
502 host->ops->dma_release(host); in mmci_dma_release()
504 host->use_dma = false; in mmci_dma_release()
509 if (!host->ops || !host->ops->dma_setup) in mmci_dma_setup()
512 if (host->ops->dma_setup(host)) in mmci_dma_setup()
516 host->next_cookie = 1; in mmci_dma_setup()
518 host->use_dma = true; in mmci_dma_setup()
527 struct variant_data *variant = host->variant; in mmci_validate_data()
531 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { in mmci_validate_data()
532 dev_err(mmc_dev(host->mmc), in mmci_validate_data()
533 "unsupported block size (%d bytes)\n", data->blksz); in mmci_validate_data()
534 return -EINVAL; in mmci_validate_data()
537 if (host->ops && host->ops->validate_data) in mmci_validate_data()
538 return host->ops->validate_data(host, data); in mmci_validate_data()
547 if (!host->ops || !host->ops->prep_data) in mmci_prep_data()
550 err = host->ops->prep_data(host, data, next); in mmci_prep_data()
553 data->host_cookie = ++host->next_cookie < 0 ? in mmci_prep_data()
554 1 : host->next_cookie; in mmci_prep_data()
562 if (host->ops && host->ops->unprep_data) in mmci_unprep_data()
563 host->ops->unprep_data(host, data, err); in mmci_unprep_data()
565 data->host_cookie = 0; in mmci_unprep_data()
570 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); in mmci_get_next_data()
572 if (host->ops && host->ops->get_next_data) in mmci_get_next_data()
573 host->ops->get_next_data(host, data); in mmci_get_next_data()
578 struct mmc_data *data = host->data; in mmci_dma_start()
581 if (!host->use_dma) in mmci_dma_start()
582 return -EINVAL; in mmci_dma_start()
588 if (!host->ops || !host->ops->dma_start) in mmci_dma_start()
589 return -EINVAL; in mmci_dma_start()
592 dev_vdbg(mmc_dev(host->mmc), in mmci_dma_start()
594 data->sg_len, data->blksz, data->blocks, data->flags); in mmci_dma_start()
596 ret = host->ops->dma_start(host, &datactrl); in mmci_dma_start()
608 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, in mmci_dma_start()
609 host->base + MMCIMASK0); in mmci_dma_start()
615 if (!host->use_dma) in mmci_dma_finalize()
618 if (host->ops && host->ops->dma_finalize) in mmci_dma_finalize()
619 host->ops->dma_finalize(host, data); in mmci_dma_finalize()
624 if (!host->use_dma) in mmci_dma_error()
627 if (host->ops && host->ops->dma_error) in mmci_dma_error()
628 host->ops->dma_error(host); in mmci_dma_error()
634 writel(0, host->base + MMCICOMMAND); in mmci_request_end()
636 BUG_ON(host->data); in mmci_request_end()
638 host->mrq = NULL; in mmci_request_end()
639 host->cmd = NULL; in mmci_request_end()
641 mmc_request_done(host->mmc, mrq); in mmci_request_end()
646 void __iomem *base = host->base; in mmci_set_mask1()
647 struct variant_data *variant = host->variant; in mmci_set_mask1()
649 if (host->singleirq) { in mmci_set_mask1()
652 mask0 &= ~variant->irq_pio_mask; in mmci_set_mask1()
658 if (variant->mmcimask1) in mmci_set_mask1()
661 host->mask1_reg = mask; in mmci_set_mask1()
668 host->data = NULL; in mmci_stop_data()
675 if (data->flags & MMC_DATA_READ) in mmci_init_sg()
680 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); in mmci_init_sg()
690 return MCI_DPSM_ENABLE | (host->data->blksz << 16); in ux500v2_get_dctrl_cfg()
695 void __iomem *base = host->base; in ux500_busy_clear_mask_done()
697 writel(host->variant->busy_detect_mask, base + MMCICLEAR); in ux500_busy_clear_mask_done()
699 ~host->variant->busy_detect_mask, base + MMCIMASK0); in ux500_busy_clear_mask_done()
700 host->busy_state = MMCI_BUSY_DONE; in ux500_busy_clear_mask_done()
701 host->busy_status = 0; in ux500_busy_clear_mask_done()
705 * ux500_busy_complete() - this will wait until the busy status
707 * host->busy_status until we know the card is not busy any more.
713 * DAT0 busy +-----------------+
715 * DAT0 not busy ----+ +--------
724 void __iomem *base = host->base; in ux500_busy_complete()
737 switch (host->busy_state) { in ux500_busy_complete()
742 * command in-progress, waiting for busy signaling to end, in ux500_busy_complete()
743 * store the status in host->busy_status. in ux500_busy_complete()
746 * it starts signaling busy on DAT0, hence re-read the in ux500_busy_complete()
754 * host->busy_status, which is what it should be in IDLE. in ux500_busy_complete()
756 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
760 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
761 if (status & host->variant->busy_detect_flag) { in ux500_busy_complete()
763 host->variant->busy_detect_mask, in ux500_busy_complete()
765 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ; in ux500_busy_complete()
766 schedule_delayed_work(&host->ux500_busy_timeout_work, in ux500_busy_complete()
767 msecs_to_jiffies(cmd->busy_timeout)); in ux500_busy_complete()
770 retries--; in ux500_busy_complete()
772 dev_dbg(mmc_dev(host->mmc), in ux500_busy_complete()
773 "no busy signalling in time CMD%02x\n", cmd->opcode); in ux500_busy_complete()
778 * If there is a command in-progress that has been successfully in ux500_busy_complete()
789 if (status & host->variant->busy_detect_flag) { in ux500_busy_complete()
790 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
791 writel(host->variant->busy_detect_mask, base + MMCICLEAR); in ux500_busy_complete()
792 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ; in ux500_busy_complete()
794 dev_dbg(mmc_dev(host->mmc), in ux500_busy_complete()
796 cmd->opcode); in ux500_busy_complete()
797 cancel_delayed_work(&host->ux500_busy_timeout_work); in ux500_busy_complete()
803 if (!(status & host->variant->busy_detect_flag)) { in ux500_busy_complete()
804 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
805 writel(host->variant->busy_detect_mask, base + MMCICLEAR); in ux500_busy_complete()
806 cancel_delayed_work(&host->ux500_busy_timeout_work); in ux500_busy_complete()
809 dev_dbg(mmc_dev(host->mmc), in ux500_busy_complete()
810 "busy status still asserted when handling busy end IRQ - will keep waiting CMD%02x\n", in ux500_busy_complete()
811 cmd->opcode); in ux500_busy_complete()
816 dev_dbg(mmc_dev(host->mmc), "fell through on state %d, CMD%02x\n", in ux500_busy_complete()
817 host->busy_state, cmd->opcode); in ux500_busy_complete()
822 return (host->busy_state == MMCI_BUSY_DONE); in ux500_busy_complete()
849 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); in mmci_dmae_setup()
851 return -ENOMEM; in mmci_dmae_setup()
853 host->dma_priv = dmae; in mmci_dmae_setup()
855 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); in mmci_dmae_setup()
856 if (IS_ERR(dmae->rx_channel)) { in mmci_dmae_setup()
857 int ret = PTR_ERR(dmae->rx_channel); in mmci_dmae_setup()
858 dmae->rx_channel = NULL; in mmci_dmae_setup()
862 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); in mmci_dmae_setup()
863 if (IS_ERR(dmae->tx_channel)) { in mmci_dmae_setup()
864 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) in mmci_dmae_setup()
865 dev_warn(mmc_dev(host->mmc), in mmci_dmae_setup()
867 dmae->tx_channel = NULL; in mmci_dmae_setup()
875 if (dmae->rx_channel && !dmae->tx_channel) in mmci_dmae_setup()
876 dmae->tx_channel = dmae->rx_channel; in mmci_dmae_setup()
878 if (dmae->rx_channel) in mmci_dmae_setup()
879 rxname = dma_chan_name(dmae->rx_channel); in mmci_dmae_setup()
883 if (dmae->tx_channel) in mmci_dmae_setup()
884 txname = dma_chan_name(dmae->tx_channel); in mmci_dmae_setup()
888 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", in mmci_dmae_setup()
895 if (dmae->tx_channel) { in mmci_dmae_setup()
896 struct device *dev = dmae->tx_channel->device->dev; in mmci_dmae_setup()
899 if (max_seg_size < host->mmc->max_seg_size) in mmci_dmae_setup()
900 host->mmc->max_seg_size = max_seg_size; in mmci_dmae_setup()
902 if (dmae->rx_channel) { in mmci_dmae_setup()
903 struct device *dev = dmae->rx_channel->device->dev; in mmci_dmae_setup()
906 if (max_seg_size < host->mmc->max_seg_size) in mmci_dmae_setup()
907 host->mmc->max_seg_size = max_seg_size; in mmci_dmae_setup()
910 if (!dmae->tx_channel || !dmae->rx_channel) { in mmci_dmae_setup()
912 return -EINVAL; in mmci_dmae_setup()
924 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_release()
926 if (dmae->rx_channel) in mmci_dmae_release()
927 dma_release_channel(dmae->rx_channel); in mmci_dmae_release()
928 if (dmae->tx_channel) in mmci_dmae_release()
929 dma_release_channel(dmae->tx_channel); in mmci_dmae_release()
930 dmae->rx_channel = dmae->tx_channel = NULL; in mmci_dmae_release()
935 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dma_unmap()
938 if (data->flags & MMC_DATA_READ) in mmci_dma_unmap()
939 chan = dmae->rx_channel; in mmci_dma_unmap()
941 chan = dmae->tx_channel; in mmci_dma_unmap()
943 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, in mmci_dma_unmap()
949 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_error()
954 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); in mmci_dmae_error()
955 dmaengine_terminate_all(dmae->cur); in mmci_dmae_error()
956 host->dma_in_progress = false; in mmci_dmae_error()
957 dmae->cur = NULL; in mmci_dmae_error()
958 dmae->desc_current = NULL; in mmci_dmae_error()
959 host->data->host_cookie = 0; in mmci_dmae_error()
961 mmci_dma_unmap(host, host->data); in mmci_dmae_error()
966 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_finalize()
975 status = readl(host->base + MMCISTATUS); in mmci_dmae_finalize()
982 * Check to see whether we still have some data left in the FIFO - in mmci_dmae_finalize()
984 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- in mmci_dmae_finalize()
989 if (!data->error) in mmci_dmae_finalize()
990 data->error = -EIO; in mmci_dmae_finalize()
991 } else if (!data->host_cookie) { in mmci_dmae_finalize()
996 * Use of DMA with scatter-gather is impossible. in mmci_dmae_finalize()
1000 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); in mmci_dmae_finalize()
1004 host->dma_in_progress = false; in mmci_dmae_finalize()
1005 dmae->cur = NULL; in mmci_dmae_finalize()
1006 dmae->desc_current = NULL; in mmci_dmae_finalize()
1009 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
1014 struct mmci_dmae_priv *dmae = host->dma_priv; in _mmci_dmae_prep_data()
1015 struct variant_data *variant = host->variant; in _mmci_dmae_prep_data()
1017 .src_addr = host->phybase + MMCIFIFO, in _mmci_dmae_prep_data()
1018 .dst_addr = host->phybase + MMCIFIFO, in _mmci_dmae_prep_data()
1021 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ in _mmci_dmae_prep_data()
1022 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ in _mmci_dmae_prep_data()
1023 .device_fc = variant->dma_flow_controller, in _mmci_dmae_prep_data()
1031 if (data->flags & MMC_DATA_READ) { in _mmci_dmae_prep_data()
1033 chan = dmae->rx_channel; in _mmci_dmae_prep_data()
1036 chan = dmae->tx_channel; in _mmci_dmae_prep_data()
1041 return -EINVAL; in _mmci_dmae_prep_data()
1044 if (data->blksz * data->blocks <= variant->fifosize) in _mmci_dmae_prep_data()
1045 return -EINVAL; in _mmci_dmae_prep_data()
1050 * - The Ux500 DMA controller (DMA40) in _mmci_dmae_prep_data()
1051 * - The MMCI DMA interface on the Ux500 in _mmci_dmae_prep_data()
1056 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) in _mmci_dmae_prep_data()
1057 return -EINVAL; in _mmci_dmae_prep_data()
1059 device = chan->device; in _mmci_dmae_prep_data()
1060 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, in _mmci_dmae_prep_data()
1063 return -EINVAL; in _mmci_dmae_prep_data()
1065 if (host->variant->qcom_dml) in _mmci_dmae_prep_data()
1069 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, in _mmci_dmae_prep_data()
1080 dma_unmap_sg(device->dev, data->sg, data->sg_len, in _mmci_dmae_prep_data()
1082 return -ENOMEM; in _mmci_dmae_prep_data()
1089 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_prep_data()
1090 struct mmci_dmae_next *nd = &dmae->next_data; in mmci_dmae_prep_data()
1092 if (!host->use_dma) in mmci_dmae_prep_data()
1093 return -EINVAL; in mmci_dmae_prep_data()
1096 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); in mmci_dmae_prep_data()
1098 if (dmae->cur && dmae->desc_current) in mmci_dmae_prep_data()
1102 return _mmci_dmae_prep_data(host, data, &dmae->cur, in mmci_dmae_prep_data()
1103 &dmae->desc_current); in mmci_dmae_prep_data()
1108 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_start()
1111 host->dma_in_progress = true; in mmci_dmae_start()
1112 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); in mmci_dmae_start()
1114 host->dma_in_progress = false; in mmci_dmae_start()
1117 dma_async_issue_pending(dmae->cur); in mmci_dmae_start()
1126 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_get_next_data()
1127 struct mmci_dmae_next *next = &dmae->next_data; in mmci_dmae_get_next_data()
1129 if (!host->use_dma) in mmci_dmae_get_next_data()
1132 WARN_ON(!data->host_cookie && (next->desc || next->chan)); in mmci_dmae_get_next_data()
1134 dmae->desc_current = next->desc; in mmci_dmae_get_next_data()
1135 dmae->cur = next->chan; in mmci_dmae_get_next_data()
1136 next->desc = NULL; in mmci_dmae_get_next_data()
1137 next->chan = NULL; in mmci_dmae_get_next_data()
1144 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_unprep_data()
1146 if (!host->use_dma) in mmci_dmae_unprep_data()
1152 struct mmci_dmae_next *next = &dmae->next_data; in mmci_dmae_unprep_data()
1154 if (data->flags & MMC_DATA_READ) in mmci_dmae_unprep_data()
1155 chan = dmae->rx_channel; in mmci_dmae_unprep_data()
1157 chan = dmae->tx_channel; in mmci_dmae_unprep_data()
1160 if (dmae->desc_current == next->desc) in mmci_dmae_unprep_data()
1161 dmae->desc_current = NULL; in mmci_dmae_unprep_data()
1163 if (dmae->cur == next->chan) { in mmci_dmae_unprep_data()
1164 host->dma_in_progress = false; in mmci_dmae_unprep_data()
1165 dmae->cur = NULL; in mmci_dmae_unprep_data()
1168 next->desc = NULL; in mmci_dmae_unprep_data()
1169 next->chan = NULL; in mmci_dmae_unprep_data()
1192 host->ops = &mmci_variant_ops; in mmci_variant_init()
1197 host->ops = &mmci_variant_ops; in ux500_variant_init()
1198 host->ops->busy_complete = ux500_busy_complete; in ux500_variant_init()
1203 host->ops = &mmci_variant_ops; in ux500v2_variant_init()
1204 host->ops->busy_complete = ux500_busy_complete; in ux500v2_variant_init()
1205 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; in ux500v2_variant_init()
1211 struct mmc_data *data = mrq->data; in mmci_pre_request()
1216 WARN_ON(data->host_cookie); in mmci_pre_request()
1228 struct mmc_data *data = mrq->data; in mmci_post_request()
1230 if (!data || !data->host_cookie) in mmci_post_request()
1238 struct variant_data *variant = host->variant; in mmci_start_data()
1243 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", in mmci_start_data()
1244 data->blksz, data->blocks, data->flags); in mmci_start_data()
1246 host->data = data; in mmci_start_data()
1247 host->size = data->blksz * data->blocks; in mmci_start_data()
1248 data->bytes_xfered = 0; in mmci_start_data()
1250 clks = (unsigned long long)data->timeout_ns * host->cclk; in mmci_start_data()
1253 timeout = data->timeout_clks + (unsigned int)clks; in mmci_start_data()
1255 base = host->base; in mmci_start_data()
1257 writel(host->size, base + MMCIDATALENGTH); in mmci_start_data()
1259 datactrl = host->ops->get_datactrl_cfg(host); in mmci_start_data()
1260 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; in mmci_start_data()
1262 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { in mmci_start_data()
1265 datactrl |= variant->datactrl_mask_sdio; in mmci_start_data()
1273 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && in mmci_start_data()
1274 (host->size < 8 || in mmci_start_data()
1275 (host->size <= 8 && host->mclk > 50000000))) in mmci_start_data()
1276 clk = host->clk_reg & ~variant->clkreg_enable; in mmci_start_data()
1278 clk = host->clk_reg | variant->clkreg_enable; in mmci_start_data()
1283 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_start_data()
1284 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) in mmci_start_data()
1285 datactrl |= variant->datactrl_mask_ddrmode; in mmci_start_data()
1297 if (data->flags & MMC_DATA_READ) { in mmci_start_data()
1301 * If we have less than the fifo 'half-full' threshold to in mmci_start_data()
1305 if (host->size < variant->fifohalfsize) in mmci_start_data()
1323 void __iomem *base = host->base; in mmci_start_command()
1324 bool busy_resp = cmd->flags & MMC_RSP_BUSY; in mmci_start_command()
1327 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", in mmci_start_command()
1328 cmd->opcode, cmd->arg, cmd->flags); in mmci_start_command()
1330 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { in mmci_start_command()
1335 if (host->variant->cmdreg_stop && in mmci_start_command()
1336 cmd->opcode == MMC_STOP_TRANSMISSION) in mmci_start_command()
1337 c |= host->variant->cmdreg_stop; in mmci_start_command()
1339 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; in mmci_start_command()
1340 if (cmd->flags & MMC_RSP_PRESENT) { in mmci_start_command()
1341 if (cmd->flags & MMC_RSP_136) in mmci_start_command()
1342 c |= host->variant->cmdreg_lrsp_crc; in mmci_start_command()
1343 else if (cmd->flags & MMC_RSP_CRC) in mmci_start_command()
1344 c |= host->variant->cmdreg_srsp_crc; in mmci_start_command()
1346 c |= host->variant->cmdreg_srsp; in mmci_start_command()
1349 host->busy_status = 0; in mmci_start_command()
1350 host->busy_state = MMCI_BUSY_DONE; in mmci_start_command()
1353 if (busy_resp && !cmd->busy_timeout) in mmci_start_command()
1354 cmd->busy_timeout = 10 * MSEC_PER_SEC; in mmci_start_command()
1356 if (busy_resp && host->variant->busy_timeout) { in mmci_start_command()
1357 if (cmd->busy_timeout > host->mmc->max_busy_timeout) in mmci_start_command()
1358 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk; in mmci_start_command()
1360 clks = (unsigned long long)cmd->busy_timeout * host->cclk; in mmci_start_command()
1363 writel_relaxed(clks, host->base + MMCIDATATIMER); in mmci_start_command()
1366 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) in mmci_start_command()
1367 host->ops->pre_sig_volt_switch(host); in mmci_start_command()
1373 c |= host->variant->data_cmd_enable; in mmci_start_command()
1375 host->cmd = cmd; in mmci_start_command()
1377 writel(cmd->arg, base + MMCIARGUMENT); in mmci_start_command()
1383 host->stop_abort.error = 0; in mmci_stop_command()
1384 mmci_start_command(host, &host->stop_abort, 0); in mmci_stop_command()
1398 status_err = status & (host->variant->start_err | in mmci_data_irq()
1412 * can be as much as a FIFO-worth of data ahead. This in mmci_data_irq()
1415 if (!host->variant->datacnt_useless) { in mmci_data_irq()
1416 remain = readl(host->base + MMCIDATACNT); in mmci_data_irq()
1417 success = data->blksz * data->blocks - remain; in mmci_data_irq()
1422 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", in mmci_data_irq()
1426 success -= 1; in mmci_data_irq()
1427 data->error = -EILSEQ; in mmci_data_irq()
1429 data->error = -ETIMEDOUT; in mmci_data_irq()
1431 data->error = -ECOMM; in mmci_data_irq()
1433 data->error = -EIO; in mmci_data_irq()
1435 if (success > host->variant->fifosize) in mmci_data_irq()
1436 success -= host->variant->fifosize; in mmci_data_irq()
1439 data->error = -EIO; in mmci_data_irq()
1441 data->bytes_xfered = round_down(success, data->blksz); in mmci_data_irq()
1445 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); in mmci_data_irq()
1447 if (status & MCI_DATAEND || data->error) { in mmci_data_irq()
1452 if (!data->error) in mmci_data_irq()
1454 data->bytes_xfered = data->blksz * data->blocks; in mmci_data_irq()
1456 if (!data->stop) { in mmci_data_irq()
1457 if (host->variant->cmdreg_stop && data->error) in mmci_data_irq()
1460 mmci_request_end(host, data->mrq); in mmci_data_irq()
1461 } else if (host->mrq->sbc && !data->error) { in mmci_data_irq()
1462 mmci_request_end(host, data->mrq); in mmci_data_irq()
1464 mmci_start_command(host, data->stop, 0); in mmci_data_irq()
1474 void __iomem *base = host->base; in mmci_cmd_irq()
1480 sbc = (cmd == host->mrq->sbc); in mmci_cmd_irq()
1481 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); in mmci_cmd_irq()
1488 if (host->variant->busy_timeout && busy_resp) in mmci_cmd_irq()
1491 if (!((status | host->busy_status) & in mmci_cmd_irq()
1496 if (busy_resp && host->variant->busy_detect) in mmci_cmd_irq()
1497 if (!host->ops->busy_complete(host, cmd, status, err_msk)) in mmci_cmd_irq()
1500 host->cmd = NULL; in mmci_cmd_irq()
1503 cmd->error = -ETIMEDOUT; in mmci_cmd_irq()
1504 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { in mmci_cmd_irq()
1505 cmd->error = -EILSEQ; in mmci_cmd_irq()
1506 } else if (host->variant->busy_timeout && busy_resp && in mmci_cmd_irq()
1508 cmd->error = -ETIMEDOUT; in mmci_cmd_irq()
1513 host->irq_action = IRQ_WAKE_THREAD; in mmci_cmd_irq()
1515 cmd->resp[0] = readl(base + MMCIRESPONSE0); in mmci_cmd_irq()
1516 cmd->resp[1] = readl(base + MMCIRESPONSE1); in mmci_cmd_irq()
1517 cmd->resp[2] = readl(base + MMCIRESPONSE2); in mmci_cmd_irq()
1518 cmd->resp[3] = readl(base + MMCIRESPONSE3); in mmci_cmd_irq()
1521 if ((!sbc && !cmd->data) || cmd->error) { in mmci_cmd_irq()
1522 if (host->data) { in mmci_cmd_irq()
1527 if (host->variant->cmdreg_stop && cmd->error) { in mmci_cmd_irq()
1533 if (host->irq_action != IRQ_WAKE_THREAD) in mmci_cmd_irq()
1534 mmci_request_end(host, host->mrq); in mmci_cmd_irq()
1537 mmci_start_command(host, host->mrq->cmd, 0); in mmci_cmd_irq()
1538 } else if (!host->variant->datactrl_first && in mmci_cmd_irq()
1539 !(cmd->data->flags & MMC_DATA_READ)) { in mmci_cmd_irq()
1540 mmci_start_data(host, cmd->data); in mmci_cmd_irq()
1546 switch (host->busy_state) { in ux500_state_str()
1570 spin_lock_irqsave(&host->lock, flags); in ux500_busy_timeout_work()
1572 if (host->cmd) { in ux500_busy_timeout_work()
1573 /* If we are still busy let's tag on a cmd-timeout error. */ in ux500_busy_timeout_work()
1574 status = readl(host->base + MMCISTATUS); in ux500_busy_timeout_work()
1575 if (status & host->variant->busy_detect_flag) { in ux500_busy_timeout_work()
1577 dev_err(mmc_dev(host->mmc), in ux500_busy_timeout_work()
1579 ux500_state_str(host), host->cmd->opcode); in ux500_busy_timeout_work()
1581 dev_err(mmc_dev(host->mmc), in ux500_busy_timeout_work()
1583 ux500_state_str(host), host->cmd->opcode); in ux500_busy_timeout_work()
1586 mmci_cmd_irq(host, host->cmd, status); in ux500_busy_timeout_work()
1589 spin_unlock_irqrestore(&host->lock, flags); in ux500_busy_timeout_work()
1594 return remain - (readl(host->base + MMCIFIFOCNT) << 2); in mmci_get_rx_fifocnt()
1604 return host->variant->fifohalfsize; in mmci_qcom_get_rx_fifocnt()
1613 void __iomem *base = host->base; in mmci_pio_read()
1615 u32 status = readl(host->base + MMCISTATUS); in mmci_pio_read()
1616 int host_remain = host->size; in mmci_pio_read()
1619 int count = host->get_rx_fifocnt(host, status, host_remain); in mmci_pio_read()
1631 * while only doing full 32-bit reads towards the FIFO. in mmci_pio_read()
1647 remain -= count; in mmci_pio_read()
1648 host_remain -= count; in mmci_pio_read()
1656 return ptr - buffer; in mmci_pio_read()
1661 struct variant_data *variant = host->variant; in mmci_pio_write()
1662 void __iomem *base = host->base; in mmci_pio_write()
1669 variant->fifosize : variant->fifohalfsize; in mmci_pio_write()
1675 * etc), and the FIFO only accept full 32-bit writes. in mmci_pio_write()
1683 remain -= count; in mmci_pio_write()
1691 return ptr - buffer; in mmci_pio_write()
1700 struct sg_mapping_iter *sg_miter = &host->sg_miter; in mmci_pio_irq()
1701 struct variant_data *variant = host->variant; in mmci_pio_irq()
1702 void __iomem *base = host->base; in mmci_pio_irq()
1707 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); in mmci_pio_irq()
1714 * For write, we only need to test the half-empty flag in mmci_pio_irq()
1715 * here - if the FIFO is completely empty, then by in mmci_pio_irq()
1726 buffer = sg_miter->addr; in mmci_pio_irq()
1727 remain = sg_miter->length; in mmci_pio_irq()
1735 sg_miter->consumed = len; in mmci_pio_irq()
1737 host->size -= len; in mmci_pio_irq()
1738 remain -= len; in mmci_pio_irq()
1749 * If we have less than the fifo 'half-full' threshold to transfer, in mmci_pio_irq()
1752 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) in mmci_pio_irq()
1761 if (host->size == 0) { in mmci_pio_irq()
1771 void __iomem *base = host->base; in mmci_write_sdio_irq_bit()
1784 sdio_signal_irq(host->mmc); in mmci_signal_sdio_irq()
1796 spin_lock(&host->lock); in mmci_irq()
1797 host->irq_action = IRQ_HANDLED; in mmci_irq()
1800 status = readl(host->base + MMCISTATUS); in mmci_irq()
1804 if (host->singleirq) { in mmci_irq()
1805 if (status & host->mask1_reg) in mmci_irq()
1808 status &= ~host->variant->irq_pio_mask; in mmci_irq()
1815 status &= readl(host->base + MMCIMASK0); in mmci_irq()
1816 if (host->variant->busy_detect) in mmci_irq()
1817 writel(status & ~host->variant->busy_detect_mask, in mmci_irq()
1818 host->base + MMCICLEAR); in mmci_irq()
1820 writel(status, host->base + MMCICLEAR); in mmci_irq()
1822 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); in mmci_irq()
1824 if (host->variant->reversed_irq_handling) { in mmci_irq()
1825 mmci_data_irq(host, host->data, status); in mmci_irq()
1826 mmci_cmd_irq(host, host->cmd, status); in mmci_irq()
1828 mmci_cmd_irq(host, host->cmd, status); in mmci_irq()
1829 mmci_data_irq(host, host->data, status); in mmci_irq()
1832 if (host->variant->supports_sdio_irq) in mmci_irq()
1839 if (host->variant->busy_detect_flag) in mmci_irq()
1840 status &= ~host->variant->busy_detect_flag; in mmci_irq()
1844 spin_unlock(&host->lock); in mmci_irq()
1846 return host->irq_action; in mmci_irq()
1850 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW.
1853 * causes the DPSM to stay busy (non-functional).
1860 if (host->rst) { in mmci_irq_thread()
1861 reset_control_assert(host->rst); in mmci_irq_thread()
1863 reset_control_deassert(host->rst); in mmci_irq_thread()
1866 spin_lock_irqsave(&host->lock, flags); in mmci_irq_thread()
1867 writel(host->clk_reg, host->base + MMCICLOCK); in mmci_irq_thread()
1868 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_irq_thread()
1869 writel(MCI_IRQENABLE | host->variant->start_err, in mmci_irq_thread()
1870 host->base + MMCIMASK0); in mmci_irq_thread()
1872 host->irq_action = IRQ_HANDLED; in mmci_irq_thread()
1873 mmci_request_end(host, host->mrq); in mmci_irq_thread()
1874 spin_unlock_irqrestore(&host->lock, flags); in mmci_irq_thread()
1876 return host->irq_action; in mmci_irq_thread()
1884 WARN_ON(host->mrq != NULL); in mmci_request()
1886 mrq->cmd->error = mmci_validate_data(host, mrq->data); in mmci_request()
1887 if (mrq->cmd->error) { in mmci_request()
1892 spin_lock_irqsave(&host->lock, flags); in mmci_request()
1894 host->mrq = mrq; in mmci_request()
1896 if (mrq->data) in mmci_request()
1897 mmci_get_next_data(host, mrq->data); in mmci_request()
1899 if (mrq->data && in mmci_request()
1900 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) in mmci_request()
1901 mmci_start_data(host, mrq->data); in mmci_request()
1903 if (mrq->sbc) in mmci_request()
1904 mmci_start_command(host, mrq->sbc, 0); in mmci_request()
1906 mmci_start_command(host, mrq->cmd, 0); in mmci_request()
1908 spin_unlock_irqrestore(&host->lock, flags); in mmci_request()
1916 if (!host->variant->busy_detect) in mmci_set_max_busy_timeout()
1919 if (host->variant->busy_timeout && mmc->actual_clock) in mmci_set_max_busy_timeout()
1920 max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock, in mmci_set_max_busy_timeout()
1923 mmc->max_busy_timeout = max_busy_timeout; in mmci_set_max_busy_timeout()
1929 struct variant_data *variant = host->variant; in mmci_set_ios()
1934 switch (ios->power_mode) { in mmci_set_ios()
1936 if (!IS_ERR(mmc->supply.vmmc)) in mmci_set_ios()
1937 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in mmci_set_ios()
1939 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in mmci_set_ios()
1940 regulator_disable(mmc->supply.vqmmc); in mmci_set_ios()
1941 host->vqmmc_enabled = false; in mmci_set_ios()
1946 if (!IS_ERR(mmc->supply.vmmc)) in mmci_set_ios()
1947 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); in mmci_set_ios()
1954 pwr |= variant->pwrreg_powerup; in mmci_set_ios()
1958 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in mmci_set_ios()
1959 ret = regulator_enable(mmc->supply.vqmmc); in mmci_set_ios()
1964 host->vqmmc_enabled = true; in mmci_set_ios()
1971 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { in mmci_set_ios()
1975 * the SD/MMC bus and feedback-clock usage. in mmci_set_ios()
1977 pwr |= host->pwr_reg_add; in mmci_set_ios()
1979 if (ios->bus_width == MMC_BUS_WIDTH_4) in mmci_set_ios()
1981 else if (ios->bus_width == MMC_BUS_WIDTH_1) in mmci_set_ios()
1987 if (variant->opendrain) { in mmci_set_ios()
1988 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) in mmci_set_ios()
1989 pwr |= variant->opendrain; in mmci_set_ios()
1995 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) in mmci_set_ios()
1996 pinctrl_select_state(host->pinctrl, host->pins_opendrain); in mmci_set_ios()
2005 if (!ios->clock && variant->pwrreg_clkgate) in mmci_set_ios()
2008 if (host->variant->explicit_mclk_control && in mmci_set_ios()
2009 ios->clock != host->clock_cache) { in mmci_set_ios()
2010 ret = clk_set_rate(host->clk, ios->clock); in mmci_set_ios()
2012 dev_err(mmc_dev(host->mmc), in mmci_set_ios()
2015 host->mclk = clk_get_rate(host->clk); in mmci_set_ios()
2017 host->clock_cache = ios->clock; in mmci_set_ios()
2019 spin_lock_irqsave(&host->lock, flags); in mmci_set_ios()
2021 if (host->ops && host->ops->set_clkreg) in mmci_set_ios()
2022 host->ops->set_clkreg(host, ios->clock); in mmci_set_ios()
2024 mmci_set_clkreg(host, ios->clock); in mmci_set_ios()
2028 if (host->ops && host->ops->set_pwrreg) in mmci_set_ios()
2029 host->ops->set_pwrreg(host, pwr); in mmci_set_ios()
2035 spin_unlock_irqrestore(&host->lock, flags); in mmci_set_ios()
2041 struct mmci_platform_data *plat = host->plat; in mmci_get_cd()
2044 if (status == -ENOSYS) { in mmci_get_cd()
2045 if (!plat->status) in mmci_get_cd()
2048 status = plat->status(mmc_dev(host->mmc)); in mmci_get_cd()
2060 if (!ret && host->ops && host->ops->post_sig_volt_switch) in mmci_sig_volt_switch()
2061 ret = host->ops->post_sig_volt_switch(host, ios); in mmci_sig_volt_switch()
2080 spin_lock_irqsave(&host->lock, flags); in mmci_enable_sdio_irq()
2082 spin_unlock_irqrestore(&host->lock, flags); in mmci_enable_sdio_irq()
2095 spin_lock_irqsave(&host->lock, flags); in mmci_ack_sdio_irq()
2097 spin_unlock_irqrestore(&host->lock, flags); in mmci_ack_sdio_irq()
2120 * Assume the level translator is present if st,use-ckin is set. in mmci_probe_level_translator()
2123 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; in mmci_probe_level_translator()
2133 ckin_gpio = gpiod_get(dev, "st,ckin", GPIOD_IN); in mmci_probe_level_translator()
2137 /* All GPIOs are valid, test whether level translator works */ in mmci_probe_level_translator()
2139 /* Sample CKIN */ in mmci_probe_level_translator()
2145 /* Sample CKIN */ in mmci_probe_level_translator()
2152 /* Level translator is present if CK signal is propagated to CKIN */ in mmci_probe_level_translator()
2154 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN; in mmci_probe_level_translator()
2156 "Level translator inoperable, CK signal not detected on CKIN, disabling.\n"); in mmci_probe_level_translator()
2177 if (of_property_read_bool(np, "st,sig-dir-dat0")) in mmci_of_parse()
2178 host->pwr_reg_add |= MCI_ST_DATA0DIREN; in mmci_of_parse()
2179 if (of_property_read_bool(np, "st,sig-dir-dat2")) in mmci_of_parse()
2180 host->pwr_reg_add |= MCI_ST_DATA2DIREN; in mmci_of_parse()
2181 if (of_property_read_bool(np, "st,sig-dir-dat31")) in mmci_of_parse()
2182 host->pwr_reg_add |= MCI_ST_DATA31DIREN; in mmci_of_parse()
2183 if (of_property_read_bool(np, "st,sig-dir-dat74")) in mmci_of_parse()
2184 host->pwr_reg_add |= MCI_ST_DATA74DIREN; in mmci_of_parse()
2185 if (of_property_read_bool(np, "st,sig-dir-cmd")) in mmci_of_parse()
2186 host->pwr_reg_add |= MCI_ST_CMDDIREN; in mmci_of_parse()
2187 if (of_property_read_bool(np, "st,sig-pin-fbclk")) in mmci_of_parse()
2188 host->pwr_reg_add |= MCI_ST_FBCLKEN; in mmci_of_parse()
2189 if (of_property_read_bool(np, "st,sig-dir")) in mmci_of_parse()
2190 host->pwr_reg_add |= MCI_STM32_DIRPOL; in mmci_of_parse()
2191 if (of_property_read_bool(np, "st,neg-edge")) in mmci_of_parse()
2192 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; in mmci_of_parse()
2193 if (of_property_read_bool(np, "st,use-ckin")) in mmci_of_parse()
2196 if (of_property_read_bool(np, "mmc-cap-mmc-highspeed")) in mmci_of_parse()
2197 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; in mmci_of_parse()
2198 if (of_property_read_bool(np, "mmc-cap-sd-highspeed")) in mmci_of_parse()
2199 mmc->caps |= MMC_CAP_SD_HIGHSPEED; in mmci_of_parse()
2207 struct mmci_platform_data *plat = dev->dev.platform_data; in mmci_probe()
2208 struct device_node *np = dev->dev.of_node; in mmci_probe()
2209 struct variant_data *variant = id->data; in mmci_probe()
2216 dev_err(&dev->dev, "No plat data or DT found\n"); in mmci_probe()
2217 return -EINVAL; in mmci_probe()
2221 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); in mmci_probe()
2223 return -ENOMEM; in mmci_probe()
2226 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); in mmci_probe()
2228 return -ENOMEM; in mmci_probe()
2231 host->mmc = mmc; in mmci_probe()
2232 host->mmc_ops = &mmci_ops; in mmci_probe()
2233 mmc->ops = &mmci_ops; in mmci_probe()
2243 if (!variant->opendrain) { in mmci_probe()
2244 host->pinctrl = devm_pinctrl_get(&dev->dev); in mmci_probe()
2245 if (IS_ERR(host->pinctrl)) { in mmci_probe()
2246 dev_err(&dev->dev, "failed to get pinctrl"); in mmci_probe()
2247 ret = PTR_ERR(host->pinctrl); in mmci_probe()
2251 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, in mmci_probe()
2253 if (IS_ERR(host->pins_opendrain)) { in mmci_probe()
2255 ret = PTR_ERR(host->pins_opendrain); in mmci_probe()
2260 host->hw_designer = amba_manf(dev); in mmci_probe()
2261 host->hw_revision = amba_rev(dev); in mmci_probe()
2262 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); in mmci_probe()
2263 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); in mmci_probe()
2265 host->clk = devm_clk_get(&dev->dev, NULL); in mmci_probe()
2266 if (IS_ERR(host->clk)) { in mmci_probe()
2267 ret = PTR_ERR(host->clk); in mmci_probe()
2271 ret = clk_prepare_enable(host->clk); in mmci_probe()
2275 if (variant->qcom_fifo) in mmci_probe()
2276 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; in mmci_probe()
2278 host->get_rx_fifocnt = mmci_get_rx_fifocnt; in mmci_probe()
2280 host->plat = plat; in mmci_probe()
2281 host->variant = variant; in mmci_probe()
2282 host->mclk = clk_get_rate(host->clk); in mmci_probe()
2288 if (host->mclk > variant->f_max) { in mmci_probe()
2289 ret = clk_set_rate(host->clk, variant->f_max); in mmci_probe()
2292 host->mclk = clk_get_rate(host->clk); in mmci_probe()
2294 host->mclk); in mmci_probe()
2297 host->phybase = dev->res.start; in mmci_probe()
2298 host->base = devm_ioremap_resource(&dev->dev, &dev->res); in mmci_probe()
2299 if (IS_ERR(host->base)) { in mmci_probe()
2300 ret = PTR_ERR(host->base); in mmci_probe()
2304 if (variant->init) in mmci_probe()
2305 variant->init(host); in mmci_probe()
2313 if (variant->st_clkdiv) in mmci_probe()
2314 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); in mmci_probe()
2315 else if (variant->stm32_clkdiv) in mmci_probe()
2316 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); in mmci_probe()
2317 else if (variant->explicit_mclk_control) in mmci_probe()
2318 mmc->f_min = clk_round_rate(host->clk, 100000); in mmci_probe()
2320 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); in mmci_probe()
2327 if (mmc->f_max) in mmci_probe()
2328 mmc->f_max = variant->explicit_mclk_control ? in mmci_probe()
2329 min(variant->f_max, mmc->f_max) : in mmci_probe()
2330 min(host->mclk, mmc->f_max); in mmci_probe()
2332 mmc->f_max = variant->explicit_mclk_control ? in mmci_probe()
2333 fmax : min(host->mclk, fmax); in mmci_probe()
2336 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); in mmci_probe()
2338 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); in mmci_probe()
2339 if (IS_ERR(host->rst)) { in mmci_probe()
2340 ret = PTR_ERR(host->rst); in mmci_probe()
2343 ret = reset_control_deassert(host->rst); in mmci_probe()
2345 dev_err(mmc_dev(mmc), "failed to de-assert reset\n"); in mmci_probe()
2352 if (!mmc->ocr_avail) in mmci_probe()
2353 mmc->ocr_avail = plat->ocr_mask; in mmci_probe()
2354 else if (plat->ocr_mask) in mmci_probe()
2358 mmc->caps |= MMC_CAP_CMD23; in mmci_probe()
2363 if (variant->busy_detect) { in mmci_probe()
2369 if (variant->busy_dpsm_flag) in mmci_probe()
2371 host->variant->busy_dpsm_flag); in mmci_probe()
2372 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in mmci_probe()
2375 if (variant->supports_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ) { in mmci_probe()
2376 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in mmci_probe()
2382 host->variant->datactrl_mask_sdio); in mmci_probe()
2386 if (variant->busy_timeout) in mmci_probe()
2387 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; in mmci_probe()
2389 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ in mmci_probe()
2390 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; in mmci_probe()
2391 host->stop_abort.arg = 0; in mmci_probe()
2392 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; in mmci_probe()
2395 mmc->pm_caps |= MMC_PM_KEEP_POWER; in mmci_probe()
2400 mmc->max_segs = NR_SG; in mmci_probe()
2404 * register, we must ensure that we don't exceed 2^num-1 bytes in a in mmci_probe()
2407 mmc->max_req_size = (1 << variant->datalength_bits) - 1; in mmci_probe()
2413 mmc->max_seg_size = mmc->max_req_size; in mmci_probe()
2418 mmc->max_blk_size = 1 << variant->datactrl_blocksz; in mmci_probe()
2424 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; in mmci_probe()
2426 spin_lock_init(&host->lock); in mmci_probe()
2428 writel(0, host->base + MMCIMASK0); in mmci_probe()
2430 if (variant->mmcimask1) in mmci_probe()
2431 writel(0, host->base + MMCIMASK1); in mmci_probe()
2433 writel(0xfff, host->base + MMCICLEAR); in mmci_probe()
2437 * - not using DT but using a descriptor table, or in mmci_probe()
2438 * - using a table of descriptors ALONGSIDE DT, or in mmci_probe()
2444 if (ret == -EPROBE_DEFER) in mmci_probe()
2448 if (ret == -EPROBE_DEFER) in mmci_probe()
2452 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, in mmci_probe()
2458 if (!dev->irq[1]) in mmci_probe()
2459 host->singleirq = true; in mmci_probe()
2461 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, in mmci_probe()
2467 if (host->variant->busy_detect) in mmci_probe()
2468 INIT_DELAYED_WORK(&host->ux500_busy_timeout_work, in mmci_probe()
2471 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); in mmci_probe()
2475 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", in mmci_probe()
2477 amba_rev(dev), (unsigned long long)dev->res.start, in mmci_probe()
2478 dev->irq[0], dev->irq[1]); in mmci_probe()
2482 pm_runtime_set_autosuspend_delay(&dev->dev, 50); in mmci_probe()
2483 pm_runtime_use_autosuspend(&dev->dev); in mmci_probe()
2489 pm_runtime_put(&dev->dev); in mmci_probe()
2493 clk_disable_unprepare(host->clk); in mmci_probe()
2505 struct variant_data *variant = host->variant; in mmci_remove()
2511 pm_runtime_get_sync(&dev->dev); in mmci_remove()
2515 writel(0, host->base + MMCIMASK0); in mmci_remove()
2517 if (variant->mmcimask1) in mmci_remove()
2518 writel(0, host->base + MMCIMASK1); in mmci_remove()
2520 writel(0, host->base + MMCICOMMAND); in mmci_remove()
2521 writel(0, host->base + MMCIDATACTRL); in mmci_remove()
2524 clk_disable_unprepare(host->clk); in mmci_remove()
2534 spin_lock_irqsave(&host->lock, flags); in mmci_save()
2536 writel(0, host->base + MMCIMASK0); in mmci_save()
2537 if (host->variant->pwrreg_nopower) { in mmci_save()
2538 writel(0, host->base + MMCIDATACTRL); in mmci_save()
2539 writel(0, host->base + MMCIPOWER); in mmci_save()
2540 writel(0, host->base + MMCICLOCK); in mmci_save()
2544 spin_unlock_irqrestore(&host->lock, flags); in mmci_save()
2551 spin_lock_irqsave(&host->lock, flags); in mmci_restore()
2553 if (host->variant->pwrreg_nopower) { in mmci_restore()
2554 writel(host->clk_reg, host->base + MMCICLOCK); in mmci_restore()
2555 writel(host->datactrl_reg, host->base + MMCIDATACTRL); in mmci_restore()
2556 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_restore()
2558 writel(MCI_IRQENABLE | host->variant->start_err, in mmci_restore()
2559 host->base + MMCIMASK0); in mmci_restore()
2562 spin_unlock_irqrestore(&host->lock, flags); in mmci_restore()
2574 clk_disable_unprepare(host->clk); in mmci_runtime_suspend()
2587 clk_prepare_enable(host->clk); in mmci_runtime_resume()