Lines Matching +full:idma +full:- +full:addr
1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/dma-mapping.h>
38 #include <linux/mmc/slot-gpio.h>
73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81 u32 des6; /* Lower 32-bits of Next Descriptor Address */
82 u32 des7; /* Upper 32-bits of Next Descriptor Address */
97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
110 struct dw_mci_slot *slot = s->private; in dw_mci_req_show()
117 spin_lock_bh(&slot->host->lock); in dw_mci_req_show()
118 mrq = slot->mrq; in dw_mci_req_show()
121 cmd = mrq->cmd; in dw_mci_req_show()
122 data = mrq->data; in dw_mci_req_show()
123 stop = mrq->stop; in dw_mci_req_show()
128 cmd->opcode, cmd->arg, cmd->flags, in dw_mci_req_show()
129 cmd->resp[0], cmd->resp[1], cmd->resp[2], in dw_mci_req_show()
130 cmd->resp[2], cmd->error); in dw_mci_req_show()
133 data->bytes_xfered, data->blocks, in dw_mci_req_show()
134 data->blksz, data->flags, data->error); in dw_mci_req_show()
138 stop->opcode, stop->arg, stop->flags, in dw_mci_req_show()
139 stop->resp[0], stop->resp[1], stop->resp[2], in dw_mci_req_show()
140 stop->resp[2], stop->error); in dw_mci_req_show()
143 spin_unlock_bh(&slot->host->lock); in dw_mci_req_show()
151 struct dw_mci *host = s->private; in dw_mci_regs_show()
153 pm_runtime_get_sync(host->dev); in dw_mci_regs_show()
162 pm_runtime_put_autosuspend(host->dev); in dw_mci_regs_show()
170 struct mmc_host *mmc = slot->mmc; in dw_mci_init_debugfs()
171 struct dw_mci *host = slot->host; in dw_mci_init_debugfs()
174 root = mmc->debugfs_root; in dw_mci_init_debugfs()
180 debugfs_create_u32("state", S_IRUSR, root, &host->state); in dw_mci_init_debugfs()
182 &host->pending_events); in dw_mci_init_debugfs()
184 &host->completed_events); in dw_mci_init_debugfs()
186 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc); in dw_mci_init_debugfs()
200 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, in dw_mci_ctrl_reset()
203 dev_err(host->dev, in dw_mci_ctrl_reset()
226 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_wait_while_busy()
230 dev_err(host->dev, "Busy; trying anyway\n"); in dw_mci_wait_while_busy()
236 struct dw_mci *host = slot->host; in mci_send_cmd()
244 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, in mci_send_cmd()
247 dev_err(&slot->mmc->class_dev, in mci_send_cmd()
255 struct dw_mci *host = slot->host; in dw_mci_prepare_command()
258 cmd->error = -EINPROGRESS; in dw_mci_prepare_command()
259 cmdr = cmd->opcode; in dw_mci_prepare_command()
261 if (cmd->opcode == MMC_STOP_TRANSMISSION || in dw_mci_prepare_command()
262 cmd->opcode == MMC_GO_IDLE_STATE || in dw_mci_prepare_command()
263 cmd->opcode == MMC_GO_INACTIVE_STATE || in dw_mci_prepare_command()
264 (cmd->opcode == SD_IO_RW_DIRECT && in dw_mci_prepare_command()
265 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) in dw_mci_prepare_command()
267 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) in dw_mci_prepare_command()
270 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in dw_mci_prepare_command()
277 WARN_ON(slot->host->state != STATE_SENDING_CMD); in dw_mci_prepare_command()
278 slot->host->state = STATE_SENDING_CMD11; in dw_mci_prepare_command()
288 * ever called with a non-zero clock. That shouldn't happen in dw_mci_prepare_command()
292 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); in dw_mci_prepare_command()
298 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_prepare_command()
301 if (cmd->flags & MMC_RSP_136) in dw_mci_prepare_command()
305 if (cmd->flags & MMC_RSP_CRC) in dw_mci_prepare_command()
308 if (cmd->data) { in dw_mci_prepare_command()
310 if (cmd->data->flags & MMC_DATA_WRITE) in dw_mci_prepare_command()
314 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) in dw_mci_prepare_command()
325 if (!cmd->data) in dw_mci_prep_stop_abort()
328 stop = &host->stop_abort; in dw_mci_prep_stop_abort()
329 cmdr = cmd->opcode; in dw_mci_prep_stop_abort()
338 stop->opcode = MMC_STOP_TRANSMISSION; in dw_mci_prep_stop_abort()
339 stop->arg = 0; in dw_mci_prep_stop_abort()
340 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; in dw_mci_prep_stop_abort()
342 stop->opcode = SD_IO_RW_DIRECT; in dw_mci_prep_stop_abort()
343 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | in dw_mci_prep_stop_abort()
344 ((cmd->arg >> 28) & 0x7); in dw_mci_prep_stop_abort()
345 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; in dw_mci_prep_stop_abort()
350 cmdr = stop->opcode | SDMMC_CMD_STOP | in dw_mci_prep_stop_abort()
353 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) in dw_mci_prep_stop_abort()
372 host->bus_hz); in dw_mci_set_cto()
390 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_cto()
391 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_set_cto()
392 mod_timer(&host->cto_timer, in dw_mci_set_cto()
394 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_cto()
400 host->cmd = cmd; in dw_mci_start_command()
401 dev_vdbg(host->dev, in dw_mci_start_command()
403 cmd->arg, cmd_flags); in dw_mci_start_command()
405 mci_writel(host, CMDARG, cmd->arg); in dw_mci_start_command()
418 struct mmc_command *stop = &host->stop_abort; in send_stop_abort()
420 dw_mci_start_command(host, stop, host->stop_cmdr); in send_stop_abort()
426 if (host->using_dma) { in dw_mci_stop_dma()
427 host->dma_ops->stop(host); in dw_mci_stop_dma()
428 host->dma_ops->cleanup(host); in dw_mci_stop_dma()
432 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_stop_dma()
437 struct mmc_data *data = host->data; in dw_mci_dma_cleanup()
439 if (data && data->host_cookie == COOKIE_MAPPED) { in dw_mci_dma_cleanup()
440 dma_unmap_sg(host->dev, in dw_mci_dma_cleanup()
441 data->sg, in dw_mci_dma_cleanup()
442 data->sg_len, in dw_mci_dma_cleanup()
444 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_dma_cleanup()
476 struct mmc_data *data = host->data; in dw_mci_dmac_complete_dma()
478 dev_vdbg(host->dev, "DMA complete\n"); in dw_mci_dmac_complete_dma()
480 if ((host->use_dma == TRANS_MODE_EDMAC) && in dw_mci_dmac_complete_dma()
481 data && (data->flags & MMC_DATA_READ)) in dw_mci_dmac_complete_dma()
483 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), in dw_mci_dmac_complete_dma()
484 data->sg, in dw_mci_dmac_complete_dma()
485 data->sg_len, in dw_mci_dmac_complete_dma()
488 host->dma_ops->cleanup(host); in dw_mci_dmac_complete_dma()
495 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_dmac_complete_dma()
496 queue_work(system_bh_wq, &host->bh_work); in dw_mci_dmac_complete_dma()
504 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
507 host->ring_size = in dw_mci_idmac_init()
511 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; in dw_mci_idmac_init()
513 p->des6 = (host->sg_dma + in dw_mci_idmac_init()
517 p->des7 = (u64)(host->sg_dma + in dw_mci_idmac_init()
521 p->des0 = 0; in dw_mci_idmac_init()
522 p->des1 = 0; in dw_mci_idmac_init()
523 p->des2 = 0; in dw_mci_idmac_init()
524 p->des3 = 0; in dw_mci_idmac_init()
527 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
528 p->des6 = host->sg_dma & 0xffffffff; in dw_mci_idmac_init()
529 p->des7 = (u64)host->sg_dma >> 32; in dw_mci_idmac_init()
530 p->des0 = IDMAC_DES0_ER; in dw_mci_idmac_init()
535 host->ring_size = in dw_mci_idmac_init()
539 for (i = 0, p = host->sg_cpu; in dw_mci_idmac_init()
540 i < host->ring_size - 1; in dw_mci_idmac_init()
542 p->des3 = cpu_to_le32(host->sg_dma + in dw_mci_idmac_init()
544 p->des0 = 0; in dw_mci_idmac_init()
545 p->des1 = 0; in dw_mci_idmac_init()
548 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
549 p->des3 = cpu_to_le32(host->sg_dma); in dw_mci_idmac_init()
550 p->des0 = cpu_to_le32(IDMAC_DES0_ER); in dw_mci_idmac_init()
555 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
556 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
562 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); in dw_mci_idmac_init()
563 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); in dw_mci_idmac_init()
566 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
572 mci_writel(host, DBADDR, host->sg_dma); in dw_mci_idmac_init()
587 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc64()
590 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc64()
592 u64 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc64()
598 length -= desc_len; in dw_mci_prepare_desc64()
606 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc64()
615 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | in dw_mci_prepare_desc64()
622 desc->des4 = mem_addr & 0xffffffff; in dw_mci_prepare_desc64()
623 desc->des5 = mem_addr >> 32; in dw_mci_prepare_desc64()
634 desc_first->des0 |= IDMAC_DES0_FD; in dw_mci_prepare_desc64()
637 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); in dw_mci_prepare_desc64()
638 desc_last->des0 |= IDMAC_DES0_LD; in dw_mci_prepare_desc64()
643 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc64()
644 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc64()
646 return -EINVAL; in dw_mci_prepare_desc64()
659 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc32()
662 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc32()
664 u32 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc32()
670 length -= desc_len; in dw_mci_prepare_desc32()
678 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc32()
688 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | in dw_mci_prepare_desc32()
696 desc->des2 = cpu_to_le32(mem_addr); in dw_mci_prepare_desc32()
707 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); in dw_mci_prepare_desc32()
710 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | in dw_mci_prepare_desc32()
712 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); in dw_mci_prepare_desc32()
717 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc32()
718 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc32()
720 return -EINVAL; in dw_mci_prepare_desc32()
728 if (host->dma_64bit_address == 1) in dw_mci_idmac_start_dma()
729 ret = dw_mci_prepare_desc64(host, host->data, sg_len); in dw_mci_idmac_start_dma()
731 ret = dw_mci_prepare_desc32(host, host->data, sg_len); in dw_mci_idmac_start_dma()
773 dmaengine_terminate_async(host->dms->ch); in dw_mci_edmac_stop_dma()
781 struct scatterlist *sgl = host->data->sg; in dw_mci_edmac_start_dma()
783 u32 sg_elems = host->data->sg_len; in dw_mci_edmac_start_dma()
785 u32 fifo_offset = host->fifo_reg - host->regs; in dw_mci_edmac_start_dma()
790 cfg.dst_addr = host->phy_regs + fifo_offset; in dw_mci_edmac_start_dma()
800 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
805 ret = dmaengine_slave_config(host->dms->ch, &cfg); in dw_mci_edmac_start_dma()
807 dev_err(host->dev, "Failed to config edmac.\n"); in dw_mci_edmac_start_dma()
808 return -EBUSY; in dw_mci_edmac_start_dma()
811 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, in dw_mci_edmac_start_dma()
815 dev_err(host->dev, "Can't prepare slave sg.\n"); in dw_mci_edmac_start_dma()
816 return -EBUSY; in dw_mci_edmac_start_dma()
820 desc->callback = dw_mci_dmac_complete_dma; in dw_mci_edmac_start_dma()
821 desc->callback_param = (void *)host; in dw_mci_edmac_start_dma()
825 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
826 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, in dw_mci_edmac_start_dma()
829 dma_async_issue_pending(host->dms->ch); in dw_mci_edmac_start_dma()
837 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); in dw_mci_edmac_init()
838 if (!host->dms) in dw_mci_edmac_init()
839 return -ENOMEM; in dw_mci_edmac_init()
841 host->dms->ch = dma_request_chan(host->dev, "rx-tx"); in dw_mci_edmac_init()
842 if (IS_ERR(host->dms->ch)) { in dw_mci_edmac_init()
843 int ret = PTR_ERR(host->dms->ch); in dw_mci_edmac_init()
845 dev_err(host->dev, "Failed to get external DMA channel.\n"); in dw_mci_edmac_init()
846 kfree(host->dms); in dw_mci_edmac_init()
847 host->dms = NULL; in dw_mci_edmac_init()
856 if (host->dms) { in dw_mci_edmac_exit()
857 if (host->dms->ch) { in dw_mci_edmac_exit()
858 dma_release_channel(host->dms->ch); in dw_mci_edmac_exit()
859 host->dms->ch = NULL; in dw_mci_edmac_exit()
861 kfree(host->dms); in dw_mci_edmac_exit()
862 host->dms = NULL; in dw_mci_edmac_exit()
882 if (data->host_cookie == COOKIE_PRE_MAPPED) in dw_mci_pre_dma_transfer()
883 return data->sg_len; in dw_mci_pre_dma_transfer()
887 * non-word-aligned buffers or lengths. Also, we don't bother in dw_mci_pre_dma_transfer()
890 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) in dw_mci_pre_dma_transfer()
891 return -EINVAL; in dw_mci_pre_dma_transfer()
893 if (data->blksz & 3) in dw_mci_pre_dma_transfer()
894 return -EINVAL; in dw_mci_pre_dma_transfer()
896 for_each_sg(data->sg, sg, data->sg_len, i) { in dw_mci_pre_dma_transfer()
897 if (sg->offset & 3 || sg->length & 3) in dw_mci_pre_dma_transfer()
898 return -EINVAL; in dw_mci_pre_dma_transfer()
901 sg_len = dma_map_sg(host->dev, in dw_mci_pre_dma_transfer()
902 data->sg, in dw_mci_pre_dma_transfer()
903 data->sg_len, in dw_mci_pre_dma_transfer()
906 return -EINVAL; in dw_mci_pre_dma_transfer()
908 data->host_cookie = cookie; in dw_mci_pre_dma_transfer()
917 struct mmc_data *data = mrq->data; in dw_mci_pre_req()
919 if (!slot->host->use_dma || !data) in dw_mci_pre_req()
923 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
925 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, in dw_mci_pre_req()
927 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
935 struct mmc_data *data = mrq->data; in dw_mci_post_req()
937 if (!slot->host->use_dma || !data) in dw_mci_post_req()
940 if (data->host_cookie != COOKIE_UNMAPPED) in dw_mci_post_req()
941 dma_unmap_sg(slot->host->dev, in dw_mci_post_req()
942 data->sg, in dw_mci_post_req()
943 data->sg_len, in dw_mci_post_req()
945 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_post_req()
952 struct dw_mci *host = slot->host; in dw_mci_get_cd()
956 if (((mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_get_cd()
960 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { in dw_mci_get_cd()
961 if (mmc->caps & MMC_CAP_NEEDS_POLL) { in dw_mci_get_cd()
962 dev_info(&mmc->class_dev, in dw_mci_get_cd()
965 dev_info(&mmc->class_dev, in dw_mci_get_cd()
966 "card is non-removable.\n"); in dw_mci_get_cd()
968 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); in dw_mci_get_cd()
975 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) in dw_mci_get_cd()
978 spin_lock_bh(&host->lock); in dw_mci_get_cd()
979 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
980 dev_dbg(&mmc->class_dev, "card is present\n"); in dw_mci_get_cd()
982 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
983 dev_dbg(&mmc->class_dev, "card is not present\n"); in dw_mci_get_cd()
984 spin_unlock_bh(&host->lock); in dw_mci_get_cd()
991 unsigned int blksz = data->blksz; in dw_mci_adjust_fifoth()
993 u32 fifo_width = 1 << host->data_shift; in dw_mci_adjust_fifoth()
996 int idx = ARRAY_SIZE(mszs) - 1; in dw_mci_adjust_fifoth()
999 if (!host->use_dma) in dw_mci_adjust_fifoth()
1002 tx_wmark = (host->fifo_depth) / 2; in dw_mci_adjust_fifoth()
1003 tx_wmark_invers = host->fifo_depth - tx_wmark; in dw_mci_adjust_fifoth()
1016 rx_wmark = mszs[idx] - 1; in dw_mci_adjust_fifoth()
1019 } while (--idx > 0); in dw_mci_adjust_fifoth()
1031 unsigned int blksz = data->blksz; in dw_mci_ctrl_thld()
1040 if (host->verid < DW_MMC_240A || in dw_mci_ctrl_thld()
1041 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) in dw_mci_ctrl_thld()
1048 if (data->flags & MMC_DATA_WRITE && in dw_mci_ctrl_thld()
1049 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1052 if (data->flags & MMC_DATA_WRITE) in dw_mci_ctrl_thld()
1057 if (host->timing != MMC_TIMING_MMC_HS200 && in dw_mci_ctrl_thld()
1058 host->timing != MMC_TIMING_UHS_SDR104 && in dw_mci_ctrl_thld()
1059 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1062 blksz_depth = blksz / (1 << host->data_shift); in dw_mci_ctrl_thld()
1063 fifo_depth = host->fifo_depth; in dw_mci_ctrl_thld()
1087 host->using_dma = 0; in dw_mci_submit_data_dma()
1090 if (!host->use_dma) in dw_mci_submit_data_dma()
1091 return -ENODEV; in dw_mci_submit_data_dma()
1095 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1099 host->using_dma = 1; in dw_mci_submit_data_dma()
1101 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_submit_data_dma()
1102 dev_vdbg(host->dev, in dw_mci_submit_data_dma()
1104 (unsigned long)host->sg_cpu, in dw_mci_submit_data_dma()
1105 (unsigned long)host->sg_dma, in dw_mci_submit_data_dma()
1113 if (host->prev_blksz != data->blksz) in dw_mci_submit_data_dma()
1122 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1126 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1128 if (host->dma_ops->start(host, sg_len)) { in dw_mci_submit_data_dma()
1129 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1131 dev_dbg(host->dev, in dw_mci_submit_data_dma()
1134 return -ENODEV; in dw_mci_submit_data_dma()
1146 data->error = -EINPROGRESS; in dw_mci_submit_data()
1148 WARN_ON(host->data); in dw_mci_submit_data()
1149 host->sg = NULL; in dw_mci_submit_data()
1150 host->data = data; in dw_mci_submit_data()
1152 if (data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1153 host->dir_status = DW_MCI_RECV_STATUS; in dw_mci_submit_data()
1155 host->dir_status = DW_MCI_SEND_STATUS; in dw_mci_submit_data()
1160 if (host->data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1165 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); in dw_mci_submit_data()
1166 host->sg = data->sg; in dw_mci_submit_data()
1167 host->part_buf_start = 0; in dw_mci_submit_data()
1168 host->part_buf_count = 0; in dw_mci_submit_data()
1172 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data()
1176 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data()
1188 if (host->wm_aligned) in dw_mci_submit_data()
1191 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_submit_data()
1192 host->prev_blksz = 0; in dw_mci_submit_data()
1199 host->prev_blksz = data->blksz; in dw_mci_submit_data()
1205 struct dw_mci *host = slot->host; in dw_mci_setup_bus()
1206 unsigned int clock = slot->clock; in dw_mci_setup_bus()
1212 if (host->state == STATE_WAITING_CMD11_DONE) in dw_mci_setup_bus()
1215 slot->mmc->actual_clock = 0; in dw_mci_setup_bus()
1220 } else if (clock != host->current_speed || force_clkinit) { in dw_mci_setup_bus()
1221 div = host->bus_hz / clock; in dw_mci_setup_bus()
1222 if (host->bus_hz % clock && host->bus_hz > clock) in dw_mci_setup_bus()
1225 * over-clocking the card. in dw_mci_setup_bus()
1229 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; in dw_mci_setup_bus()
1231 if ((clock != slot->__clk_old && in dw_mci_setup_bus()
1232 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || in dw_mci_setup_bus()
1236 dev_info(&slot->mmc->class_dev, in dw_mci_setup_bus()
1238 slot->id, host->bus_hz, clock, in dw_mci_setup_bus()
1239 div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1240 host->bus_hz, div); in dw_mci_setup_bus()
1246 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && in dw_mci_setup_bus()
1247 slot->mmc->f_min == clock) in dw_mci_setup_bus()
1248 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); in dw_mci_setup_bus()
1265 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; in dw_mci_setup_bus()
1266 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) in dw_mci_setup_bus()
1267 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_setup_bus()
1274 slot->__clk_old = clock; in dw_mci_setup_bus()
1275 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1276 host->bus_hz; in dw_mci_setup_bus()
1279 host->current_speed = clock; in dw_mci_setup_bus()
1282 mci_writel(host, CTYPE, (slot->ctype << slot->id)); in dw_mci_setup_bus()
1288 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_set_data_timeout()
1292 if (drv_data && drv_data->set_data_timeout) in dw_mci_set_data_timeout()
1293 return drv_data->set_data_timeout(host, timeout_ns); in dw_mci_set_data_timeout()
1299 tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC); in dw_mci_set_data_timeout()
1312 dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x", in dw_mci_set_data_timeout()
1324 mrq = slot->mrq; in __dw_mci_start_request()
1326 host->mrq = mrq; in __dw_mci_start_request()
1328 host->pending_events = 0; in __dw_mci_start_request()
1329 host->completed_events = 0; in __dw_mci_start_request()
1330 host->cmd_status = 0; in __dw_mci_start_request()
1331 host->data_status = 0; in __dw_mci_start_request()
1332 host->dir_status = 0; in __dw_mci_start_request()
1334 data = cmd->data; in __dw_mci_start_request()
1336 dw_mci_set_data_timeout(host, data->timeout_ns); in __dw_mci_start_request()
1337 mci_writel(host, BYTCNT, data->blksz*data->blocks); in __dw_mci_start_request()
1338 mci_writel(host, BLKSIZ, data->blksz); in __dw_mci_start_request()
1341 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); in __dw_mci_start_request()
1344 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) in __dw_mci_start_request()
1354 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in __dw_mci_start_request()
1367 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_start_request()
1368 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in __dw_mci_start_request()
1369 mod_timer(&host->cmd11_timer, in __dw_mci_start_request()
1371 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_start_request()
1374 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); in __dw_mci_start_request()
1380 struct mmc_request *mrq = slot->mrq; in dw_mci_start_request()
1383 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; in dw_mci_start_request()
1387 /* must be called with host->lock held */
1391 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", in dw_mci_queue_request()
1392 host->state); in dw_mci_queue_request()
1394 slot->mrq = mrq; in dw_mci_queue_request()
1396 if (host->state == STATE_WAITING_CMD11_DONE) { in dw_mci_queue_request()
1397 dev_warn(&slot->mmc->class_dev, in dw_mci_queue_request()
1404 host->state = STATE_IDLE; in dw_mci_queue_request()
1407 if (host->state == STATE_IDLE) { in dw_mci_queue_request()
1408 host->state = STATE_SENDING_CMD; in dw_mci_queue_request()
1411 list_add_tail(&slot->queue_node, &host->queue); in dw_mci_queue_request()
1418 struct dw_mci *host = slot->host; in dw_mci_request()
1420 WARN_ON(slot->mrq); in dw_mci_request()
1429 mrq->cmd->error = -ENOMEDIUM; in dw_mci_request()
1434 spin_lock_bh(&host->lock); in dw_mci_request()
1438 spin_unlock_bh(&host->lock); in dw_mci_request()
1444 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; in dw_mci_set_ios()
1448 switch (ios->bus_width) { in dw_mci_set_ios()
1450 slot->ctype = SDMMC_CTYPE_4BIT; in dw_mci_set_ios()
1453 slot->ctype = SDMMC_CTYPE_8BIT; in dw_mci_set_ios()
1457 slot->ctype = SDMMC_CTYPE_1BIT; in dw_mci_set_ios()
1460 regs = mci_readl(slot->host, UHS_REG); in dw_mci_set_ios()
1463 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_set_ios()
1464 ios->timing == MMC_TIMING_UHS_DDR50 || in dw_mci_set_ios()
1465 ios->timing == MMC_TIMING_MMC_HS400) in dw_mci_set_ios()
1466 regs |= ((0x1 << slot->id) << 16); in dw_mci_set_ios()
1468 regs &= ~((0x1 << slot->id) << 16); in dw_mci_set_ios()
1470 mci_writel(slot->host, UHS_REG, regs); in dw_mci_set_ios()
1471 slot->host->timing = ios->timing; in dw_mci_set_ios()
1474 * Use mirror of ios->clock to prevent race with mmc in dw_mci_set_ios()
1477 slot->clock = ios->clock; in dw_mci_set_ios()
1479 if (drv_data && drv_data->set_ios) in dw_mci_set_ios()
1480 drv_data->set_ios(slot->host, ios); in dw_mci_set_ios()
1482 switch (ios->power_mode) { in dw_mci_set_ios()
1484 if (!IS_ERR(mmc->supply.vmmc)) { in dw_mci_set_ios()
1485 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in dw_mci_set_ios()
1486 ios->vdd); in dw_mci_set_ios()
1488 dev_err(slot->host->dev, in dw_mci_set_ios()
1494 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); in dw_mci_set_ios()
1495 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1496 regs |= (1 << slot->id); in dw_mci_set_ios()
1497 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1500 if (!slot->host->vqmmc_enabled) { in dw_mci_set_ios()
1501 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_set_ios()
1502 ret = regulator_enable(mmc->supply.vqmmc); in dw_mci_set_ios()
1504 dev_err(slot->host->dev, in dw_mci_set_ios()
1507 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1511 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1515 dw_mci_ctrl_reset(slot->host, in dw_mci_set_ios()
1527 if (!IS_ERR(mmc->supply.vmmc)) in dw_mci_set_ios()
1528 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in dw_mci_set_ios()
1530 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) in dw_mci_set_ios()
1531 regulator_disable(mmc->supply.vqmmc); in dw_mci_set_ios()
1532 slot->host->vqmmc_enabled = false; in dw_mci_set_ios()
1534 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1535 regs &= ~(1 << slot->id); in dw_mci_set_ios()
1536 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1542 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) in dw_mci_set_ios()
1543 slot->host->state = STATE_IDLE; in dw_mci_set_ios()
1555 status = mci_readl(slot->host, STATUS); in dw_mci_card_busy()
1563 struct dw_mci *host = slot->host; in dw_mci_switch_voltage()
1564 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_switch_voltage()
1566 u32 v18 = SDMMC_UHS_18V << slot->id; in dw_mci_switch_voltage()
1569 if (drv_data && drv_data->switch_voltage) in dw_mci_switch_voltage()
1570 return drv_data->switch_voltage(mmc, ios); in dw_mci_switch_voltage()
1578 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) in dw_mci_switch_voltage()
1583 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_switch_voltage()
1586 dev_dbg(&mmc->class_dev, in dw_mci_switch_voltage()
1587 "Regulator set error %d - %s V\n", in dw_mci_switch_voltage()
1608 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; in dw_mci_get_ro()
1610 dev_dbg(&mmc->class_dev, "card is %s\n", in dw_mci_get_ro()
1611 read_only ? "read-only" : "read-write"); in dw_mci_get_ro()
1619 struct dw_mci *host = slot->host; in dw_mci_hw_reset()
1620 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_hw_reset()
1623 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_hw_reset()
1630 if (drv_data && drv_data->hw_reset) { in dw_mci_hw_reset()
1631 drv_data->hw_reset(host); in dw_mci_hw_reset()
1642 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); in dw_mci_hw_reset()
1645 reset |= SDMMC_RST_HWACTIVE << slot->id; in dw_mci_hw_reset()
1652 struct dw_mci *host = slot->host; in dw_mci_prepare_sdio_irq()
1653 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_prepare_sdio_irq()
1665 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_prepare_sdio_irq()
1668 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_prepare_sdio_irq()
1681 struct dw_mci *host = slot->host; in __dw_mci_enable_sdio_irq()
1685 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1690 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1692 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1695 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1701 struct dw_mci *host = slot->host; in dw_mci_enable_sdio_irq()
1708 pm_runtime_get_noresume(host->dev); in dw_mci_enable_sdio_irq()
1710 pm_runtime_put_noidle(host->dev); in dw_mci_enable_sdio_irq()
1723 struct dw_mci *host = slot->host; in dw_mci_execute_tuning()
1724 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_execute_tuning()
1725 int err = -EINVAL; in dw_mci_execute_tuning()
1727 if (drv_data && drv_data->execute_tuning) in dw_mci_execute_tuning()
1728 err = drv_data->execute_tuning(slot, opcode); in dw_mci_execute_tuning()
1736 struct dw_mci *host = slot->host; in dw_mci_prepare_hs400_tuning()
1737 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_prepare_hs400_tuning()
1739 if (drv_data && drv_data->prepare_hs400_tuning) in dw_mci_prepare_hs400_tuning()
1740 return drv_data->prepare_hs400_tuning(host, ios); in dw_mci_prepare_hs400_tuning()
1753 * the scatter-gather pointer to NULL. in dw_mci_reset()
1755 if (host->sg) { in dw_mci_reset()
1756 sg_miter_stop(&host->sg_miter); in dw_mci_reset()
1757 host->sg = NULL; in dw_mci_reset()
1760 if (host->use_dma) in dw_mci_reset()
1770 if (!host->use_dma) { in dw_mci_reset()
1776 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_reset()
1780 dev_err(host->dev, in dw_mci_reset()
1792 dev_err(host->dev, in dw_mci_reset()
1799 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_reset()
1807 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); in dw_mci_reset()
1834 spin_lock_irqsave(&host->irq_lock, flags); in dw_mci_fault_timer()
1840 if (!host->data_status) { in dw_mci_fault_timer()
1841 host->data_status = SDMMC_INT_DCRC; in dw_mci_fault_timer()
1842 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_fault_timer()
1843 queue_work(system_bh_wq, &host->bh_work); in dw_mci_fault_timer()
1846 spin_unlock_irqrestore(&host->irq_lock, flags); in dw_mci_fault_timer()
1853 struct mmc_data *data = host->data; in dw_mci_start_fault_timer()
1855 if (!data || data->blocks <= 1) in dw_mci_start_fault_timer()
1858 if (!should_fail(&host->fail_data_crc, 1)) in dw_mci_start_fault_timer()
1864 hrtimer_start(&host->fault_timer, in dw_mci_start_fault_timer()
1871 hrtimer_cancel(&host->fault_timer); in dw_mci_stop_fault_timer()
1876 host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER; in dw_mci_init_fault()
1878 hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in dw_mci_init_fault()
1879 host->fault_timer.function = dw_mci_fault_timer; in dw_mci_init_fault()
1896 __releases(&host->lock) in dw_mci_request_end()
1897 __acquires(&host->lock) in dw_mci_request_end()
1900 struct mmc_host *prev_mmc = host->slot->mmc; in dw_mci_request_end()
1902 WARN_ON(host->cmd || host->data); in dw_mci_request_end()
1904 host->slot->mrq = NULL; in dw_mci_request_end()
1905 host->mrq = NULL; in dw_mci_request_end()
1906 if (!list_empty(&host->queue)) { in dw_mci_request_end()
1907 slot = list_entry(host->queue.next, in dw_mci_request_end()
1909 list_del(&slot->queue_node); in dw_mci_request_end()
1910 dev_vdbg(host->dev, "list not empty: %s is next\n", in dw_mci_request_end()
1911 mmc_hostname(slot->mmc)); in dw_mci_request_end()
1912 host->state = STATE_SENDING_CMD; in dw_mci_request_end()
1915 dev_vdbg(host->dev, "list empty\n"); in dw_mci_request_end()
1917 if (host->state == STATE_SENDING_CMD11) in dw_mci_request_end()
1918 host->state = STATE_WAITING_CMD11_DONE; in dw_mci_request_end()
1920 host->state = STATE_IDLE; in dw_mci_request_end()
1923 spin_unlock(&host->lock); in dw_mci_request_end()
1925 spin_lock(&host->lock); in dw_mci_request_end()
1930 u32 status = host->cmd_status; in dw_mci_command_complete()
1932 host->cmd_status = 0; in dw_mci_command_complete()
1935 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_command_complete()
1936 if (cmd->flags & MMC_RSP_136) { in dw_mci_command_complete()
1937 cmd->resp[3] = mci_readl(host, RESP0); in dw_mci_command_complete()
1938 cmd->resp[2] = mci_readl(host, RESP1); in dw_mci_command_complete()
1939 cmd->resp[1] = mci_readl(host, RESP2); in dw_mci_command_complete()
1940 cmd->resp[0] = mci_readl(host, RESP3); in dw_mci_command_complete()
1942 cmd->resp[0] = mci_readl(host, RESP0); in dw_mci_command_complete()
1943 cmd->resp[1] = 0; in dw_mci_command_complete()
1944 cmd->resp[2] = 0; in dw_mci_command_complete()
1945 cmd->resp[3] = 0; in dw_mci_command_complete()
1950 cmd->error = -ETIMEDOUT; in dw_mci_command_complete()
1951 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) in dw_mci_command_complete()
1952 cmd->error = -EILSEQ; in dw_mci_command_complete()
1954 cmd->error = -EIO; in dw_mci_command_complete()
1956 cmd->error = 0; in dw_mci_command_complete()
1958 return cmd->error; in dw_mci_command_complete()
1963 u32 status = host->data_status; in dw_mci_data_complete()
1967 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1969 data->error = -EILSEQ; in dw_mci_data_complete()
1971 if (host->dir_status == in dw_mci_data_complete()
1978 data->bytes_xfered = 0; in dw_mci_data_complete()
1979 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1980 } else if (host->dir_status == in dw_mci_data_complete()
1982 data->error = -EILSEQ; in dw_mci_data_complete()
1986 data->error = -EILSEQ; in dw_mci_data_complete()
1989 dev_dbg(host->dev, "data error, status 0x%08x\n", status); in dw_mci_data_complete()
1997 data->bytes_xfered = data->blocks * data->blksz; in dw_mci_data_complete()
1998 data->error = 0; in dw_mci_data_complete()
2001 return data->error; in dw_mci_data_complete()
2006 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_set_drto()
2012 if (drv_data && drv_data->get_drto_clks) in dw_mci_set_drto()
2013 drto_clks = drv_data->get_drto_clks(host); in dw_mci_set_drto()
2021 host->bus_hz); in dw_mci_set_drto()
2023 dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); in dw_mci_set_drto()
2028 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_drto()
2029 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_set_drto()
2030 mod_timer(&host->dto_timer, in dw_mci_set_drto()
2032 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_drto()
2037 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_cmd_complete()
2047 WARN_ON(del_timer_sync(&host->cto_timer)); in dw_mci_clear_pending_cmd_complete()
2048 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_clear_pending_cmd_complete()
2055 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_data_complete()
2059 WARN_ON(del_timer_sync(&host->dto_timer)); in dw_mci_clear_pending_data_complete()
2060 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_clear_pending_data_complete()
2075 spin_lock(&host->lock); in dw_mci_work_func()
2077 state = host->state; in dw_mci_work_func()
2078 data = host->data; in dw_mci_work_func()
2079 mrq = host->mrq; in dw_mci_work_func()
2094 cmd = host->cmd; in dw_mci_work_func()
2095 host->cmd = NULL; in dw_mci_work_func()
2096 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); in dw_mci_work_func()
2098 if (cmd == mrq->sbc && !err) { in dw_mci_work_func()
2099 __dw_mci_start_request(host, host->slot, in dw_mci_work_func()
2100 mrq->cmd); in dw_mci_work_func()
2104 if (cmd->data && err) { in dw_mci_work_func()
2126 if (err != -ETIMEDOUT && in dw_mci_work_func()
2127 host->dir_status == DW_MCI_RECV_STATUS) { in dw_mci_work_func()
2138 if (!cmd->data || err) { in dw_mci_work_func()
2156 &host->pending_events)) { in dw_mci_work_func()
2157 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_work_func()
2166 &host->pending_events)) { in dw_mci_work_func()
2168 * If all data-related interrupts don't come in dw_mci_work_func()
2171 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_work_func()
2176 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); in dw_mci_work_func()
2192 &host->pending_events)) { in dw_mci_work_func()
2193 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_work_func()
2211 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_work_func()
2217 host->data = NULL; in dw_mci_work_func()
2218 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); in dw_mci_work_func()
2222 if (!data->stop || mrq->sbc) { in dw_mci_work_func()
2223 if (mrq->sbc && data->stop) in dw_mci_work_func()
2224 data->stop->error = 0; in dw_mci_work_func()
2229 /* stop command for open-ended transfer*/ in dw_mci_work_func()
2230 if (data->stop) in dw_mci_work_func()
2243 &host->pending_events)) { in dw_mci_work_func()
2244 host->cmd = NULL; in dw_mci_work_func()
2251 * If err has non-zero, in dw_mci_work_func()
2252 * stop-abort command has been already issued. in dw_mci_work_func()
2263 if (mrq->cmd->error && mrq->data) in dw_mci_work_func()
2267 host->cmd = NULL; in dw_mci_work_func()
2268 host->data = NULL; in dw_mci_work_func()
2270 if (!mrq->sbc && mrq->stop) in dw_mci_work_func()
2271 dw_mci_command_complete(host, mrq->stop); in dw_mci_work_func()
2273 host->cmd_status = 0; in dw_mci_work_func()
2280 &host->pending_events)) in dw_mci_work_func()
2288 host->state = state; in dw_mci_work_func()
2290 spin_unlock(&host->lock); in dw_mci_work_func()
2297 memcpy((void *)&host->part_buf, buf, cnt); in dw_mci_set_part_bytes()
2298 host->part_buf_count = cnt; in dw_mci_set_part_bytes()
2304 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); in dw_mci_push_part_bytes()
2305 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); in dw_mci_push_part_bytes()
2306 host->part_buf_count += cnt; in dw_mci_push_part_bytes()
2313 cnt = min_t(int, cnt, host->part_buf_count); in dw_mci_pull_part_bytes()
2315 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, in dw_mci_pull_part_bytes()
2317 host->part_buf_count -= cnt; in dw_mci_pull_part_bytes()
2318 host->part_buf_start += cnt; in dw_mci_pull_part_bytes()
2326 memcpy(buf, &host->part_buf, cnt); in dw_mci_pull_final_bytes()
2327 host->part_buf_start = cnt; in dw_mci_pull_final_bytes()
2328 host->part_buf_count = (1 << host->data_shift) - cnt; in dw_mci_pull_final_bytes()
2333 struct mmc_data *data = host->data; in dw_mci_push_data16()
2337 if (unlikely(host->part_buf_count)) { in dw_mci_push_data16()
2341 cnt -= len; in dw_mci_push_data16()
2342 if (host->part_buf_count == 2) { in dw_mci_push_data16()
2343 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2344 host->part_buf_count = 0; in dw_mci_push_data16()
2351 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_push_data16()
2357 cnt -= len; in dw_mci_push_data16()
2360 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data16()
2367 for (; cnt >= 2; cnt -= 2) in dw_mci_push_data16()
2368 mci_fifo_writew(host->fifo_reg, *pdata++); in dw_mci_push_data16()
2375 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data16()
2376 (data->blksz * data->blocks)) in dw_mci_push_data16()
2377 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2388 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_pull_data16()
2393 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2397 cnt -= len; in dw_mci_pull_data16()
2404 for (; cnt >= 2; cnt -= 2) in dw_mci_pull_data16()
2405 *pdata++ = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2409 host->part_buf16 = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2416 struct mmc_data *data = host->data; in dw_mci_push_data32()
2420 if (unlikely(host->part_buf_count)) { in dw_mci_push_data32()
2424 cnt -= len; in dw_mci_push_data32()
2425 if (host->part_buf_count == 4) { in dw_mci_push_data32()
2426 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2427 host->part_buf_count = 0; in dw_mci_push_data32()
2434 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_push_data32()
2440 cnt -= len; in dw_mci_push_data32()
2443 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data32()
2450 for (; cnt >= 4; cnt -= 4) in dw_mci_push_data32()
2451 mci_fifo_writel(host->fifo_reg, *pdata++); in dw_mci_push_data32()
2458 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data32()
2459 (data->blksz * data->blocks)) in dw_mci_push_data32()
2460 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2471 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_pull_data32()
2476 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2480 cnt -= len; in dw_mci_pull_data32()
2487 for (; cnt >= 4; cnt -= 4) in dw_mci_pull_data32()
2488 *pdata++ = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2492 host->part_buf32 = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2499 struct mmc_data *data = host->data; in dw_mci_push_data64()
2503 if (unlikely(host->part_buf_count)) { in dw_mci_push_data64()
2507 cnt -= len; in dw_mci_push_data64()
2509 if (host->part_buf_count == 8) { in dw_mci_push_data64()
2510 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2511 host->part_buf_count = 0; in dw_mci_push_data64()
2518 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_push_data64()
2524 cnt -= len; in dw_mci_push_data64()
2527 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data64()
2534 for (; cnt >= 8; cnt -= 8) in dw_mci_push_data64()
2535 mci_fifo_writeq(host->fifo_reg, *pdata++); in dw_mci_push_data64()
2542 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data64()
2543 (data->blksz * data->blocks)) in dw_mci_push_data64()
2544 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2555 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_pull_data64()
2560 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2565 cnt -= len; in dw_mci_pull_data64()
2572 for (; cnt >= 8; cnt -= 8) in dw_mci_pull_data64()
2573 *pdata++ = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2577 host->part_buf = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2591 cnt -= len; in dw_mci_pull_data()
2594 host->pull_data(host, buf, cnt); in dw_mci_pull_data()
2599 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_read_data_pio()
2602 struct mmc_data *data = host->data; in dw_mci_read_data_pio()
2603 int shift = host->data_shift; in dw_mci_read_data_pio()
2612 host->sg = sg_miter->piter.sg; in dw_mci_read_data_pio()
2613 buf = sg_miter->addr; in dw_mci_read_data_pio()
2614 remain = sg_miter->length; in dw_mci_read_data_pio()
2619 << shift) + host->part_buf_count; in dw_mci_read_data_pio()
2624 data->bytes_xfered += len; in dw_mci_read_data_pio()
2626 remain -= len; in dw_mci_read_data_pio()
2629 sg_miter->consumed = offset; in dw_mci_read_data_pio()
2639 sg_miter->consumed = 0; in dw_mci_read_data_pio()
2646 host->sg = NULL; in dw_mci_read_data_pio()
2648 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_read_data_pio()
2653 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_write_data_pio()
2656 struct mmc_data *data = host->data; in dw_mci_write_data_pio()
2657 int shift = host->data_shift; in dw_mci_write_data_pio()
2660 unsigned int fifo_depth = host->fifo_depth; in dw_mci_write_data_pio()
2667 host->sg = sg_miter->piter.sg; in dw_mci_write_data_pio()
2668 buf = sg_miter->addr; in dw_mci_write_data_pio()
2669 remain = sg_miter->length; in dw_mci_write_data_pio()
2673 fcnt = ((fifo_depth - in dw_mci_write_data_pio()
2675 << shift) - host->part_buf_count; in dw_mci_write_data_pio()
2679 host->push_data(host, (void *)(buf + offset), len); in dw_mci_write_data_pio()
2680 data->bytes_xfered += len; in dw_mci_write_data_pio()
2682 remain -= len; in dw_mci_write_data_pio()
2685 sg_miter->consumed = offset; in dw_mci_write_data_pio()
2693 sg_miter->consumed = 0; in dw_mci_write_data_pio()
2700 host->sg = NULL; in dw_mci_write_data_pio()
2702 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_write_data_pio()
2707 del_timer(&host->cto_timer); in dw_mci_cmd_interrupt()
2709 if (!host->cmd_status) in dw_mci_cmd_interrupt()
2710 host->cmd_status = status; in dw_mci_cmd_interrupt()
2714 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd_interrupt()
2715 queue_work(system_bh_wq, &host->bh_work); in dw_mci_cmd_interrupt()
2722 struct dw_mci_slot *slot = host->slot; in dw_mci_handle_cd()
2724 mmc_detect_change(slot->mmc, in dw_mci_handle_cd()
2725 msecs_to_jiffies(host->pdata->detect_delay_ms)); in dw_mci_handle_cd()
2732 struct dw_mci_slot *slot = host->slot; in dw_mci_interrupt()
2734 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_interrupt()
2738 if ((host->state == STATE_SENDING_CMD11) && in dw_mci_interrupt()
2747 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2749 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2751 del_timer(&host->cmd11_timer); in dw_mci_interrupt()
2755 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2757 del_timer(&host->cto_timer); in dw_mci_interrupt()
2759 host->cmd_status = pending; in dw_mci_interrupt()
2761 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2763 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2767 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2769 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) in dw_mci_interrupt()
2770 del_timer(&host->dto_timer); in dw_mci_interrupt()
2774 host->data_status = pending; in dw_mci_interrupt()
2776 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_interrupt()
2778 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) in dw_mci_interrupt()
2781 &host->pending_events); in dw_mci_interrupt()
2783 queue_work(system_bh_wq, &host->bh_work); in dw_mci_interrupt()
2785 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2789 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2791 del_timer(&host->dto_timer); in dw_mci_interrupt()
2794 if (!host->data_status) in dw_mci_interrupt()
2795 host->data_status = pending; in dw_mci_interrupt()
2797 if (host->dir_status == DW_MCI_RECV_STATUS) { in dw_mci_interrupt()
2798 if (host->sg != NULL) in dw_mci_interrupt()
2801 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2802 queue_work(system_bh_wq, &host->bh_work); in dw_mci_interrupt()
2804 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2809 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) in dw_mci_interrupt()
2815 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) in dw_mci_interrupt()
2820 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2825 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2833 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { in dw_mci_interrupt()
2835 SDMMC_INT_SDIO(slot->sdio_id)); in dw_mci_interrupt()
2837 sdio_signal_irq(slot->mmc); in dw_mci_interrupt()
2842 if (host->use_dma != TRANS_MODE_IDMAC) in dw_mci_interrupt()
2845 /* Handle IDMA interrupts */ in dw_mci_interrupt()
2846 if (host->dma_64bit_address == 1) { in dw_mci_interrupt()
2852 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2853 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2861 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2862 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2871 struct dw_mci *host = slot->host; in dw_mci_init_slot_caps()
2872 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_init_slot_caps()
2873 struct mmc_host *mmc = slot->mmc; in dw_mci_init_slot_caps()
2876 if (host->pdata->caps) in dw_mci_init_slot_caps()
2877 mmc->caps = host->pdata->caps; in dw_mci_init_slot_caps()
2879 if (host->pdata->pm_caps) in dw_mci_init_slot_caps()
2880 mmc->pm_caps = host->pdata->pm_caps; in dw_mci_init_slot_caps()
2883 mmc->caps |= drv_data->common_caps; in dw_mci_init_slot_caps()
2885 if (host->dev->of_node) { in dw_mci_init_slot_caps()
2886 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); in dw_mci_init_slot_caps()
2890 ctrl_id = to_platform_device(host->dev)->id; in dw_mci_init_slot_caps()
2893 if (drv_data && drv_data->caps) { in dw_mci_init_slot_caps()
2894 if (ctrl_id >= drv_data->num_caps) { in dw_mci_init_slot_caps()
2895 dev_err(host->dev, "invalid controller id %d\n", in dw_mci_init_slot_caps()
2897 return -EINVAL; in dw_mci_init_slot_caps()
2899 mmc->caps |= drv_data->caps[ctrl_id]; in dw_mci_init_slot_caps()
2902 if (host->pdata->caps2) in dw_mci_init_slot_caps()
2903 mmc->caps2 = host->pdata->caps2; in dw_mci_init_slot_caps()
2906 if (host->minimum_speed) in dw_mci_init_slot_caps()
2907 mmc->f_min = host->minimum_speed; in dw_mci_init_slot_caps()
2909 mmc->f_min = DW_MCI_FREQ_MIN; in dw_mci_init_slot_caps()
2911 if (!mmc->f_max) in dw_mci_init_slot_caps()
2912 mmc->f_max = DW_MCI_FREQ_MAX; in dw_mci_init_slot_caps()
2915 if (mmc->caps & MMC_CAP_SDIO_IRQ) in dw_mci_init_slot_caps()
2916 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in dw_mci_init_slot_caps()
2927 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); in dw_mci_init_slot()
2929 return -ENOMEM; in dw_mci_init_slot()
2932 slot->id = 0; in dw_mci_init_slot()
2933 slot->sdio_id = host->sdio_id0 + slot->id; in dw_mci_init_slot()
2934 slot->mmc = mmc; in dw_mci_init_slot()
2935 slot->host = host; in dw_mci_init_slot()
2936 host->slot = slot; in dw_mci_init_slot()
2938 mmc->ops = &dw_mci_ops; in dw_mci_init_slot()
2945 if (!mmc->ocr_avail) in dw_mci_init_slot()
2946 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; in dw_mci_init_slot()
2957 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_slot()
2958 mmc->max_segs = host->ring_size; in dw_mci_init_slot()
2959 mmc->max_blk_size = 65535; in dw_mci_init_slot()
2960 mmc->max_seg_size = 0x1000; in dw_mci_init_slot()
2961 mmc->max_req_size = mmc->max_seg_size * host->ring_size; in dw_mci_init_slot()
2962 mmc->max_blk_count = mmc->max_req_size / 512; in dw_mci_init_slot()
2963 } else if (host->use_dma == TRANS_MODE_EDMAC) { in dw_mci_init_slot()
2964 mmc->max_segs = 64; in dw_mci_init_slot()
2965 mmc->max_blk_size = 65535; in dw_mci_init_slot()
2966 mmc->max_blk_count = 65535; in dw_mci_init_slot()
2967 mmc->max_req_size = in dw_mci_init_slot()
2968 mmc->max_blk_size * mmc->max_blk_count; in dw_mci_init_slot()
2969 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
2972 mmc->max_segs = 64; in dw_mci_init_slot()
2973 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ in dw_mci_init_slot()
2974 mmc->max_blk_count = 512; in dw_mci_init_slot()
2975 mmc->max_req_size = mmc->max_blk_size * in dw_mci_init_slot()
2976 mmc->max_blk_count; in dw_mci_init_slot()
2977 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
3000 mmc_remove_host(slot->mmc); in dw_mci_cleanup_slot()
3001 slot->host->slot = NULL; in dw_mci_cleanup_slot()
3002 mmc_free_host(slot->mmc); in dw_mci_cleanup_slot()
3008 struct device *dev = host->dev; in dw_mci_init_dma()
3013 * 2b'00: No DMA Interface -> Actually means using Internal DMA block in dw_mci_init_dma()
3014 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block in dw_mci_init_dma()
3015 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block in dw_mci_init_dma()
3016 * 2b'11: Non DW DMA Interface -> pio only in dw_mci_init_dma()
3021 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); in dw_mci_init_dma()
3022 if (host->use_dma == DMA_INTERFACE_IDMA) { in dw_mci_init_dma()
3023 host->use_dma = TRANS_MODE_IDMAC; in dw_mci_init_dma()
3024 } else if (host->use_dma == DMA_INTERFACE_DWDMA || in dw_mci_init_dma()
3025 host->use_dma == DMA_INTERFACE_GDMA) { in dw_mci_init_dma()
3026 host->use_dma = TRANS_MODE_EDMAC; in dw_mci_init_dma()
3032 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_dma()
3040 /* host supports IDMAC in 64-bit address mode */ in dw_mci_init_dma()
3041 host->dma_64bit_address = 1; in dw_mci_init_dma()
3042 dev_info(host->dev, in dw_mci_init_dma()
3043 "IDMAC supports 64-bit address mode.\n"); in dw_mci_init_dma()
3044 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) in dw_mci_init_dma()
3045 dma_set_coherent_mask(host->dev, in dw_mci_init_dma()
3048 /* host supports IDMAC in 32-bit address mode */ in dw_mci_init_dma()
3049 host->dma_64bit_address = 0; in dw_mci_init_dma()
3050 dev_info(host->dev, in dw_mci_init_dma()
3051 "IDMAC supports 32-bit address mode.\n"); in dw_mci_init_dma()
3055 host->sg_cpu = dmam_alloc_coherent(host->dev, in dw_mci_init_dma()
3057 &host->sg_dma, GFP_KERNEL); in dw_mci_init_dma()
3058 if (!host->sg_cpu) { in dw_mci_init_dma()
3059 dev_err(host->dev, in dw_mci_init_dma()
3065 host->dma_ops = &dw_mci_idmac_ops; in dw_mci_init_dma()
3066 dev_info(host->dev, "Using internal DMA controller.\n"); in dw_mci_init_dma()
3069 if ((device_property_string_array_count(dev, "dma-names") < 0) || in dw_mci_init_dma()
3073 host->dma_ops = &dw_mci_edmac_ops; in dw_mci_init_dma()
3074 dev_info(host->dev, "Using external DMA controller.\n"); in dw_mci_init_dma()
3077 if (host->dma_ops->init && host->dma_ops->start && in dw_mci_init_dma()
3078 host->dma_ops->stop && host->dma_ops->cleanup) { in dw_mci_init_dma()
3079 if (host->dma_ops->init(host)) { in dw_mci_init_dma()
3080 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", in dw_mci_init_dma()
3085 dev_err(host->dev, "DMA initialization not found.\n"); in dw_mci_init_dma()
3092 dev_info(host->dev, "Using PIO mode.\n"); in dw_mci_init_dma()
3093 host->use_dma = TRANS_MODE_PIO; in dw_mci_init_dma()
3100 if (host->state != STATE_SENDING_CMD11) { in dw_mci_cmd11_timer()
3101 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); in dw_mci_cmd11_timer()
3105 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cmd11_timer()
3106 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd11_timer()
3107 queue_work(system_bh_wq, &host->bh_work); in dw_mci_cmd11_timer()
3116 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3124 * pending command in the controller--we just assume it will never come. in dw_mci_cto_timer()
3126 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_cto_timer()
3129 dev_warn(host->dev, "Unexpected interrupt latency\n"); in dw_mci_cto_timer()
3132 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { in dw_mci_cto_timer()
3134 dev_warn(host->dev, "CTO timeout when already completed\n"); in dw_mci_cto_timer()
3142 switch (host->state) { in dw_mci_cto_timer()
3151 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cto_timer()
3152 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cto_timer()
3153 queue_work(system_bh_wq, &host->bh_work); in dw_mci_cto_timer()
3156 dev_warn(host->dev, "Unexpected command timeout, state %d\n", in dw_mci_cto_timer()
3157 host->state); in dw_mci_cto_timer()
3162 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3171 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3177 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_dto_timer()
3180 dev_warn(host->dev, "Unexpected data interrupt latency\n"); in dw_mci_dto_timer()
3183 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { in dw_mci_dto_timer()
3185 dev_warn(host->dev, "DTO timeout when already completed\n"); in dw_mci_dto_timer()
3193 switch (host->state) { in dw_mci_dto_timer()
3201 host->data_status = SDMMC_INT_DRTO; in dw_mci_dto_timer()
3202 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_dto_timer()
3203 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_dto_timer()
3204 queue_work(system_bh_wq, &host->bh_work); in dw_mci_dto_timer()
3207 dev_warn(host->dev, "Unexpected data timeout, state %d\n", in dw_mci_dto_timer()
3208 host->state); in dw_mci_dto_timer()
3213 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3220 struct device *dev = host->dev; in dw_mci_parse_dt()
3221 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_parse_dt()
3227 return ERR_PTR(-ENOMEM); in dw_mci_parse_dt()
3230 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); in dw_mci_parse_dt()
3231 if (IS_ERR(pdata->rstc)) in dw_mci_parse_dt()
3232 return ERR_CAST(pdata->rstc); in dw_mci_parse_dt()
3234 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) in dw_mci_parse_dt()
3236 "fifo-depth property not found, using value of FIFOTH register as default\n"); in dw_mci_parse_dt()
3238 device_property_read_u32(dev, "card-detect-delay", in dw_mci_parse_dt()
3239 &pdata->detect_delay_ms); in dw_mci_parse_dt()
3241 device_property_read_u32(dev, "data-addr", &host->data_addr_override); in dw_mci_parse_dt()
3243 if (device_property_present(dev, "fifo-watermark-aligned")) in dw_mci_parse_dt()
3244 host->wm_aligned = true; in dw_mci_parse_dt()
3246 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) in dw_mci_parse_dt()
3247 pdata->bus_hz = clock_frequency; in dw_mci_parse_dt()
3249 if (drv_data && drv_data->parse_dt) { in dw_mci_parse_dt()
3250 ret = drv_data->parse_dt(host); in dw_mci_parse_dt()
3261 return ERR_PTR(-EINVAL); in dw_mci_parse_dt()
3271 * No need for CD if all slots have a non-error GPIO in dw_mci_enable_cd()
3274 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_enable_cd()
3277 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { in dw_mci_enable_cd()
3278 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3282 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3288 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_probe()
3292 if (!host->pdata) { in dw_mci_probe()
3293 host->pdata = dw_mci_parse_dt(host); in dw_mci_probe()
3294 if (IS_ERR(host->pdata)) in dw_mci_probe()
3295 return dev_err_probe(host->dev, PTR_ERR(host->pdata), in dw_mci_probe()
3299 host->biu_clk = devm_clk_get(host->dev, "biu"); in dw_mci_probe()
3300 if (IS_ERR(host->biu_clk)) { in dw_mci_probe()
3301 dev_dbg(host->dev, "biu clock not available\n"); in dw_mci_probe()
3302 ret = PTR_ERR(host->biu_clk); in dw_mci_probe()
3303 if (ret == -EPROBE_DEFER) in dw_mci_probe()
3307 ret = clk_prepare_enable(host->biu_clk); in dw_mci_probe()
3309 dev_err(host->dev, "failed to enable biu clock\n"); in dw_mci_probe()
3314 host->ciu_clk = devm_clk_get(host->dev, "ciu"); in dw_mci_probe()
3315 if (IS_ERR(host->ciu_clk)) { in dw_mci_probe()
3316 dev_dbg(host->dev, "ciu clock not available\n"); in dw_mci_probe()
3317 ret = PTR_ERR(host->ciu_clk); in dw_mci_probe()
3318 if (ret == -EPROBE_DEFER) in dw_mci_probe()
3321 host->bus_hz = host->pdata->bus_hz; in dw_mci_probe()
3323 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_probe()
3325 dev_err(host->dev, "failed to enable ciu clock\n"); in dw_mci_probe()
3329 if (host->pdata->bus_hz) { in dw_mci_probe()
3330 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); in dw_mci_probe()
3332 dev_warn(host->dev, in dw_mci_probe()
3334 host->pdata->bus_hz); in dw_mci_probe()
3336 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_probe()
3339 if (!host->bus_hz) { in dw_mci_probe()
3340 dev_err(host->dev, in dw_mci_probe()
3342 ret = -ENODEV; in dw_mci_probe()
3346 if (host->pdata->rstc) { in dw_mci_probe()
3347 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3349 reset_control_deassert(host->pdata->rstc); in dw_mci_probe()
3352 if (drv_data && drv_data->init) { in dw_mci_probe()
3353 ret = drv_data->init(host); in dw_mci_probe()
3355 dev_err(host->dev, in dw_mci_probe()
3361 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); in dw_mci_probe()
3362 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); in dw_mci_probe()
3363 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); in dw_mci_probe()
3365 spin_lock_init(&host->lock); in dw_mci_probe()
3366 spin_lock_init(&host->irq_lock); in dw_mci_probe()
3367 INIT_LIST_HEAD(&host->queue); in dw_mci_probe()
3372 * Get the host data width - this assumes that HCON has been set with in dw_mci_probe()
3377 host->push_data = dw_mci_push_data16; in dw_mci_probe()
3378 host->pull_data = dw_mci_pull_data16; in dw_mci_probe()
3380 host->data_shift = 1; in dw_mci_probe()
3382 host->push_data = dw_mci_push_data64; in dw_mci_probe()
3383 host->pull_data = dw_mci_pull_data64; in dw_mci_probe()
3385 host->data_shift = 3; in dw_mci_probe()
3390 "Defaulting to 32-bit access.\n"); in dw_mci_probe()
3391 host->push_data = dw_mci_push_data32; in dw_mci_probe()
3392 host->pull_data = dw_mci_pull_data32; in dw_mci_probe()
3394 host->data_shift = 2; in dw_mci_probe()
3399 ret = -ENODEV; in dw_mci_probe()
3403 host->dma_ops = host->pdata->dma_ops; in dw_mci_probe()
3414 * FIFO threshold settings RxMark = fifo_size / 2 - 1, in dw_mci_probe()
3417 if (!host->pdata->fifo_depth) { in dw_mci_probe()
3419 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may in dw_mci_probe()
3427 fifo_size = host->pdata->fifo_depth; in dw_mci_probe()
3429 host->fifo_depth = fifo_size; in dw_mci_probe()
3430 host->fifoth_val = in dw_mci_probe()
3431 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); in dw_mci_probe()
3432 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_probe()
3440 * Need to check the version-id and set data-offset for DATA register. in dw_mci_probe()
3442 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); in dw_mci_probe()
3443 dev_info(host->dev, "Version ID is %04x\n", host->verid); in dw_mci_probe()
3445 if (host->data_addr_override) in dw_mci_probe()
3446 host->fifo_reg = host->regs + host->data_addr_override; in dw_mci_probe()
3447 else if (host->verid < DW_MMC_240A) in dw_mci_probe()
3448 host->fifo_reg = host->regs + DATA_OFFSET; in dw_mci_probe()
3450 host->fifo_reg = host->regs + DATA_240A_OFFSET; in dw_mci_probe()
3452 INIT_WORK(&host->bh_work, dw_mci_work_func); in dw_mci_probe()
3453 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, in dw_mci_probe()
3454 host->irq_flags, "dw-mci", host); in dw_mci_probe()
3468 dev_info(host->dev, in dw_mci_probe()
3470 host->irq, width, fifo_size); in dw_mci_probe()
3475 dev_dbg(host->dev, "slot %d init failed\n", i); in dw_mci_probe()
3485 if (host->use_dma && host->dma_ops->exit) in dw_mci_probe()
3486 host->dma_ops->exit(host); in dw_mci_probe()
3488 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3491 clk_disable_unprepare(host->ciu_clk); in dw_mci_probe()
3494 clk_disable_unprepare(host->biu_clk); in dw_mci_probe()
3502 dev_dbg(host->dev, "remove slot\n"); in dw_mci_remove()
3503 if (host->slot) in dw_mci_remove()
3504 dw_mci_cleanup_slot(host->slot); in dw_mci_remove()
3513 if (host->use_dma && host->dma_ops->exit) in dw_mci_remove()
3514 host->dma_ops->exit(host); in dw_mci_remove()
3516 reset_control_assert(host->pdata->rstc); in dw_mci_remove()
3518 clk_disable_unprepare(host->ciu_clk); in dw_mci_remove()
3519 clk_disable_unprepare(host->biu_clk); in dw_mci_remove()
3530 if (host->use_dma && host->dma_ops->exit) in dw_mci_runtime_suspend()
3531 host->dma_ops->exit(host); in dw_mci_runtime_suspend()
3533 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_suspend()
3535 if (host->slot && in dw_mci_runtime_suspend()
3536 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_suspend()
3537 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_suspend()
3538 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_suspend()
3549 if (host->slot && in dw_mci_runtime_resume()
3550 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3551 !mmc_card_is_removable(host->slot->mmc))) { in dw_mci_runtime_resume()
3552 ret = clk_prepare_enable(host->biu_clk); in dw_mci_runtime_resume()
3557 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_runtime_resume()
3562 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_resume()
3563 ret = -ENODEV; in dw_mci_runtime_resume()
3567 if (host->use_dma && host->dma_ops->init) in dw_mci_runtime_resume()
3568 host->dma_ops->init(host); in dw_mci_runtime_resume()
3574 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_runtime_resume()
3575 host->prev_blksz = 0; in dw_mci_runtime_resume()
3587 if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) in dw_mci_runtime_resume()
3588 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); in dw_mci_runtime_resume()
3591 dw_mci_setup_bus(host->slot, true); in dw_mci_runtime_resume()
3593 /* Re-enable SDIO interrupts. */ in dw_mci_runtime_resume()
3594 if (sdio_irq_claimed(host->slot->mmc)) in dw_mci_runtime_resume()
3595 __dw_mci_enable_sdio_irq(host->slot, 1); in dw_mci_runtime_resume()
3603 if (host->slot && in dw_mci_runtime_resume()
3604 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3605 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_resume()
3606 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_resume()