50 	/* Constant signal, no measurable phase shift */  in rockchip_mmc_get_internal_phase()
96 	 * MMC host to the card, which expects the phase clock inherits  in rockchip_mmc_set_internal_phase()
216 	 * Set the drive phase offset based on speed mode to achieve hold times.  in dw_mci_rk3288_set_ios()
242 		int phase;  in dw_mci_rk3288_set_ios()  local
245 		 * In almost all cases a 90 degree phase offset will provide  in dw_mci_rk3288_set_ios()
250 		phase = 90;  in dw_mci_rk3288_set_ios()
256 			 * bus width is 8 we need to double the phase offset  in dw_mci_rk3288_set_ios()
260 				phase = 180;  in dw_mci_rk3288_set_ios()
272 			phase = 180;  in dw_mci_rk3288_set_ios()
276 		rockchip_mmc_set_phase(host, false, phase);  in dw_mci_rk3288_set_ios()
300 	int phase;  in dw_mci_rk3288_execute_tuning()  local
312 	/* Try each phase and extract good ranges */  in dw_mci_rk3288_execute_tuning()
365 		dev_info(host->dev, "All phases work, using default phase %d.",  in dw_mci_rk3288_execute_tuning()
382 		dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",  in dw_mci_rk3288_execute_tuning()
391 	dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",  in dw_mci_rk3288_execute_tuning()
401 	phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases);  in dw_mci_rk3288_execute_tuning()
402 	dev_info(host->dev, "Successfully tuned phase to %d\n", phase);  in dw_mci_rk3288_execute_tuning()
404 	rockchip_mmc_set_phase(host, true, phase);  in dw_mci_rk3288_execute_tuning()
424 	if (of_property_read_u32(np, "rockchip,default-sample-phase",  in dw_mci_common_parse_dt()