Lines Matching +full:rom +full:- +full:val
1 // SPDX-License-Identifier: GPL-2.0-only
24 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
25 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
30 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
32 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
35 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
47 /* CM-iTC */
58 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
59 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
65 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
86 * struct pch_phub_reg - PHUB register structure
87 * @phub_id_reg: PHUB_ID register val
88 * @q_pri_val_reg: QUEUE_PRI_VAL register val
89 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val
90 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val
91 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val
92 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val
93 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val
94 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val
95 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val
96 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val
97 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val
98 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val
99 * @clkcfg_reg: CLK CFG register val
102 * @pch_phub_extrom_base_address: external rom base address
104 * @pch_opt_rom_start_address: Option ROM start address
137 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
147 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
151 /* pch_phub_save_reg_conf - saves register configuration */
157 void __iomem *p = chip->pch_phub_base_address;
159 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
160 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
161 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
162 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
163 chip->comp_resp_timeout_reg =
165 chip->bus_slave_control_reg =
167 chip->deadlock_avoid_type_reg =
169 chip->intpin_reg_wpermit_reg0 =
171 chip->intpin_reg_wpermit_reg1 =
173 chip->intpin_reg_wpermit_reg2 =
175 chip->intpin_reg_wpermit_reg3 =
177 dev_dbg(&pdev->dev, "%s : "
178 "chip->phub_id_reg=%x, "
179 "chip->q_pri_val_reg=%x, "
180 "chip->rc_q_maxsize_reg=%x, "
181 "chip->bri_q_maxsize_reg=%x, "
182 "chip->comp_resp_timeout_reg=%x, "
183 "chip->bus_slave_control_reg=%x, "
184 "chip->deadlock_avoid_type_reg=%x, "
185 "chip->intpin_reg_wpermit_reg0=%x, "
186 "chip->intpin_reg_wpermit_reg1=%x, "
187 "chip->intpin_reg_wpermit_reg2=%x, "
188 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
189 chip->phub_id_reg,
190 chip->q_pri_val_reg,
191 chip->rc_q_maxsize_reg,
192 chip->bri_q_maxsize_reg,
193 chip->comp_resp_timeout_reg,
194 chip->bus_slave_control_reg,
195 chip->deadlock_avoid_type_reg,
196 chip->intpin_reg_wpermit_reg0,
197 chip->intpin_reg_wpermit_reg1,
198 chip->intpin_reg_wpermit_reg2,
199 chip->intpin_reg_wpermit_reg3);
201 chip->int_reduce_control_reg[i] =
203 dev_dbg(&pdev->dev, "%s : "
204 "chip->int_reduce_control_reg[%d]=%x\n",
205 __func__, i, chip->int_reduce_control_reg[i]);
207 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
208 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
209 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
212 /* pch_phub_restore_reg_conf - restore register configuration */
218 p = chip->pch_phub_base_address;
220 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
221 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
222 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
223 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
224 iowrite32(chip->comp_resp_timeout_reg,
226 iowrite32(chip->bus_slave_control_reg,
228 iowrite32(chip->deadlock_avoid_type_reg,
230 iowrite32(chip->intpin_reg_wpermit_reg0,
232 iowrite32(chip->intpin_reg_wpermit_reg1,
234 iowrite32(chip->intpin_reg_wpermit_reg2,
236 iowrite32(chip->intpin_reg_wpermit_reg3,
238 dev_dbg(&pdev->dev, "%s : "
239 "chip->phub_id_reg=%x, "
240 "chip->q_pri_val_reg=%x, "
241 "chip->rc_q_maxsize_reg=%x, "
242 "chip->bri_q_maxsize_reg=%x, "
243 "chip->comp_resp_timeout_reg=%x, "
244 "chip->bus_slave_control_reg=%x, "
245 "chip->deadlock_avoid_type_reg=%x, "
246 "chip->intpin_reg_wpermit_reg0=%x, "
247 "chip->intpin_reg_wpermit_reg1=%x, "
248 "chip->intpin_reg_wpermit_reg2=%x, "
249 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
250 chip->phub_id_reg,
251 chip->q_pri_val_reg,
252 chip->rc_q_maxsize_reg,
253 chip->bri_q_maxsize_reg,
254 chip->comp_resp_timeout_reg,
255 chip->bus_slave_control_reg,
256 chip->deadlock_avoid_type_reg,
257 chip->intpin_reg_wpermit_reg0,
258 chip->intpin_reg_wpermit_reg1,
259 chip->intpin_reg_wpermit_reg2,
260 chip->intpin_reg_wpermit_reg3);
262 iowrite32(chip->int_reduce_control_reg[i],
264 dev_dbg(&pdev->dev, "%s : "
265 "chip->int_reduce_control_reg[%d]=%x\n",
266 __func__, i, chip->int_reduce_control_reg[i]);
269 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
270 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
271 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
275 * pch_phub_read_serial_rom() - Reading Serial ROM
277 * @offset_address: Serial ROM offset address to read.
278 * @data: Read buffer for specified Serial ROM value.
283 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
290 * pch_phub_write_serial_rom() - Writing Serial ROM
292 * @offset_address: Serial ROM offset address.
293 * @data: Serial ROM value to write.
298 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
308 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
314 while (ioread8(chip->pch_phub_extrom_base_address +
318 return -ETIMEDOUT;
323 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
329 * pch_phub_read_serial_rom_val() - Read Serial ROM value
331 * @offset_address: Serial ROM address offset value.
332 * @data: Serial ROM value to read.
339 mem_addr = chip->pch_mac_start_address +
346 * pch_phub_write_serial_rom_val() - writing Serial ROM value
348 * @offset_address: Serial ROM address offset value.
349 * @data: Serial ROM value.
357 mem_addr = chip->pch_mac_start_address +
365 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
405 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
448 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
460 * pch_phub_write_gbe_mac_addr() - Write MAC address
469 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
502 err = -ERESTARTSYS;
506 /* Get Rom signature */
507 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
508 if (!chip->pch_phub_extrom_base_address) {
509 err = -ENODATA;
513 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
516 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
521 chip->pch_opt_rom_start_address + 2,
535 chip->pch_opt_rom_start_address + addr_offset + off,
539 err = -ENODATA;
543 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
548 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
567 return -ERESTARTSYS;
578 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
579 if (!chip->pch_phub_extrom_base_address) {
580 err = -ENOMEM;
589 chip->pch_opt_rom_start_address + addr_offset + off,
598 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
603 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
617 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
618 if (!chip->pch_phub_extrom_base_address)
619 return -ENOMEM;
622 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
636 return -EINVAL;
638 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
639 if (!chip->pch_phub_extrom_base_address)
640 return -ENOMEM;
643 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
670 return -ENOMEM;
674 dev_err(&pdev->dev,
678 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
683 dev_err(&pdev->dev,
687 dev_dbg(&pdev->dev, "%s : "
690 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
693 if (chip->pch_phub_base_address == NULL) {
694 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
695 ret = -ENOMEM;
698 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
700 chip->pch_phub_base_address);
702 chip->pdev = pdev; /* Save pci device struct */
704 if (id->driver_data == 1) { /* EG20T PCH */
708 if (pdev->dev.of_node)
709 of_property_read_u32(pdev->dev.of_node,
710 "intel,eg20t-prefetch",
713 ret = sysfs_create_file(&pdev->dev.kobj,
718 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
727 /* quirk for CM-iTC board */
729 if (board_name && strstr(board_name, "CM-iTC"))
737 iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
739 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
740 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
741 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
744 if (pdev->dev.of_node) {
752 } else if (id->driver_data == 2) { /* ML7213 IOH */
753 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
762 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
763 chip->pch_opt_rom_start_address =\
765 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
769 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
771 iowrite32(0x25, chip->pch_phub_base_address + 0x140);
772 chip->pch_opt_rom_start_address =\
774 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
775 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
776 ret = sysfs_create_file(&pdev->dev.kobj,
780 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
788 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
789 chip->pch_opt_rom_start_address =\
791 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
792 } else if (id->driver_data == 5) { /* ML7831 */
793 ret = sysfs_create_file(&pdev->dev.kobj,
798 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
803 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
805 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
806 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
807 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
810 chip->ioh_type = id->driver_data;
815 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
818 pci_iounmap(pdev, chip->pch_phub_base_address);
825 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
833 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
834 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
835 pci_iounmap(pdev, chip->pch_phub_base_address);