Lines Matching +full:ipc +full:- +full:3

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3  * Copyright (c) 2013-2014, Intel Corporation. All rights reserved.
28  * This register resides in PCI-E config space.
39 #define IPC_BASE_ADDR	0x80400 /* SeC IPC Base Address */
41 /* IPC Input Doorbell Register */
44 /* IPC Input Status Register
53 /* IPC Host Interrupt Status Register */
68 /* IPC Host Interrupt Mask Register */
74 /* IPC Input Payload RAM */
76 /* IPC Shared Payload RAM */
79 /* SeC Address Translation Table Entry 2 - Ctrl
81  * This register resides also in SeC's PCI-E Memory space.
92  /* SATT Table Entry 2 SAP Bridge Address - LSB Register */
95 /* Host High-level Interrupt Status Register */
97 /* Host High-level Interrupt Enable Register
102  * that arrive via IPC.
109 /* Host High-level Interrupt Mask Register.
118 /* Host High-level IRQ Status Register */
121 /* Host Interrupt Cause Register 0 - SeC IPC Readiness
125  * This register is used by SeC's IPC driver in order
126  * to synchronize with host about IPC interface state.
136 /* Host Interrupt Cause Register 1 - Aliveness Response */
144 /* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */
164 #define   HISR_INT_3_STS      BIT(3)
177 #define   HIER_INT_3_EN      BIT(3)
187 /* SEC Memory Space IPC output payload.
193 /* SeC Interrupt Cause Register - Host Aliveness Request
195  * in the host-visible PCI memory space.
202 /* SeC Interrupt Cause Register - Host IPC Readiness
205  * in the host-visible PCI memory space.
207  * to synchronize with SeC about IPC interface state.
219 /* SeC Interrupt Cause Register - SeC IPC Output Status
231 /*  MEI IPC Message payload size 64 bytes */