Lines Matching +full:native +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <asm/pnv-pci.h>
89 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
90 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
161 dev_info(&dev->dev, "dump_cxl_config_space\n");
164 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
166 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
168 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
170 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
172 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
174 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
176 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
178 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
180 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
187 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
200 show_reg("Mode Control", (val >> 16) & 0xff);
265 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
282 show_reg("Reserved", (val >> (63-7)) & 0xff);
291 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
298 show_reg("Reserved", (val >> (63-7)) & 0xff);
319 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
320 return -ENODEV;
328 * - For chips other than POWER8NVL, we only have CAPP 0,
330 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
347 * PEC1 (PHB1 - PHB2). No capi mode
348 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
369 return -ENODEV;
371 while (np && of_property_read_u32(np, "ibm,chip-id", &id))
374 return -ENODEV;
388 pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible slot\n",
390 return -ENODEV;
408 return -ENODEV;
411 if (of_property_read_u32_array(np, "ibm,phb-indications", val, 3)) {
432 * bit 61:60 MSI bits --> 0
433 * bit 59 TVT selector --> 0
436 return -ENODEV;
442 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
443 xsl_dsnctl |= (capp_unit_id << (63-15));
446 xsl_dsnctl |= ((u64)0x09 << (63-28));
450 * the Non-Blocking queues by the PHB. This field should match
455 xsl_dsnctl |= (nbwind << (63-55));
489 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
490 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
513 /* disable machines 31-47 and 20-27 for DMA */
524 * Check if PSL has data-cache. We need to flush adapter datacache
529 dev_dbg(&dev->dev, "No data-cache present\n");
530 adapter->native->no_data_cache = true;
549 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
551 psl_dsnctl |= (chipid << (63-5));
552 psl_dsnctl |= (capp_unit_id << (63-13));
559 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
560 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
570 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
571 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
595 adapter->psl_timebase_synced = false;
602 if (!of_property_present(np, "ibm,capp-timebase-sync")) {
604 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
613 if (adapter->native->sl_ops->write_timebase_ctrl)
614 adapter->native->sl_ops->write_timebase_ctrl(adapter);
644 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
651 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
657 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
658 return -ENODEV;
662 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
666 if (adapter->perst_loads_image)
671 if (adapter->perst_select_user)
677 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
686 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
693 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
701 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
709 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
719 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
720 return -ENODEV;
734 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
741 dev_info(&dev->dev, "switch card to CXL\n");
744 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
745 return -ENODEV;
749 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
755 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
759 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
760 * we must wait 100ms after this mode switch before touching
774 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
775 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
776 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
777 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
779 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
781 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
784 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
790 iounmap(afu->p2n_mmio);
792 iounmap(afu->native->p1n_mmio);
794 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
795 return -ENOMEM;
800 if (afu->p2n_mmio) {
801 iounmap(afu->p2n_mmio);
802 afu->p2n_mmio = NULL;
804 if (afu->native->p1n_mmio) {
805 iounmap(afu->native->p1n_mmio);
806 afu->native->p1n_mmio = NULL;
808 if (afu->native->afu_desc_mmio) {
809 iounmap(afu->native->afu_desc_mmio);
810 afu->native->afu_desc_mmio = NULL;
820 idr_destroy(&afu->contexts_idr);
823 kfree(afu->native);
833 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
834 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
835 afu->crs_num = AFUD_NUM_CRS(val);
838 afu->modes_supported |= CXL_MODE_DIRECTED;
840 afu->modes_supported |= CXL_MODE_DEDICATED;
842 afu->modes_supported |= CXL_MODE_TIME_SLICED;
845 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
846 afu->psa = AFUD_PPPSA_PSA(val);
847 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
848 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
851 afu->crs_len = AFUD_CR_LEN(val) * 256;
852 afu->crs_offset = AFUD_READ_CR_OFF(afu);
856 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
857 afu->eb_offset = AFUD_READ_EB_OFF(afu);
860 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
861 dev_warn(&afu->dev,
863 afu->eb_offset);
864 dev_info(&afu->dev,
867 afu->eb_len = 0;
878 if (afu->psa && afu->adapter->ps_size <
879 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
880 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
881 return -ENODEV;
884 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
885 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
887 for (i = 0; i < afu->crs_num; i++) {
888 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
890 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
891 return -EINVAL;
895 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
906 dev_err(&afu->dev, "AFU does not support any processes\n");
907 return -EINVAL;
924 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
925 if (cxl_ops->afu_reset(afu))
926 return -EIO;
928 return -EIO;
930 return -EIO;
936 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
942 if (afu->adapter->native->sl_ops->register_serr_irq) {
946 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
952 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
970 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
971 if (cxl_ops->afu_reset(afu))
972 return -EIO;
974 return -EIO;
976 return -EIO;
991 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
997 if (afu->adapter->native->sl_ops->register_serr_irq) {
1001 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1007 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1027 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1029 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1033 count = min((size_t)(afu->eb_len - off), count);
1036 aligned_length = aligned_end - aligned_start;
1041 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1047 return -ENOMEM;
1065 if (adapter->native->sl_ops->sanitise_afu_regs) {
1066 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1072 if ((rc = cxl_ops->afu_reset(afu)))
1084 if (adapter->native->sl_ops->afu_regs_init)
1085 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1088 if (adapter->native->sl_ops->register_serr_irq)
1089 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1095 atomic_set(&afu->configured_state, 0);
1099 if (adapter->native->sl_ops->release_serr_irq)
1100 adapter->native->sl_ops->release_serr_irq(afu);
1112 if (atomic_read(&afu->configured_state) != -1) {
1113 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1117 if (afu->adapter->native->sl_ops->release_serr_irq)
1118 afu->adapter->native->sl_ops->release_serr_irq(afu);
1125 int rc = -ENOMEM;
1129 return -ENOMEM;
1131 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1132 if (!afu->native)
1135 mutex_init(&afu->native->spa_mutex);
1137 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1158 adapter->afu[afu->slice] = afu;
1161 dev_info(&afu->dev, "Can't register vPHB\n");
1166 device_del(&afu->dev);
1170 put_device(&afu->dev);
1174 kfree(afu->native);
1192 spin_lock(&afu->adapter->afu_list_lock);
1193 afu->adapter->afu[afu->slice] = NULL;
1194 spin_unlock(&afu->adapter->afu_list_lock);
1197 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1200 device_unregister(&afu->dev);
1205 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1208 if (adapter->perst_same_image) {
1209 dev_warn(&dev->dev,
1211 return -EINVAL;
1214 dev_info(&dev->dev, "CXL reset\n");
1225 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1242 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1245 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1251 iounmap(adapter->native->p1_mmio);
1252 adapter->native->p1_mmio = NULL;
1258 return -ENOMEM;
1263 if (adapter->native->p1_mmio) {
1264 iounmap(adapter->native->p1_mmio);
1265 adapter->native->p1_mmio = NULL;
1266 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1268 if (adapter->native->p2_mmio) {
1269 iounmap(adapter->native->p2_mmio);
1270 adapter->native->p2_mmio = NULL;
1271 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1284 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1285 return -ENODEV;
1290 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1291 return -EINVAL;
1294 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1295 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1296 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1297 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1298 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1300 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1301 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1302 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1304 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1311 * code a month later and forget what units these are in ;-) */
1312 adapter->native->ps_off = ps_off * 64 * 1024;
1313 adapter->ps_size = ps_size * 64 * 1024;
1314 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1315 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1317 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1318 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1336 if (adapter->psl_rev & 0xf000)
1351 if (cxl_is_power8() && (adapter->caia_major == 1))
1354 if (cxl_is_power9() && (adapter->caia_major == 2))
1362 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1363 return -EBUSY;
1365 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1366 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1367 return -EINVAL;
1371 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1372 adapter->caia_major);
1373 return -ENODEV;
1376 if (!adapter->slices) {
1379 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1380 return -EINVAL;
1383 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1384 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1385 return -EINVAL;
1388 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1389 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1391 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1392 return -EINVAL;
1400 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1411 kfree(adapter->native);
1415 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1424 if (adapter->native->sl_ops->invalidate_all) {
1426 if (cxl_is_power9() && (adapter->perst_loads_image))
1428 rc = adapter->native->sl_ops->invalidate_all(adapter);
1441 adapter->dev.parent = &dev->dev;
1442 adapter->dev.release = cxl_release_adapter;
1447 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1474 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1477 /* Required for devices using CAPP DMA mode, harmless for others */
1480 adapter->tunneled_ops_supported = false;
1484 dev_info(&dev->dev, "Tunneled operations unsupported\n");
1486 adapter->tunneled_ops_supported = true;
1489 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1493 * In the non-recovery case this has no effect */
1513 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1528 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1533 trace_mask = (0x3ULL << (62 - traceid * 2));
1534 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1535 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1553 spin_lock(&adapter->afu_list_lock);
1554 for (slice = 0; slice < adapter->slices; slice++) {
1555 if (adapter->afu[slice])
1556 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1559 spin_unlock(&adapter->afu_list_lock);
1612 dev_info(&dev->dev, "Device uses a PSL8\n");
1613 adapter->native->sl_ops = &psl8_ops;
1615 dev_info(&dev->dev, "Device uses a PSL9\n");
1616 adapter->native->sl_ops = &psl9_ops;
1628 return ERR_PTR(-ENOMEM);
1630 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1631 if (!adapter->native) {
1632 rc = -ENOMEM;
1641 adapter->perst_loads_image = true;
1642 adapter->perst_same_image = false;
1669 device_del(&adapter->dev);
1676 put_device(&adapter->dev);
1680 cxl_release_adapter(&adapter->dev);
1698 device_unregister(&adapter->dev);
1710 return -ENODEV;
1729 dev_err_once(&dev->dev, "DEPRECATED: cxl is deprecated and will be removed in a future kernel release\n");
1732 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1733 return -ENODEV;
1737 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1738 return -ENODEV;
1742 dev_info(&dev->dev, "Only Radix mode supported\n");
1743 return -ENODEV;
1751 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1755 for (slice = 0; slice < adapter->slices; slice++) {
1757 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1761 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1763 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1779 for (i = 0; i < adapter->slices; i++) {
1780 afu = adapter->afu[i];
1798 if (afu == NULL || afu->phb == NULL)
1801 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1802 afu_drv = to_pci_driver(afu_dev->dev.driver);
1806 afu_dev->error_state = state;
1808 err_handler = afu_drv->err_handler;
1810 afu_result = err_handler->error_detected(afu_dev,
1839 spin_lock(&adapter->afu_list_lock);
1840 for (i = 0; i < adapter->slices; i++) {
1841 afu = adapter->afu[i];
1848 spin_unlock(&adapter->afu_list_lock);
1855 * different, including a non-CAPI card. As such, by default
1857 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1862 * order to get back to a more reliable known-good state.
1865 * trust that we'll come back the same - we could have a new
1868 * back the same - for example a regular EEH event.
1874 if (adapter->perst_loads_image && !adapter->perst_same_image) {
1875 /* TODO take the PHB out of CXL mode */
1876 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1885 * - We send the driver, if bound, an error_detected callback.
1890 * - We detach all contexts associated with the AFU. This
1896 * - We clean up our side: releasing and unmapping resources we hold
1901 * - Any contexts you create in your kernel driver (except
1906 * - We will take responsibility for re-initialising the
1932 spin_lock(&adapter->afu_list_lock);
1934 for (i = 0; i < adapter->slices; i++) {
1935 afu = adapter->afu[i];
1942 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1952 spin_unlock(&adapter->afu_list_lock);
1956 dev_warn(&adapter->dev,
1957 "Couldn't take context lock with %d active-contexts\n",
1958 atomic_read(&adapter->contexts_num));
1987 spin_lock(&adapter->afu_list_lock);
1988 for (i = 0; i < adapter->slices; i++) {
1989 afu = adapter->afu[i];
2000 if (afu->phb == NULL)
2003 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2016 afu_dev->dev.archdata.cxl_ctx = ctx;
2018 if (cxl_ops->afu_check_and_enable(afu))
2021 afu_dev->error_state = pci_channel_io_normal;
2029 afu_drv = to_pci_driver(afu_dev->dev.driver);
2033 err_handler = afu_drv->err_handler;
2034 if (err_handler && err_handler->slot_reset)
2035 afu_result = err_handler->slot_reset(afu_dev);
2042 spin_unlock(&adapter->afu_list_lock);
2046 spin_unlock(&adapter->afu_list_lock);
2053 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2070 spin_lock(&adapter->afu_list_lock);
2071 for (i = 0; i < adapter->slices; i++) {
2072 afu = adapter->afu[i];
2074 if (afu == NULL || afu->phb == NULL)
2077 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2078 afu_drv = to_pci_driver(afu_dev->dev.driver);
2082 err_handler = afu_drv->err_handler;
2083 if (err_handler && err_handler->resume)
2084 err_handler->resume(afu_dev);
2087 spin_unlock(&adapter->afu_list_lock);
2097 .name = "cxl-pci",