Lines Matching refs:WRITE_REG_CMD
577 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in rtsx_pci_write_ppbuf()
591 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in rtsx_pci_write_ppbuf()
610 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in rtsx_pci_set_pull_ctl()
769 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rtsx_pci_switch_clock()
771 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rtsx_pci_switch_clock()
773 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rtsx_pci_switch_clock()
774 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, in rtsx_pci_switch_clock()
776 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in rtsx_pci_switch_clock()
777 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in rtsx_pci_switch_clock()
779 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
781 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
1220 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); in rtsx_pci_init_hw()
1222 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_init_hw()
1224 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); in rtsx_pci_init_hw()
1226 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); in rtsx_pci_init_hw()
1228 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, in rtsx_pci_init_hw()
1231 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, in rtsx_pci_init_hw()
1234 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1237 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1240 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rtsx_pci_init_hw()
1242 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1245 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); in rtsx_pci_init_hw()
1248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); in rtsx_pci_init_hw()
1250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, in rtsx_pci_init_hw()
1255 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); in rtsx_pci_init_hw()
1260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); in rtsx_pci_init_hw()
1266 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); in rtsx_pci_init_hw()