Lines Matching full:pcr
64 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) in rtsx_comm_set_ltr_latency() argument
66 rtsx_pci_write_register(pcr, MSGTXDATA0, in rtsx_comm_set_ltr_latency()
68 rtsx_pci_write_register(pcr, MSGTXDATA1, in rtsx_comm_set_ltr_latency()
70 rtsx_pci_write_register(pcr, MSGTXDATA2, in rtsx_comm_set_ltr_latency()
72 rtsx_pci_write_register(pcr, MSGTXDATA3, in rtsx_comm_set_ltr_latency()
74 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK | in rtsx_comm_set_ltr_latency()
80 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) in rtsx_set_ltr_latency() argument
82 return rtsx_comm_set_ltr_latency(pcr, latency); in rtsx_set_ltr_latency()
85 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable) in rtsx_comm_set_aspm() argument
87 if (pcr->aspm_enabled == enable) in rtsx_comm_set_aspm()
90 if (pcr->aspm_mode == ASPM_MODE_CFG) { in rtsx_comm_set_aspm()
91 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rtsx_comm_set_aspm()
93 enable ? pcr->aspm_en : 0); in rtsx_comm_set_aspm()
94 } else if (pcr->aspm_mode == ASPM_MODE_REG) { in rtsx_comm_set_aspm()
95 if (pcr->aspm_en & 0x02) in rtsx_comm_set_aspm()
96 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | in rtsx_comm_set_aspm()
99 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | in rtsx_comm_set_aspm()
103 if (!enable && (pcr->aspm_en & 0x02)) in rtsx_comm_set_aspm()
106 pcr->aspm_enabled = enable; in rtsx_comm_set_aspm()
109 static void rtsx_disable_aspm(struct rtsx_pcr *pcr) in rtsx_disable_aspm() argument
111 if (pcr->ops->set_aspm) in rtsx_disable_aspm()
112 pcr->ops->set_aspm(pcr, false); in rtsx_disable_aspm()
114 rtsx_comm_set_aspm(pcr, false); in rtsx_disable_aspm()
117 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val) in rtsx_set_l1off_sub() argument
119 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val); in rtsx_set_l1off_sub()
124 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active) in rtsx_set_l1off_sub_cfg_d0() argument
126 if (pcr->ops->set_l1off_cfg_sub_d0) in rtsx_set_l1off_sub_cfg_d0()
127 pcr->ops->set_l1off_cfg_sub_d0(pcr, active); in rtsx_set_l1off_sub_cfg_d0()
130 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr) in rtsx_comm_pm_full_on() argument
132 struct rtsx_cr_option *option = &pcr->option; in rtsx_comm_pm_full_on()
134 rtsx_disable_aspm(pcr); in rtsx_comm_pm_full_on()
140 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rtsx_comm_pm_full_on()
142 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) in rtsx_comm_pm_full_on()
143 rtsx_set_l1off_sub_cfg_d0(pcr, 1); in rtsx_comm_pm_full_on()
146 static void rtsx_pm_full_on(struct rtsx_pcr *pcr) in rtsx_pm_full_on() argument
148 rtsx_comm_pm_full_on(pcr); in rtsx_pm_full_on()
151 void rtsx_pci_start_run(struct rtsx_pcr *pcr) in rtsx_pci_start_run() argument
154 if (pcr->remove_pci) in rtsx_pci_start_run()
157 if (pcr->state != PDEV_STAT_RUN) { in rtsx_pci_start_run()
158 pcr->state = PDEV_STAT_RUN; in rtsx_pci_start_run()
159 if (pcr->ops->enable_auto_blink) in rtsx_pci_start_run()
160 pcr->ops->enable_auto_blink(pcr); in rtsx_pci_start_run()
161 rtsx_pm_full_on(pcr); in rtsx_pci_start_run()
166 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) in rtsx_pci_write_register() argument
175 rtsx_pci_writel(pcr, RTSX_HAIMR, val); in rtsx_pci_write_register()
178 val = rtsx_pci_readl(pcr, RTSX_HAIMR); in rtsx_pci_write_register()
190 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data) in rtsx_pci_read_register() argument
196 rtsx_pci_writel(pcr, RTSX_HAIMR, val); in rtsx_pci_read_register()
199 val = rtsx_pci_readl(pcr, RTSX_HAIMR); in rtsx_pci_read_register()
214 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) in __rtsx_pci_write_phy_register() argument
219 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val); in __rtsx_pci_write_phy_register()
220 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8)); in __rtsx_pci_write_phy_register()
221 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); in __rtsx_pci_write_phy_register()
222 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81); in __rtsx_pci_write_phy_register()
225 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); in __rtsx_pci_write_phy_register()
241 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) in rtsx_pci_write_phy_register() argument
243 if (pcr->ops->write_phy) in rtsx_pci_write_phy_register()
244 return pcr->ops->write_phy(pcr, addr, val); in rtsx_pci_write_phy_register()
246 return __rtsx_pci_write_phy_register(pcr, addr, val); in rtsx_pci_write_phy_register()
250 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) in __rtsx_pci_read_phy_register() argument
256 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); in __rtsx_pci_read_phy_register()
257 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80); in __rtsx_pci_read_phy_register()
260 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); in __rtsx_pci_read_phy_register()
273 rtsx_pci_read_register(pcr, PHYDATA0, &val1); in __rtsx_pci_read_phy_register()
274 rtsx_pci_read_register(pcr, PHYDATA1, &val2); in __rtsx_pci_read_phy_register()
283 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) in rtsx_pci_read_phy_register() argument
285 if (pcr->ops->read_phy) in rtsx_pci_read_phy_register()
286 return pcr->ops->read_phy(pcr, addr, val); in rtsx_pci_read_phy_register()
288 return __rtsx_pci_read_phy_register(pcr, addr, val); in rtsx_pci_read_phy_register()
292 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr) in rtsx_pci_stop_cmd() argument
294 if (pcr->ops->stop_cmd) in rtsx_pci_stop_cmd()
295 return pcr->ops->stop_cmd(pcr); in rtsx_pci_stop_cmd()
297 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); in rtsx_pci_stop_cmd()
298 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); in rtsx_pci_stop_cmd()
300 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); in rtsx_pci_stop_cmd()
301 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); in rtsx_pci_stop_cmd()
305 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, in rtsx_pci_add_cmd() argument
310 u32 *ptr = (u32 *)(pcr->host_cmds_ptr); in rtsx_pci_add_cmd()
317 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_add_cmd()
318 ptr += pcr->ci; in rtsx_pci_add_cmd()
319 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) { in rtsx_pci_add_cmd()
322 pcr->ci++; in rtsx_pci_add_cmd()
324 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_add_cmd()
328 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr) in rtsx_pci_send_cmd_no_wait() argument
332 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); in rtsx_pci_send_cmd_no_wait()
334 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; in rtsx_pci_send_cmd_no_wait()
337 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); in rtsx_pci_send_cmd_no_wait()
341 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout) in rtsx_pci_send_cmd() argument
349 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_send_cmd()
352 pcr->done = &trans_done; in rtsx_pci_send_cmd()
353 pcr->trans_result = TRANS_NOT_READY; in rtsx_pci_send_cmd()
356 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); in rtsx_pci_send_cmd()
358 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; in rtsx_pci_send_cmd()
361 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); in rtsx_pci_send_cmd()
363 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_send_cmd()
369 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); in rtsx_pci_send_cmd()
374 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_send_cmd()
375 if (pcr->trans_result == TRANS_RESULT_FAIL) in rtsx_pci_send_cmd()
377 else if (pcr->trans_result == TRANS_RESULT_OK) in rtsx_pci_send_cmd()
379 else if (pcr->trans_result == TRANS_NO_DEVICE) in rtsx_pci_send_cmd()
381 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_send_cmd()
384 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_send_cmd()
385 pcr->done = NULL; in rtsx_pci_send_cmd()
386 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_send_cmd()
389 rtsx_pci_stop_cmd(pcr); in rtsx_pci_send_cmd()
391 if (pcr->finish_me) in rtsx_pci_send_cmd()
392 complete(pcr->finish_me); in rtsx_pci_send_cmd()
398 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, in rtsx_pci_add_sg_tbl() argument
401 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; in rtsx_pci_add_sg_tbl()
405 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); in rtsx_pci_add_sg_tbl()
410 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) { in rtsx_pci_add_sg_tbl()
420 pcr->sgi++; in rtsx_pci_add_sg_tbl()
423 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, in rtsx_pci_dma_map_sg() argument
428 if (pcr->remove_pci) in rtsx_pci_dma_map_sg()
434 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir); in rtsx_pci_dma_map_sg()
438 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, in rtsx_pci_dma_unmap_sg() argument
443 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir); in rtsx_pci_dma_unmap_sg()
447 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, in rtsx_pci_dma_transfer() argument
460 if (pcr->remove_pci) in rtsx_pci_dma_transfer()
467 pcr->sgi = 0; in rtsx_pci_dma_transfer()
471 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1); in rtsx_pci_dma_transfer()
474 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_dma_transfer()
476 pcr->done = &trans_done; in rtsx_pci_dma_transfer()
477 pcr->trans_result = TRANS_NOT_READY; in rtsx_pci_dma_transfer()
479 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr); in rtsx_pci_dma_transfer()
480 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); in rtsx_pci_dma_transfer()
482 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_dma_transfer()
487 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); in rtsx_pci_dma_transfer()
492 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_dma_transfer()
493 if (pcr->trans_result == TRANS_RESULT_FAIL) { in rtsx_pci_dma_transfer()
495 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION) in rtsx_pci_dma_transfer()
496 pcr->dma_error_count++; in rtsx_pci_dma_transfer()
499 else if (pcr->trans_result == TRANS_NO_DEVICE) in rtsx_pci_dma_transfer()
501 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_dma_transfer()
504 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_dma_transfer()
505 pcr->done = NULL; in rtsx_pci_dma_transfer()
506 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_dma_transfer()
509 rtsx_pci_stop_cmd(pcr); in rtsx_pci_dma_transfer()
511 if (pcr->finish_me) in rtsx_pci_dma_transfer()
512 complete(pcr->finish_me); in rtsx_pci_dma_transfer()
518 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) in rtsx_pci_read_ppbuf() argument
531 rtsx_pci_init_cmd(pcr); in rtsx_pci_read_ppbuf()
534 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); in rtsx_pci_read_ppbuf()
536 err = rtsx_pci_send_cmd(pcr, 250); in rtsx_pci_read_ppbuf()
540 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256); in rtsx_pci_read_ppbuf()
545 rtsx_pci_init_cmd(pcr); in rtsx_pci_read_ppbuf()
548 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); in rtsx_pci_read_ppbuf()
550 err = rtsx_pci_send_cmd(pcr, 250); in rtsx_pci_read_ppbuf()
555 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256); in rtsx_pci_read_ppbuf()
561 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) in rtsx_pci_write_ppbuf() argument
574 rtsx_pci_init_cmd(pcr); in rtsx_pci_write_ppbuf()
577 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in rtsx_pci_write_ppbuf()
582 err = rtsx_pci_send_cmd(pcr, 250); in rtsx_pci_write_ppbuf()
588 rtsx_pci_init_cmd(pcr); in rtsx_pci_write_ppbuf()
591 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in rtsx_pci_write_ppbuf()
596 err = rtsx_pci_send_cmd(pcr, 250); in rtsx_pci_write_ppbuf()
605 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl) in rtsx_pci_set_pull_ctl() argument
607 rtsx_pci_init_cmd(pcr); in rtsx_pci_set_pull_ctl()
610 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, in rtsx_pci_set_pull_ctl()
615 return rtsx_pci_send_cmd(pcr, 100); in rtsx_pci_set_pull_ctl()
618 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card) in rtsx_pci_card_pull_ctl_enable() argument
623 tbl = pcr->sd_pull_ctl_enable_tbl; in rtsx_pci_card_pull_ctl_enable()
625 tbl = pcr->ms_pull_ctl_enable_tbl; in rtsx_pci_card_pull_ctl_enable()
629 return rtsx_pci_set_pull_ctl(pcr, tbl); in rtsx_pci_card_pull_ctl_enable()
633 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card) in rtsx_pci_card_pull_ctl_disable() argument
638 tbl = pcr->sd_pull_ctl_disable_tbl; in rtsx_pci_card_pull_ctl_disable()
640 tbl = pcr->ms_pull_ctl_disable_tbl; in rtsx_pci_card_pull_ctl_disable()
644 return rtsx_pci_set_pull_ctl(pcr, tbl); in rtsx_pci_card_pull_ctl_disable()
648 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr) in rtsx_pci_enable_bus_int() argument
650 struct rtsx_hw_param *hw_param = &pcr->hw_param; in rtsx_pci_enable_bus_int()
652 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN in rtsx_pci_enable_bus_int()
655 if (pcr->num_slots > 1) in rtsx_pci_enable_bus_int()
656 pcr->bier |= MS_INT_EN; in rtsx_pci_enable_bus_int()
659 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier); in rtsx_pci_enable_bus_int()
661 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier); in rtsx_pci_enable_bus_int()
681 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, in rtsx_pci_switch_clock() argument
694 if (PCI_PID(pcr) == PID_5261) in rtsx_pci_switch_clock()
695 return rts5261_pci_switch_clock(pcr, card_clock, in rtsx_pci_switch_clock()
697 if (PCI_PID(pcr) == PID_5228) in rtsx_pci_switch_clock()
698 return rts5228_pci_switch_clock(pcr, card_clock, in rtsx_pci_switch_clock()
700 if (PCI_PID(pcr) == PID_5264) in rtsx_pci_switch_clock()
701 return rts5264_pci_switch_clock(pcr, card_clock, in rtsx_pci_switch_clock()
711 err = rtsx_pci_write_register(pcr, SD_CFG1, in rtsx_pci_switch_clock()
718 pcr->dma_error_count && in rtsx_pci_switch_clock()
719 PCI_PID(pcr) == RTS5227_DEVICE_ID) in rtsx_pci_switch_clock()
721 (pcr->dma_error_count * 20000000); in rtsx_pci_switch_clock()
724 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); in rtsx_pci_switch_clock()
729 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", in rtsx_pci_switch_clock()
730 clk, pcr->cur_clock); in rtsx_pci_switch_clock()
732 if (clk == pcr->cur_clock) in rtsx_pci_switch_clock()
735 if (pcr->ops->conv_clk_and_div_n) in rtsx_pci_switch_clock()
736 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); in rtsx_pci_switch_clock()
749 if (pcr->ops->conv_clk_and_div_n) { in rtsx_pci_switch_clock()
750 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, in rtsx_pci_switch_clock()
752 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, in rtsx_pci_switch_clock()
759 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); in rtsx_pci_switch_clock()
766 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); in rtsx_pci_switch_clock()
768 rtsx_pci_init_cmd(pcr); in rtsx_pci_switch_clock()
769 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rtsx_pci_switch_clock()
771 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rtsx_pci_switch_clock()
773 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rtsx_pci_switch_clock()
774 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, in rtsx_pci_switch_clock()
776 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in rtsx_pci_switch_clock()
777 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in rtsx_pci_switch_clock()
779 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
781 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
785 err = rtsx_pci_send_cmd(pcr, 2000); in rtsx_pci_switch_clock()
791 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rtsx_pci_switch_clock()
795 pcr->cur_clock = clk; in rtsx_pci_switch_clock()
800 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card) in rtsx_pci_card_power_on() argument
802 if (pcr->ops->card_power_on) in rtsx_pci_card_power_on()
803 return pcr->ops->card_power_on(pcr, card); in rtsx_pci_card_power_on()
809 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card) in rtsx_pci_card_power_off() argument
811 if (pcr->ops->card_power_off) in rtsx_pci_card_power_off()
812 return pcr->ops->card_power_off(pcr, card); in rtsx_pci_card_power_off()
818 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card) in rtsx_pci_card_exclusive_check() argument
825 if (!(pcr->flags & PCR_MS_PMOS)) { in rtsx_pci_card_exclusive_check()
829 if (pcr->card_exist & (~cd_mask[card])) in rtsx_pci_card_exclusive_check()
837 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rtsx_pci_switch_output_voltage() argument
839 if (pcr->ops->switch_output_voltage) in rtsx_pci_switch_output_voltage()
840 return pcr->ops->switch_output_voltage(pcr, voltage); in rtsx_pci_switch_output_voltage()
846 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr) in rtsx_pci_card_exist() argument
850 val = rtsx_pci_readl(pcr, RTSX_BIPR); in rtsx_pci_card_exist()
851 if (pcr->ops->cd_deglitch) in rtsx_pci_card_exist()
852 val = pcr->ops->cd_deglitch(pcr); in rtsx_pci_card_exist()
858 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr) in rtsx_pci_complete_unfinished_transfer() argument
862 pcr->finish_me = &finish; in rtsx_pci_complete_unfinished_transfer()
865 if (pcr->done) in rtsx_pci_complete_unfinished_transfer()
866 complete(pcr->done); in rtsx_pci_complete_unfinished_transfer()
868 if (!pcr->remove_pci) in rtsx_pci_complete_unfinished_transfer()
869 rtsx_pci_stop_cmd(pcr); in rtsx_pci_complete_unfinished_transfer()
873 pcr->finish_me = NULL; in rtsx_pci_complete_unfinished_transfer()
880 struct rtsx_pcr *pcr; in rtsx_pci_card_detect() local
886 pcr = container_of(dwork, struct rtsx_pcr, carddet_work); in rtsx_pci_card_detect()
888 pcr_dbg(pcr, "--> %s\n", __func__); in rtsx_pci_card_detect()
890 mutex_lock(&pcr->pcr_mutex); in rtsx_pci_card_detect()
891 spin_lock_irqsave(&pcr->lock, flags); in rtsx_pci_card_detect()
893 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR); in rtsx_pci_card_detect()
894 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status); in rtsx_pci_card_detect()
897 card_inserted = pcr->card_inserted & irq_status; in rtsx_pci_card_detect()
898 card_removed = pcr->card_removed; in rtsx_pci_card_detect()
899 pcr->card_inserted = 0; in rtsx_pci_card_detect()
900 pcr->card_removed = 0; in rtsx_pci_card_detect()
902 spin_unlock_irqrestore(&pcr->lock, flags); in rtsx_pci_card_detect()
905 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n", in rtsx_pci_card_detect()
908 if (pcr->ops->cd_deglitch) in rtsx_pci_card_detect()
909 card_inserted = pcr->ops->cd_deglitch(pcr); in rtsx_pci_card_detect()
913 pcr->card_exist |= card_inserted; in rtsx_pci_card_detect()
914 pcr->card_exist &= ~card_removed; in rtsx_pci_card_detect()
917 mutex_unlock(&pcr->pcr_mutex); in rtsx_pci_card_detect()
919 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event) in rtsx_pci_card_detect()
920 pcr->slots[RTSX_SD_CARD].card_event( in rtsx_pci_card_detect()
921 pcr->slots[RTSX_SD_CARD].p_dev); in rtsx_pci_card_detect()
922 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event) in rtsx_pci_card_detect()
923 pcr->slots[RTSX_MS_CARD].card_event( in rtsx_pci_card_detect()
924 pcr->slots[RTSX_MS_CARD].p_dev); in rtsx_pci_card_detect()
927 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr) in rtsx_pci_process_ocp() argument
929 if (pcr->ops->process_ocp) { in rtsx_pci_process_ocp()
930 pcr->ops->process_ocp(pcr); in rtsx_pci_process_ocp()
932 if (!pcr->option.ocp_en) in rtsx_pci_process_ocp()
934 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); in rtsx_pci_process_ocp()
935 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { in rtsx_pci_process_ocp()
936 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); in rtsx_pci_process_ocp()
937 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rtsx_pci_process_ocp()
938 rtsx_pci_clear_ocpstat(pcr); in rtsx_pci_process_ocp()
939 pcr->ocp_stat = 0; in rtsx_pci_process_ocp()
944 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr) in rtsx_pci_process_ocp_interrupt() argument
946 if (pcr->option.ocp_en) in rtsx_pci_process_ocp_interrupt()
947 rtsx_pci_process_ocp(pcr); in rtsx_pci_process_ocp_interrupt()
954 struct rtsx_pcr *pcr = dev_id; in rtsx_pci_isr() local
957 if (!pcr) in rtsx_pci_isr()
960 spin_lock(&pcr->lock); in rtsx_pci_isr()
962 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR); in rtsx_pci_isr()
964 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg); in rtsx_pci_isr()
965 if ((int_reg & pcr->bier) == 0) { in rtsx_pci_isr()
966 spin_unlock(&pcr->lock); in rtsx_pci_isr()
970 spin_unlock(&pcr->lock); in rtsx_pci_isr()
974 int_reg &= (pcr->bier | 0x7FFFFF); in rtsx_pci_isr()
977 ((int_reg & SD_OVP_INT) && (PCI_PID(pcr) == PID_5264))) in rtsx_pci_isr()
978 rtsx_pci_process_ocp_interrupt(pcr); in rtsx_pci_isr()
982 pcr->card_inserted |= SD_EXIST; in rtsx_pci_isr()
984 pcr->card_removed |= SD_EXIST; in rtsx_pci_isr()
985 pcr->card_inserted &= ~SD_EXIST; in rtsx_pci_isr()
988 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) { in rtsx_pci_isr()
989 rtsx_pci_write_register(pcr, RTS5261_FW_STATUS, in rtsx_pci_isr()
991 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS; in rtsx_pci_isr()
994 pcr->dma_error_count = 0; in rtsx_pci_isr()
999 pcr->card_inserted |= MS_EXIST; in rtsx_pci_isr()
1001 pcr->card_removed |= MS_EXIST; in rtsx_pci_isr()
1002 pcr->card_inserted &= ~MS_EXIST; in rtsx_pci_isr()
1008 pcr->trans_result = TRANS_RESULT_FAIL; in rtsx_pci_isr()
1009 if (pcr->done) in rtsx_pci_isr()
1010 complete(pcr->done); in rtsx_pci_isr()
1012 pcr->trans_result = TRANS_RESULT_OK; in rtsx_pci_isr()
1013 if (pcr->done) in rtsx_pci_isr()
1014 complete(pcr->done); in rtsx_pci_isr()
1018 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT)) in rtsx_pci_isr()
1019 schedule_delayed_work(&pcr->carddet_work, in rtsx_pci_isr()
1022 spin_unlock(&pcr->lock); in rtsx_pci_isr()
1026 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr) in rtsx_pci_acquire_irq() argument
1028 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n", in rtsx_pci_acquire_irq()
1029 __func__, pcr->msi_en, pcr->pci->irq); in rtsx_pci_acquire_irq()
1031 if (request_irq(pcr->pci->irq, rtsx_pci_isr, in rtsx_pci_acquire_irq()
1032 pcr->msi_en ? 0 : IRQF_SHARED, in rtsx_pci_acquire_irq()
1033 DRV_NAME_RTSX_PCI, pcr)) { in rtsx_pci_acquire_irq()
1034 dev_err(&(pcr->pci->dev), in rtsx_pci_acquire_irq()
1036 pcr->pci->irq); in rtsx_pci_acquire_irq()
1040 pcr->irq = pcr->pci->irq; in rtsx_pci_acquire_irq()
1041 pci_intx(pcr->pci, !pcr->msi_en); in rtsx_pci_acquire_irq()
1046 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr) in rtsx_base_force_power_down() argument
1049 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rtsx_base_force_power_down()
1050 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rtsx_base_force_power_down()
1051 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, in rtsx_base_force_power_down()
1054 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rtsx_base_force_power_down()
1057 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN); in rtsx_base_force_power_down()
1060 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) in rtsx_pci_power_off() argument
1062 if (pcr->ops->turn_off_led) in rtsx_pci_power_off()
1063 pcr->ops->turn_off_led(pcr); in rtsx_pci_power_off()
1065 rtsx_pci_writel(pcr, RTSX_BIER, 0); in rtsx_pci_power_off()
1066 pcr->bier = 0; in rtsx_pci_power_off()
1068 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); in rtsx_pci_power_off()
1069 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); in rtsx_pci_power_off()
1071 if (pcr->ops->force_power_down) in rtsx_pci_power_off()
1072 pcr->ops->force_power_down(pcr, pm_state, runtime); in rtsx_pci_power_off()
1074 rtsx_base_force_power_down(pcr); in rtsx_pci_power_off()
1077 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr) in rtsx_pci_enable_ocp() argument
1081 if (pcr->ops->enable_ocp) { in rtsx_pci_enable_ocp()
1082 pcr->ops->enable_ocp(pcr); in rtsx_pci_enable_ocp()
1084 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); in rtsx_pci_enable_ocp()
1085 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); in rtsx_pci_enable_ocp()
1090 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr) in rtsx_pci_disable_ocp() argument
1094 if (pcr->ops->disable_ocp) { in rtsx_pci_disable_ocp()
1095 pcr->ops->disable_ocp(pcr); in rtsx_pci_disable_ocp()
1097 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rtsx_pci_disable_ocp()
1098 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, in rtsx_pci_disable_ocp()
1103 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr) in rtsx_pci_init_ocp() argument
1105 if (pcr->ops->init_ocp) { in rtsx_pci_init_ocp()
1106 pcr->ops->init_ocp(pcr); in rtsx_pci_init_ocp()
1108 struct rtsx_cr_option *option = &(pcr->option); in rtsx_pci_init_ocp()
1113 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); in rtsx_pci_init_ocp()
1114 rtsx_pci_write_register(pcr, REG_OCPPARA1, in rtsx_pci_init_ocp()
1116 rtsx_pci_write_register(pcr, REG_OCPPARA2, in rtsx_pci_init_ocp()
1118 rtsx_pci_write_register(pcr, REG_OCPGLITCH, in rtsx_pci_init_ocp()
1119 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch); in rtsx_pci_init_ocp()
1120 rtsx_pci_enable_ocp(pcr); in rtsx_pci_init_ocp()
1125 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val) in rtsx_pci_get_ocpstat() argument
1127 if (pcr->ops->get_ocpstat) in rtsx_pci_get_ocpstat()
1128 return pcr->ops->get_ocpstat(pcr, val); in rtsx_pci_get_ocpstat()
1130 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val); in rtsx_pci_get_ocpstat()
1133 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr) in rtsx_pci_clear_ocpstat() argument
1135 if (pcr->ops->clear_ocpstat) { in rtsx_pci_clear_ocpstat()
1136 pcr->ops->clear_ocpstat(pcr); in rtsx_pci_clear_ocpstat()
1141 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); in rtsx_pci_clear_ocpstat()
1143 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rtsx_pci_clear_ocpstat()
1147 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr) in rtsx_pci_enable_oobs_polling() argument
1151 if ((PCI_PID(pcr) != PID_525A) && in rtsx_pci_enable_oobs_polling()
1152 (PCI_PID(pcr) != PID_5260) && in rtsx_pci_enable_oobs_polling()
1153 (PCI_PID(pcr) != PID_5264)) { in rtsx_pci_enable_oobs_polling()
1154 rtsx_pci_read_phy_register(pcr, 0x01, &val); in rtsx_pci_enable_oobs_polling()
1156 rtsx_pci_write_phy_register(pcr, 0x01, val); in rtsx_pci_enable_oobs_polling()
1158 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32); in rtsx_pci_enable_oobs_polling()
1159 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05); in rtsx_pci_enable_oobs_polling()
1160 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83); in rtsx_pci_enable_oobs_polling()
1161 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE); in rtsx_pci_enable_oobs_polling()
1165 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr) in rtsx_pci_disable_oobs_polling() argument
1169 if ((PCI_PID(pcr) != PID_525A) && in rtsx_pci_disable_oobs_polling()
1170 (PCI_PID(pcr) != PID_5260) && in rtsx_pci_disable_oobs_polling()
1171 (PCI_PID(pcr) != PID_5264)) { in rtsx_pci_disable_oobs_polling()
1172 rtsx_pci_read_phy_register(pcr, 0x01, &val); in rtsx_pci_disable_oobs_polling()
1174 rtsx_pci_write_phy_register(pcr, 0x01, val); in rtsx_pci_disable_oobs_polling()
1176 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03); in rtsx_pci_disable_oobs_polling()
1177 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00); in rtsx_pci_disable_oobs_polling()
1181 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) in rtsx_pci_init_hw() argument
1183 struct pci_dev *pdev = pcr->pci; in rtsx_pci_init_hw()
1186 if (PCI_PID(pcr) == PID_5228) in rtsx_pci_init_hw()
1187 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK, in rtsx_pci_init_hw()
1190 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); in rtsx_pci_init_hw()
1192 rtsx_pci_enable_bus_int(pcr); in rtsx_pci_init_hw()
1195 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) { in rtsx_pci_init_hw()
1197 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, in rtsx_pci_init_hw()
1199 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL, in rtsx_pci_init_hw()
1202 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); in rtsx_pci_init_hw()
1210 rtsx_disable_aspm(pcr); in rtsx_pci_init_hw()
1211 if (pcr->ops->optimize_phy) { in rtsx_pci_init_hw()
1212 err = pcr->ops->optimize_phy(pcr); in rtsx_pci_init_hw()
1217 rtsx_pci_init_cmd(pcr); in rtsx_pci_init_hw()
1220 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); in rtsx_pci_init_hw()
1222 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_init_hw()
1224 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); in rtsx_pci_init_hw()
1226 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); in rtsx_pci_init_hw()
1228 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, in rtsx_pci_init_hw()
1229 0xFF, pcr->card_drive_sel); in rtsx_pci_init_hw()
1231 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, in rtsx_pci_init_hw()
1233 if (PCI_PID(pcr) == PID_5261) in rtsx_pci_init_hw()
1234 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1236 else if (PCI_PID(pcr) == PID_5228) in rtsx_pci_init_hw()
1237 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1239 else if (is_version(pcr, PID_5264, RTS5264_IC_VER_A)) in rtsx_pci_init_hw()
1240 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rtsx_pci_init_hw()
1241 else if (PCI_PID(pcr) == PID_5264) in rtsx_pci_init_hw()
1242 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1245 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); in rtsx_pci_init_hw()
1248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); in rtsx_pci_init_hw()
1250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, in rtsx_pci_init_hw()
1255 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); in rtsx_pci_init_hw()
1260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); in rtsx_pci_init_hw()
1266 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); in rtsx_pci_init_hw()
1268 err = rtsx_pci_send_cmd(pcr, 100); in rtsx_pci_init_hw()
1272 switch (PCI_PID(pcr)) { in rtsx_pci_init_hw()
1280 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1); in rtsx_pci_init_hw()
1287 rtsx_pci_init_ocp(pcr); in rtsx_pci_init_hw()
1290 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rtsx_pci_init_hw()
1295 if (pcr->ops->extra_init_hw) { in rtsx_pci_init_hw()
1296 err = pcr->ops->extra_init_hw(pcr); in rtsx_pci_init_hw()
1301 if (pcr->aspm_mode == ASPM_MODE_REG) in rtsx_pci_init_hw()
1302 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); in rtsx_pci_init_hw()
1305 * So we need to initialize pcr->card_exist here. in rtsx_pci_init_hw()
1307 if (pcr->ops->cd_deglitch) in rtsx_pci_init_hw()
1308 pcr->card_exist = pcr->ops->cd_deglitch(pcr); in rtsx_pci_init_hw()
1310 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST; in rtsx_pci_init_hw()
1315 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) in rtsx_pci_init_chip() argument
1317 struct rtsx_cr_option *option = &(pcr->option); in rtsx_pci_init_chip()
1323 spin_lock_init(&pcr->lock); in rtsx_pci_init_chip()
1324 mutex_init(&pcr->pcr_mutex); in rtsx_pci_init_chip()
1326 switch (PCI_PID(pcr)) { in rtsx_pci_init_chip()
1329 rts5209_init_params(pcr); in rtsx_pci_init_chip()
1333 rts5229_init_params(pcr); in rtsx_pci_init_chip()
1337 rtl8411_init_params(pcr); in rtsx_pci_init_chip()
1341 rts5227_init_params(pcr); in rtsx_pci_init_chip()
1345 rts522a_init_params(pcr); in rtsx_pci_init_chip()
1349 rts5249_init_params(pcr); in rtsx_pci_init_chip()
1353 rts524a_init_params(pcr); in rtsx_pci_init_chip()
1357 rts525a_init_params(pcr); in rtsx_pci_init_chip()
1361 rtl8411b_init_params(pcr); in rtsx_pci_init_chip()
1365 rtl8402_init_params(pcr); in rtsx_pci_init_chip()
1369 rts5260_init_params(pcr); in rtsx_pci_init_chip()
1373 rts5261_init_params(pcr); in rtsx_pci_init_chip()
1377 rts5228_init_params(pcr); in rtsx_pci_init_chip()
1381 rts5264_init_params(pcr); in rtsx_pci_init_chip()
1385 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n", in rtsx_pci_init_chip()
1386 PCI_PID(pcr), pcr->ic_version); in rtsx_pci_init_chip()
1388 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot), in rtsx_pci_init_chip()
1390 if (!pcr->slots) in rtsx_pci_init_chip()
1393 if (pcr->aspm_mode == ASPM_MODE_CFG) { in rtsx_pci_init_chip()
1394 pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val); in rtsx_pci_init_chip()
1396 pcr->aspm_enabled = true; in rtsx_pci_init_chip()
1398 pcr->aspm_enabled = false; in rtsx_pci_init_chip()
1400 } else if (pcr->aspm_mode == ASPM_MODE_REG) { in rtsx_pci_init_chip()
1401 rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val); in rtsx_pci_init_chip()
1403 pcr->aspm_enabled = false; in rtsx_pci_init_chip()
1405 pcr->aspm_enabled = true; in rtsx_pci_init_chip()
1408 l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS); in rtsx_pci_init_chip()
1410 pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); in rtsx_pci_init_chip()
1413 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); in rtsx_pci_init_chip()
1415 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); in rtsx_pci_init_chip()
1418 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); in rtsx_pci_init_chip()
1420 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); in rtsx_pci_init_chip()
1423 rtsx_set_dev_flag(pcr, PM_L1_1_EN); in rtsx_pci_init_chip()
1425 rtsx_clear_dev_flag(pcr, PM_L1_1_EN); in rtsx_pci_init_chip()
1428 rtsx_set_dev_flag(pcr, PM_L1_2_EN); in rtsx_pci_init_chip()
1430 rtsx_clear_dev_flag(pcr, PM_L1_2_EN); in rtsx_pci_init_chip()
1432 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val); in rtsx_pci_init_chip()
1440 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rtsx_pci_init_chip()
1450 if (pcr->ops->fetch_vendor_settings) in rtsx_pci_init_chip()
1451 pcr->ops->fetch_vendor_settings(pcr); in rtsx_pci_init_chip()
1453 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en); in rtsx_pci_init_chip()
1454 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n", in rtsx_pci_init_chip()
1455 pcr->sd30_drive_sel_1v8); in rtsx_pci_init_chip()
1456 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n", in rtsx_pci_init_chip()
1457 pcr->sd30_drive_sel_3v3); in rtsx_pci_init_chip()
1458 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n", in rtsx_pci_init_chip()
1459 pcr->card_drive_sel); in rtsx_pci_init_chip()
1460 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags); in rtsx_pci_init_chip()
1462 pcr->state = PDEV_STAT_IDLE; in rtsx_pci_init_chip()
1463 err = rtsx_pci_init_hw(pcr); in rtsx_pci_init_chip()
1465 kfree(pcr->slots); in rtsx_pci_init_chip()
1475 struct rtsx_pcr *pcr; in rtsx_pci_probe() local
1497 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); in rtsx_pci_probe()
1498 if (!pcr) { in rtsx_pci_probe()
1508 handle->pcr = pcr; in rtsx_pci_probe()
1512 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); in rtsx_pci_probe()
1514 pcr->id = ret; in rtsx_pci_probe()
1520 pcr->pci = pcidev; in rtsx_pci_probe()
1523 if ((CHK_PCI_PID(pcr, 0x525A)) || (CHK_PCI_PID(pcr, 0x5264))) in rtsx_pci_probe()
1527 pcr->remap_addr = ioremap(base, len); in rtsx_pci_probe()
1528 if (!pcr->remap_addr) { in rtsx_pci_probe()
1533 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), in rtsx_pci_probe()
1534 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr), in rtsx_pci_probe()
1536 if (pcr->rtsx_resv_buf == NULL) { in rtsx_pci_probe()
1540 pcr->host_cmds_ptr = pcr->rtsx_resv_buf; in rtsx_pci_probe()
1541 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; in rtsx_pci_probe()
1542 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; in rtsx_pci_probe()
1543 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; in rtsx_pci_probe()
1544 pcr->card_inserted = 0; in rtsx_pci_probe()
1545 pcr->card_removed = 0; in rtsx_pci_probe()
1546 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); in rtsx_pci_probe()
1548 pcr->msi_en = msi_en; in rtsx_pci_probe()
1549 if (pcr->msi_en) { in rtsx_pci_probe()
1552 pcr->msi_en = false; in rtsx_pci_probe()
1555 ret = rtsx_pci_acquire_irq(pcr); in rtsx_pci_probe()
1560 synchronize_irq(pcr->irq); in rtsx_pci_probe()
1562 ret = rtsx_pci_init_chip(pcr); in rtsx_pci_probe()
1572 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells, in rtsx_pci_probe()
1583 kfree(pcr->slots); in rtsx_pci_probe()
1585 free_irq(pcr->irq, (void *)pcr); in rtsx_pci_probe()
1587 if (pcr->msi_en) in rtsx_pci_probe()
1588 pci_disable_msi(pcr->pci); in rtsx_pci_probe()
1589 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, in rtsx_pci_probe()
1590 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); in rtsx_pci_probe()
1592 iounmap(pcr->remap_addr); in rtsx_pci_probe()
1595 idr_remove(&rtsx_pci_idr, pcr->id); in rtsx_pci_probe()
1600 kfree(pcr); in rtsx_pci_probe()
1612 struct rtsx_pcr *pcr = handle->pcr; in rtsx_pci_remove() local
1614 pcr->remove_pci = true; in rtsx_pci_remove()
1619 /* Disable interrupts at the pcr level */ in rtsx_pci_remove()
1620 spin_lock_irq(&pcr->lock); in rtsx_pci_remove()
1621 rtsx_pci_writel(pcr, RTSX_BIER, 0); in rtsx_pci_remove()
1622 pcr->bier = 0; in rtsx_pci_remove()
1623 spin_unlock_irq(&pcr->lock); in rtsx_pci_remove()
1625 cancel_delayed_work_sync(&pcr->carddet_work); in rtsx_pci_remove()
1629 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, in rtsx_pci_remove()
1630 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); in rtsx_pci_remove()
1631 free_irq(pcr->irq, (void *)pcr); in rtsx_pci_remove()
1632 if (pcr->msi_en) in rtsx_pci_remove()
1633 pci_disable_msi(pcr->pci); in rtsx_pci_remove()
1634 iounmap(pcr->remap_addr); in rtsx_pci_remove()
1640 idr_remove(&rtsx_pci_idr, pcr->id); in rtsx_pci_remove()
1643 kfree(pcr->slots); in rtsx_pci_remove()
1644 kfree(pcr); in rtsx_pci_remove()
1656 struct rtsx_pcr *pcr = handle->pcr; in rtsx_pci_suspend() local
1660 cancel_delayed_work_sync(&pcr->carddet_work); in rtsx_pci_suspend()
1662 mutex_lock(&pcr->pcr_mutex); in rtsx_pci_suspend()
1664 rtsx_pci_power_off(pcr, HOST_ENTER_S3, false); in rtsx_pci_suspend()
1666 mutex_unlock(&pcr->pcr_mutex); in rtsx_pci_suspend()
1674 struct rtsx_pcr *pcr = handle->pcr; in rtsx_pci_resume() local
1679 mutex_lock(&pcr->pcr_mutex); in rtsx_pci_resume()
1681 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_resume()
1685 ret = rtsx_pci_init_hw(pcr); in rtsx_pci_resume()
1690 mutex_unlock(&pcr->pcr_mutex); in rtsx_pci_resume()
1696 static void rtsx_enable_aspm(struct rtsx_pcr *pcr) in rtsx_enable_aspm() argument
1698 if (pcr->ops->set_aspm) in rtsx_enable_aspm()
1699 pcr->ops->set_aspm(pcr, true); in rtsx_enable_aspm()
1701 rtsx_comm_set_aspm(pcr, true); in rtsx_enable_aspm()
1704 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr) in rtsx_comm_pm_power_saving() argument
1706 struct rtsx_cr_option *option = &pcr->option; in rtsx_comm_pm_power_saving()
1711 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN)) in rtsx_comm_pm_power_saving()
1714 rtsx_set_ltr_latency(pcr, latency); in rtsx_comm_pm_power_saving()
1717 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN)) in rtsx_comm_pm_power_saving()
1718 rtsx_set_l1off_sub_cfg_d0(pcr, 0); in rtsx_comm_pm_power_saving()
1720 rtsx_enable_aspm(pcr); in rtsx_comm_pm_power_saving()
1723 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr) in rtsx_pm_power_saving() argument
1725 rtsx_comm_pm_power_saving(pcr); in rtsx_pm_power_saving()
1731 struct rtsx_pcr *pcr = handle->pcr; in rtsx_pci_shutdown() local
1735 rtsx_pci_power_off(pcr, HOST_ENTER_S1, false); in rtsx_pci_shutdown()
1738 free_irq(pcr->irq, (void *)pcr); in rtsx_pci_shutdown()
1739 if (pcr->msi_en) in rtsx_pci_shutdown()
1740 pci_disable_msi(pcr->pci); in rtsx_pci_shutdown()
1747 struct rtsx_pcr *pcr = handle->pcr; in rtsx_pci_runtime_idle() local
1751 mutex_lock(&pcr->pcr_mutex); in rtsx_pci_runtime_idle()
1753 pcr->state = PDEV_STAT_IDLE; in rtsx_pci_runtime_idle()
1755 if (pcr->ops->disable_auto_blink) in rtsx_pci_runtime_idle()
1756 pcr->ops->disable_auto_blink(pcr); in rtsx_pci_runtime_idle()
1757 if (pcr->ops->turn_off_led) in rtsx_pci_runtime_idle()
1758 pcr->ops->turn_off_led(pcr); in rtsx_pci_runtime_idle()
1760 rtsx_pm_power_saving(pcr); in rtsx_pci_runtime_idle()
1762 mutex_unlock(&pcr->pcr_mutex); in rtsx_pci_runtime_idle()
1764 if (pcr->rtd3_en) in rtsx_pci_runtime_idle()
1774 struct rtsx_pcr *pcr = handle->pcr; in rtsx_pci_runtime_suspend() local
1778 cancel_delayed_work_sync(&pcr->carddet_work); in rtsx_pci_runtime_suspend()
1780 mutex_lock(&pcr->pcr_mutex); in rtsx_pci_runtime_suspend()
1781 rtsx_pci_power_off(pcr, HOST_ENTER_S3, true); in rtsx_pci_runtime_suspend()
1783 mutex_unlock(&pcr->pcr_mutex); in rtsx_pci_runtime_suspend()
1792 struct rtsx_pcr *pcr = handle->pcr; in rtsx_pci_runtime_resume() local
1796 mutex_lock(&pcr->pcr_mutex); in rtsx_pci_runtime_resume()
1798 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_runtime_resume()
1800 rtsx_pci_init_hw(pcr); in rtsx_pci_runtime_resume()
1802 if (pcr->slots[RTSX_SD_CARD].p_dev != NULL) { in rtsx_pci_runtime_resume()
1803 pcr->slots[RTSX_SD_CARD].card_event( in rtsx_pci_runtime_resume()
1804 pcr->slots[RTSX_SD_CARD].p_dev); in rtsx_pci_runtime_resume()
1807 mutex_unlock(&pcr->pcr_mutex); in rtsx_pci_runtime_resume()