30 		{0x11, 0x11, 0x11},  in rts5260_fill_driving()
31 		{0x22, 0x22, 0x22},  in rts5260_fill_driving()
32 		{0x55, 0x55, 0x55},  in rts5260_fill_driving()
33 		{0x33, 0x33, 0x33},  in rts5260_fill_driving()
36 		{0x35, 0x33, 0x33},  in rts5260_fill_driving()
37 		{0x8A, 0x88, 0x88},  in rts5260_fill_driving()
38 		{0xBD, 0xBB, 0xBB},  in rts5260_fill_driving()
39 		{0x9B, 0x99, 0x99},  in rts5260_fill_driving()
52 			 0xFF, driving[drive_sel][0]);  in rts5260_fill_driving()
55 			 0xFF, driving[drive_sel][1]);  in rts5260_fill_driving()
58 			 0xFF, driving[drive_sel][2]);  in rts5260_fill_driving()
67 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);  in rtsx_base_fetch_vendor_settings()
76 	pcr->card_drive_sel &= 0x3F;  in rtsx_base_fetch_vendor_settings()
80 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);  in rtsx_base_fetch_vendor_settings()
113  *     SD_DAT[3:0] ==> pull up
120 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
121 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
122 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
123 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
124 	0,
128  *     SD_DAT[3:0] ==> pull down
135 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
136 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
137 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
138 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
139 	0,
147 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
148 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
149 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
150 	0,
158 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
159 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
160 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
161 	0,
169 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,  in sd_set_sample_push_timing_sd30()
171 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);  in sd_set_sample_push_timing_sd30()
173 	return 0;  in sd_set_sample_push_timing_sd30()
200 	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,  in rts5260_card_power_on()
204 				0xFF, SD20_RX_POS_EDGE);  in rts5260_card_power_on()
205 	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);  in rts5260_card_power_on()
210 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);  in rts5260_card_power_on()
213 			SD30_CLK_STOP_CFG0, 0);  in rts5260_card_power_on()
215 	rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);  in rts5260_card_power_on()
217 	return 0;  in rts5260_card_power_on()
228 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);  in rts5260_switch_output_voltage()
245 	return 0;  in rts5260_switch_output_voltage()
267 	int err = 0;  in rts5260_card_power_off()
309 					RTS5260_DVCC_OCP_CL_EN, 0);  in rts5260_init_ocp()
315 	u8 val = 0;  in rts5260_enable_ocp()
318 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);  in rts5260_enable_ocp()
324 	u8 mask = 0;  in rts5260_disable_ocp()
327 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5260_disable_ocp()
344 	u8 mask = 0;  in rts5260_clear_ocpstat()
345 	u8 val = 0;  in rts5260_clear_ocpstat()
355 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5260_clear_ocpstat()
357 				DV3318_OCP_INT_CLR | DV3318_OCP_CLR, 0);  in rts5260_clear_ocpstat()
371 		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);  in rts5260_process_ocp()
373 		pcr->ocp_stat = 0;  in rts5260_process_ocp()
374 		pcr->ocp_stat2 = 0;  in rts5260_process_ocp()
388 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);  in rts5260_init_hw()
391 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWD_SUSPEND_EN, 0xFF, 0xFF);  in rts5260_init_hw()
400 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);  in rts5260_init_hw()
402 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);  in rts5260_init_hw()
408 	if (err < 0)  in rts5260_init_hw()
413 	return 0;  in rts5260_init_hw()
425 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);  in rts5260_pwr_saving_setting()
429 					0xFF, PCIE_L1_2_EN);  in rts5260_pwr_saving_setting()
437 					0xFF, PCIE_L1_2_PD_FE_EN);  in rts5260_pwr_saving_setting()
441 					0xFF, PCIE_L1_1_EN);  in rts5260_pwr_saving_setting()
443 					0xFF, PCIE_L1_1_PD_FE_EN);  in rts5260_pwr_saving_setting()
447 					0xFF, PCIE_L1_0_EN);  in rts5260_pwr_saving_setting()
449 					0xFF, PCIE_L1_0_PD_FE_EN);  in rts5260_pwr_saving_setting()
453 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);  in rts5260_pwr_saving_setting()
455 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);  in rts5260_pwr_saving_setting()
457 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);  in rts5260_pwr_saving_setting()
459 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);  in rts5260_pwr_saving_setting()
461 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);  in rts5260_pwr_saving_setting()
464 				0xFF, CFG_PCIE_APHY_OFF_0_DEFAULT);  in rts5260_pwr_saving_setting()
466 				0xFF, CFG_PCIE_APHY_OFF_1_DEFAULT);  in rts5260_pwr_saving_setting()
468 				0xFF, CFG_PCIE_APHY_OFF_2_DEFAULT);  in rts5260_pwr_saving_setting()
470 				0xFF, CFG_PCIE_APHY_OFF_3_DEFAULT);  in rts5260_pwr_saving_setting()
472 	rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT);  in rts5260_pwr_saving_setting()
475 				0xFF, CFG_LP_FPWM_VALUE_DEFAULT);  in rts5260_pwr_saving_setting()
478 				0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);  in rts5260_pwr_saving_setting()
498 	rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);  in rts5260_extra_init_hw()
499 	rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);  in rts5260_extra_init_hw()
505 				0xFF, RTS5260_MIMO_DISABLE);  in rts5260_extra_init_hw()
525 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);  in rts5260_extra_init_hw()
527 	return 0;  in rts5260_extra_init_hw()
536 	u8 val = 0;  in rts5260_set_l1off_cfg_sub_d0()
591 	pcr->flags = 0;  in rts5260_init_params()