Lines Matching +full:regulator +full:- +full:over +full:- +full:current +full:- +full:protection
1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * regulator safety limits (like limits for the over/under -voltages, over
14 * current, thermal protection) would require the configuring driver to be
25 * which implements some of the safety limit configurations - but leaves the
40 #include <linux/mfd/rohm-bd96801.h>
41 #include <linux/mfd/rohm-bd96802.h>
42 #include <linux/mfd/rohm-generic.h>
59 DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "otp-err"),
60 DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "dbist-err"),
61 DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "eep-err"),
62 DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "abist-err"),
63 DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "prstb-err"),
66 DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "slave-err"),
67 DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "vref-err"),
69 DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "uvlo-err"),
70 DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "ovlo-err"),
71 DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "osc-err"),
72 DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "pon-err"),
73 DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "poff-err"),
74 DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "cmd-shdn-err"),
76 DEFINE_RES_IRQ_NAMED(BD96801_INT_PRSTB_WDT_ERR, "bd96801-prstb-wdt-err"),
77 DEFINE_RES_IRQ_NAMED(BD96801_INT_CHIP_IF_ERR, "bd96801-chip-if-err"),
79 DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "int-shdn-err"),
81 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "buck1-pvin-err"),
82 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "buck1-ovp-err"),
83 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "buck1-uvp-err"),
84 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "buck1-shdn-err"),
86 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "buck2-pvin-err"),
87 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "buck2-ovp-err"),
88 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "buck2-uvp-err"),
89 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "buck2-shdn-err"),
91 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "buck3-pvin-err"),
92 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "buck3-ovp-err"),
93 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "buck3-uvp-err"),
94 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "buck3-shdn-err"),
96 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "buck4-pvin-err"),
97 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "buck4-ovp-err"),
98 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "buck4-uvp-err"),
99 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "buck4-shdn-err"),
101 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "ldo5-pvin-err"),
102 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "ldo5-ovp-err"),
103 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "ldo5-uvp-err"),
104 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "ldo5-shdn-err"),
106 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "ldo6-pvin-err"),
107 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "ldo6-ovp-err"),
108 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "ldo6-uvp-err"),
109 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "ldo6-shdn-err"),
111 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "ldo7-pvin-err"),
112 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "ldo7-ovp-err"),
113 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "ldo7-uvp-err"),
114 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "ldo7-shdn-err"),
118 DEFINE_RES_IRQ_NAMED(BD96802_OTP_ERR_STAT, "otp-err"),
119 DEFINE_RES_IRQ_NAMED(BD96802_DBIST_ERR_STAT, "dbist-err"),
120 DEFINE_RES_IRQ_NAMED(BD96802_EEP_ERR_STAT, "eep-err"),
121 DEFINE_RES_IRQ_NAMED(BD96802_ABIST_ERR_STAT, "abist-err"),
122 DEFINE_RES_IRQ_NAMED(BD96802_PRSTB_ERR_STAT, "prstb-err"),
125 DEFINE_RES_IRQ_NAMED(BD96802_SLAVE_ERR_STAT, "slave-err"),
126 DEFINE_RES_IRQ_NAMED(BD96802_VREF_ERR_STAT, "vref-err"),
128 DEFINE_RES_IRQ_NAMED(BD96802_UVLO_ERR_STAT, "uvlo-err"),
129 DEFINE_RES_IRQ_NAMED(BD96802_OVLO_ERR_STAT, "ovlo-err"),
130 DEFINE_RES_IRQ_NAMED(BD96802_OSC_ERR_STAT, "osc-err"),
131 DEFINE_RES_IRQ_NAMED(BD96802_PON_ERR_STAT, "pon-err"),
132 DEFINE_RES_IRQ_NAMED(BD96802_POFF_ERR_STAT, "poff-err"),
133 DEFINE_RES_IRQ_NAMED(BD96802_CMD_SHDN_ERR_STAT, "cmd-shdn-err"),
134 DEFINE_RES_IRQ_NAMED(BD96802_INT_SHDN_ERR_STAT, "int-shdn-err"),
136 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_PVIN_ERR_STAT, "buck1-pvin-err"),
137 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVP_ERR_STAT, "buck1-ovp-err"),
138 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVP_ERR_STAT, "buck1-uvp-err"),
139 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_SHDN_ERR_STAT, "buck1-shdn-err"),
141 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_PVIN_ERR_STAT, "buck2-pvin-err"),
142 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVP_ERR_STAT, "buck2-ovp-err"),
143 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVP_ERR_STAT, "buck2-uvp-err"),
144 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_SHDN_ERR_STAT, "buck2-shdn-err"),
148 DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "core-thermal"),
150 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "buck1-overcurr-h"),
151 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "buck1-overcurr-l"),
152 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "buck1-overcurr-n"),
153 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "buck1-overvolt"),
154 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "buck1-undervolt"),
155 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "buck1-thermal"),
157 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "buck2-overcurr-h"),
158 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "buck2-overcurr-l"),
159 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "buck2-overcurr-n"),
160 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "buck2-overvolt"),
161 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "buck2-undervolt"),
162 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "buck2-thermal"),
164 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "buck3-overcurr-h"),
165 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "buck3-overcurr-l"),
166 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "buck3-overcurr-n"),
167 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "buck3-overvolt"),
168 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "buck3-undervolt"),
169 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "buck3-thermal"),
171 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "buck4-overcurr-h"),
172 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "buck4-overcurr-l"),
173 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "buck4-overcurr-n"),
174 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "buck4-overvolt"),
175 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "buck4-undervolt"),
176 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "buck4-thermal"),
178 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "ldo5-overcurr"),
179 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "ldo5-overvolt"),
180 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "ldo5-undervolt"),
182 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "ldo6-overcurr"),
183 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "ldo6-overvolt"),
184 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "ldo6-undervolt"),
186 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "ldo7-overcurr"),
187 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "ldo7-overvolt"),
188 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "ldo7-undervolt"),
192 DEFINE_RES_IRQ_NAMED(BD96802_TW_STAT, "core-thermal"),
194 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPH_STAT, "buck1-overcurr-h"),
195 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPL_STAT, "buck1-overcurr-l"),
196 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPN_STAT, "buck1-overcurr-n"),
197 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVD_STAT, "buck1-overvolt"),
198 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVD_STAT, "buck1-undervolt"),
199 DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_TW_CH_STAT, "buck1-thermal"),
201 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPH_STAT, "buck2-overcurr-h"),
202 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPL_STAT, "buck2-overcurr-l"),
203 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPN_STAT, "buck2-overcurr-n"),
204 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVD_STAT, "buck2-overvolt"),
205 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVD_STAT, "buck2-undervolt"),
206 DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_TW_CH_STAT, "buck2-thermal"),
215 [WDG_CELL] = { .name = "bd96801-wdt", },
216 [REGULATOR_CELL] = { .name = "bd96801-regulator", },
220 [WDG_CELL] = { .name = "bd96801-wdt", },
221 [REGULATOR_CELL] = { .name = "bd96802-regulator", },
224 [WDG_CELL] = { .name = "bd96801-wdt", },
225 [REGULATOR_CELL] = { .name = "bd96805-regulator", },
229 [WDG_CELL] = { .name = "bd96806-wdt", },
230 [REGULATOR_CELL] = { .name = "bd96806-regulator", },
470 * For ERRB, mapping from main status to sub-status is such that the
471 * 'global' faults are mapped to first 3 sub-status registers - and indicated
475 * regulators, 1 sub register / regulator and 1 main status register bit /
476 * regulator, starting from bit[1].
478 * Eg, regulator specific stuff has 1 to 1 mapping from main-status to sub
486 * 1 to 1 mapping - BD96801 just having 5 register and 5 main status bits
490 * ERRB IRQs asserted but for different sub-status offsets. This might lead
503 * later disable main-status usage on systems where this ever proves to be
508 .name = "bd96801-irq-errb",
524 .name = "bd96802-irq-errb",
540 .name = "bd96801-irq-intb",
555 .name = "bd96802-irq-intb",
653 chip_type = (unsigned int)(uintptr_t)device_get_match_data(&i2c->dev); in bd96801_i2c_probe()
668 dev_err(&i2c->dev, "Unknown IC\n"); in bd96801_i2c_probe()
669 return -EINVAL; in bd96801_i2c_probe()
672 fwnode = dev_fwnode(&i2c->dev); in bd96801_i2c_probe()
674 return dev_err_probe(&i2c->dev, -EINVAL, "Failed to find fwnode\n"); in bd96801_i2c_probe()
678 return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n"); in bd96801_i2c_probe()
682 if (errb_irq == -EPROBE_DEFER) in bd96801_i2c_probe()
686 num_errb = ddata->num_errb_irqs; in bd96801_i2c_probe()
688 num_regu_irqs = ddata->num_intb_irqs + num_errb; in bd96801_i2c_probe()
690 regulator_res = devm_kcalloc(&i2c->dev, num_regu_irqs, in bd96801_i2c_probe()
693 return -ENOMEM; in bd96801_i2c_probe()
695 regmap = devm_regmap_init_i2c(i2c, ddata->regmap_config); in bd96801_i2c_probe()
697 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), in bd96801_i2c_probe()
700 ret = regmap_write(regmap, ddata->unlock_reg, ddata->unlock_val); in bd96801_i2c_probe()
702 return dev_err_probe(&i2c->dev, ret, "Failed to unlock PMIC\n"); in bd96801_i2c_probe()
704 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, intb_irq, in bd96801_i2c_probe()
705 IRQF_ONESHOT, 0, ddata->intb_irq_chip, in bd96801_i2c_probe()
708 return dev_err_probe(&i2c->dev, ret, "Failed to add INTB IRQ chip\n"); in bd96801_i2c_probe()
715 * already mapped IRQ numbers to sub-devices. in bd96801_i2c_probe()
717 for (i = 0; i < ddata->num_intb_irqs; i++) { in bd96801_i2c_probe()
720 *res = ddata->intb_irqs[i]; in bd96801_i2c_probe()
721 res->start = res->end = irq_create_mapping(intb_domain, in bd96801_i2c_probe()
722 res->start); in bd96801_i2c_probe()
726 wdg_irq = DEFINE_RES_IRQ_NAMED(wdg_irq_no, "bd96801-wdg"); in bd96801_i2c_probe()
728 ddata->cells[WDG_CELL].resources = &wdg_irq; in bd96801_i2c_probe()
729 ddata->cells[WDG_CELL].num_resources = 1; in bd96801_i2c_probe()
734 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, errb_irq, IRQF_ONESHOT, in bd96801_i2c_probe()
735 0, ddata->errb_irq_chip, &errb_irq_data); in bd96801_i2c_probe()
737 return dev_err_probe(&i2c->dev, ret, in bd96801_i2c_probe()
743 struct resource *res = ®ulator_res[ddata->num_intb_irqs + i]; in bd96801_i2c_probe()
745 *res = ddata->errb_irqs[i]; in bd96801_i2c_probe()
746 res->start = res->end = irq_create_mapping(errb_domain, res->start); in bd96801_i2c_probe()
750 ddata->cells[REGULATOR_CELL].resources = regulator_res; in bd96801_i2c_probe()
751 ddata->cells[REGULATOR_CELL].num_resources = num_regu_irqs; in bd96801_i2c_probe()
752 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, ddata->cells, in bd96801_i2c_probe()
753 ddata->num_cells, NULL, 0, NULL); in bd96801_i2c_probe()
755 dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); in bd96801_i2c_probe()
771 .name = "rohm-bd96801",