1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
99 	[RC5T583_IRQ_CLKSTP]		= RC5T583_IRQ(SYS_INT,  0, 4, 4, 0),
116 	[RC5T583_IRQ_AIN1L]		= RC5T583_IRQ(ADC_INT,  3, 0, 0, 4),
117 	[RC5T583_IRQ_AIN2L]		= RC5T583_IRQ(ADC_INT,  3, 1, 1, 4),
118 	[RC5T583_IRQ_AIN3L]		= RC5T583_IRQ(ADC_INT,  3, 2, 2, 4),
119 	[RC5T583_IRQ_VBATL]		= RC5T583_IRQ(ADC_INT,  3, 3, 3, 4),
120 	[RC5T583_IRQ_VIN3L]		= RC5T583_IRQ(ADC_INT,  3, 4, 4, 4),
121 	[RC5T583_IRQ_VIN8L]		= RC5T583_IRQ(ADC_INT,  3, 5, 5, 4),
126 	[RC5T583_IRQ_VIN3H]		= RC5T583_IRQ(ADC_INT,  3, 10, 4, 5),
130 	[RC5T583_IRQ_GPIO0]		= RC5T583_IRQ(GPIO_INT, 4, 0, 0, 7),
131 	[RC5T583_IRQ_GPIO1]		= RC5T583_IRQ(GPIO_INT, 4, 1, 1, 7),
132 	[RC5T583_IRQ_GPIO2]		= RC5T583_IRQ(GPIO_INT, 4, 2, 2, 7),
133 	[RC5T583_IRQ_GPIO3]		= RC5T583_IRQ(GPIO_INT, 4, 3, 3, 7),
134 	[RC5T583_IRQ_GPIO4]		= RC5T583_IRQ(GPIO_INT, 4, 4, 4, 7),
135 	[RC5T583_IRQ_GPIO5]		= RC5T583_IRQ(GPIO_INT, 4, 5, 5, 7),
136 	[RC5T583_IRQ_GPIO6]		= RC5T583_IRQ(GPIO_INT, 4, 6, 6, 7),
137 	[RC5T583_IRQ_GPIO7]		= RC5T583_IRQ(GPIO_INT, 4, 7, 7, 7),
143 	mutex_lock(&rc5t583->irq_lock);  in rc5t583_irq_lock()
149 	unsigned int __irq = irq_data->irq - rc5t583->irq_base;  in rc5t583_irq_unmask()
150 	const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];  in rc5t583_irq_unmask()  local
152 	rc5t583->group_irq_en[data->grp_index] |= 1 << data->grp_index;  in rc5t583_irq_unmask()
153 	rc5t583->intc_inten_reg |= 1 << data->master_bit;  in rc5t583_irq_unmask()
154 	rc5t583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit;  in rc5t583_irq_unmask()
160 	unsigned int __irq = irq_data->irq - rc5t583->irq_base;  in rc5t583_irq_mask()
161 	const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];  in rc5t583_irq_mask()  local
163 	rc5t583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index);  in rc5t583_irq_mask()
164 	if (!rc5t583->group_irq_en[data->grp_index])  in rc5t583_irq_mask()
165 		rc5t583->intc_inten_reg &= ~(1 << data->master_bit);  in rc5t583_irq_mask()
167 	rc5t583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit);  in rc5t583_irq_mask()
173 	unsigned int __irq = irq_data->irq - rc5t583->irq_base;  in rc5t583_irq_set_type()
174 	const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];  in rc5t583_irq_set_type()  local
180 	if ((data->int_type & GPIO_INT) && (type & IRQ_TYPE_EDGE_BOTH)) {  in rc5t583_irq_set_type()
181 		gpedge_index = data->int_en_bit / 4;  in rc5t583_irq_set_type()
182 		gpedge_bit_pos = data->int_en_bit % 4;  in rc5t583_irq_set_type()
190 		rc5t583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);  in rc5t583_irq_set_type()
191 		rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);  in rc5t583_irq_set_type()
195 	return -EINVAL;  in rc5t583_irq_set_type()
204 	for (i = 0; i < ARRAY_SIZE(rc5t583->gpedge_reg); i++) {  in rc5t583_irq_sync_unlock()
205 		ret = rc5t583_write(rc5t583->dev, gpedge_add[i],  in rc5t583_irq_sync_unlock()
206 				rc5t583->gpedge_reg[i]);  in rc5t583_irq_sync_unlock()
208 			dev_warn(rc5t583->dev,  in rc5t583_irq_sync_unlock()
213 	for (i = 0; i < ARRAY_SIZE(rc5t583->irq_en_reg); i++) {  in rc5t583_irq_sync_unlock()
214 		ret = rc5t583_write(rc5t583->dev, irq_en_add[i],  in rc5t583_irq_sync_unlock()
215 					rc5t583->irq_en_reg[i]);  in rc5t583_irq_sync_unlock()
217 			dev_warn(rc5t583->dev,  in rc5t583_irq_sync_unlock()
222 	ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN,  in rc5t583_irq_sync_unlock()
223 				rc5t583->intc_inten_reg);  in rc5t583_irq_sync_unlock()
225 		dev_warn(rc5t583->dev,  in rc5t583_irq_sync_unlock()
229 	mutex_unlock(&rc5t583->irq_lock);  in rc5t583_irq_sync_unlock()
235 	return irq_set_irq_wake(rc5t583->chip_irq, on);  in rc5t583_irq_set_wake()
238 static irqreturn_t rc5t583_irq(int irq, void *data)  in rc5t583_irq()  argument
240 	struct rc5t583 *rc5t583 = data;  in rc5t583_irq()
251 	ret  = rc5t583_read(rc5t583->dev, RC5T583_INTC_INTMON, &master_int);  in rc5t583_irq()
253 		dev_err(rc5t583->dev,  in rc5t583_irq()
263 		ret = rc5t583_read(rc5t583->dev, irq_mon_add[i], &int_sts[i]);  in rc5t583_irq()
265 			dev_warn(rc5t583->dev,  in rc5t583_irq()
284 		ret = rc5t583_write(rc5t583->dev, irq_clr_add[i],  in rc5t583_irq()
287 			dev_warn(rc5t583->dev,  in rc5t583_irq()
300 		const struct rc5t583_irq_data *data = &rc5t583_irqs[i];  in rc5t583_irq()  local
301 		if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&  in rc5t583_irq()
302 			(rc5t583->group_irq_en[data->master_bit] &  in rc5t583_irq()
303 					(1 << data->grp_index)))  in rc5t583_irq()
304 			handle_nested_irq(rc5t583->irq_base + i);  in rc5t583_irq()
311 	.name = "rc5t583-irq",
325 		dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");  in rc5t583_irq_init()
326 		return -EINVAL;  in rc5t583_irq_init()
329 	mutex_init(&rc5t583->irq_lock);  in rc5t583_irq_init()
333 		ret = rc5t583_write(rc5t583->dev, irq_en_add[i],  in rc5t583_irq_init()
334 				rc5t583->irq_en_reg[i]);  in rc5t583_irq_init()
336 			dev_warn(rc5t583->dev,  in rc5t583_irq_init()
342 		ret = rc5t583_write(rc5t583->dev, gpedge_add[i],  in rc5t583_irq_init()
343 				rc5t583->gpedge_reg[i]);  in rc5t583_irq_init()
345 			dev_warn(rc5t583->dev,  in rc5t583_irq_init()
350 	ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 0x0);  in rc5t583_irq_init()
352 		dev_warn(rc5t583->dev,  in rc5t583_irq_init()
358 		ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 0);  in rc5t583_irq_init()
360 			dev_warn(rc5t583->dev,  in rc5t583_irq_init()
365 	rc5t583->irq_base = irq_base;  in rc5t583_irq_init()
366 	rc5t583->chip_irq = irq;  in rc5t583_irq_init()
369 		int __irq = i + rc5t583->irq_base;  in rc5t583_irq_init()
377 	ret = devm_request_threaded_irq(rc5t583->dev, irq, NULL, rc5t583_irq,  in rc5t583_irq_init()
380 		dev_err(rc5t583->dev,  in rc5t583_irq_init()