Lines Matching +full:0 +full:x71000000
30 #define REG_DEV_CPUORG_IF_CTRL 0x0000
31 #define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
33 #define CFGSTAT_IF_NUM_VCORE (0 << 24)
38 #define VSC7512_DEVCPU_ORG_RES_START 0x71000000
39 #define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
41 #define VSC7512_CHIP_REGS_RES_START 0x71070000
42 #define VSC7512_CHIP_REGS_RES_SIZE 0x14
64 * our CPU. These are two bits (0 and 1) but they're repeated such that in ocelot_spi_initialize()
68 * 0b00: little-endian, MSB first in ocelot_spi_initialize()
72 * 0b01: big-endian, MSB first in ocelot_spi_initialize()
76 * 0b10: little-endian, LSB first in ocelot_spi_initialize()
80 * 0b11: big-endian, LSB first in ocelot_spi_initialize()
102 * 0:3. in ocelot_spi_initialize()
122 return 0; in ocelot_spi_initialize()
131 .write_flag_mask = 0x80,
144 struct spi_transfer xfers[3] = {0}; in ocelot_spi_regmap_bus_read()
148 unsigned int index = 0; in ocelot_spi_regmap_bus_read()
212 ddata->spi_padding_bytes = 0; in ocelot_spi_probe()
270 return 0; in ocelot_spi_probe()
274 { "vsc7512", 0 },