1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/clk-provider.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
37 #include "intel-lpss.h"
49 /* Offsets from lpss->priv */
108  * Cells needs to be ordered so that the iDMA is created first. This is
125 	.name = "dw-apb-uart",
131 	.name = "pxa2xx-spi",
141 	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);  in intel_lpss_cache_ltr()
142 	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);  in intel_lpss_cache_ltr()
149 	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);  in intel_lpss_debugfs_add()
156 	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);  in intel_lpss_debugfs_add()
157 	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);  in intel_lpss_debugfs_add()
158 	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);  in intel_lpss_debugfs_add()
160 	lpss->debugfs = dir;  in intel_lpss_debugfs_add()
166 	debugfs_remove_recursive(lpss->debugfs);  in intel_lpss_debugfs_remove()
179 	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);  in intel_lpss_ltr_set()
194 	if (ltr == lpss->active_ltr)  in intel_lpss_ltr_set()
197 	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);  in intel_lpss_ltr_set()
198 	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);  in intel_lpss_ltr_set()
206 	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;  in intel_lpss_ltr_expose()
207 	dev_pm_qos_expose_latency_tolerance(lpss->dev);  in intel_lpss_ltr_expose()
212 	dev_pm_qos_hide_latency_tolerance(lpss->dev);  in intel_lpss_ltr_hide()
213 	lpss->dev->power.set_latency_tolerance = NULL;  in intel_lpss_ltr_hide()
221 	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;  in intel_lpss_assign_devs()
235 		return -ENODEV;  in intel_lpss_assign_devs()
238 	lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);  in intel_lpss_assign_devs()
239 	if (!lpss->cell)  in intel_lpss_assign_devs()
240 		return -ENOMEM;  in intel_lpss_assign_devs()
242 	lpss->type = type;  in intel_lpss_assign_devs()
249 	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;  in intel_lpss_has_idma()
254 	resource_size_t addr = lpss->info->mem->start;  in intel_lpss_set_remap_addr()  local
256 	lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);  in intel_lpss_set_remap_addr()
264 	writel(value, lpss->priv + LPSS_PRIV_RESETS);  in intel_lpss_deassert_reset()
272 	writel(0, lpss->priv + LPSS_PRIV_RESETS);  in intel_lpss_init_dev()
281 	/* Make sure that SPI multiblock DMA transfers are re-enabled */  in intel_lpss_init_dev()
282 	if (lpss->type == LPSS_DEV_SPI)  in intel_lpss_init_dev()
283 		writel(value, lpss->priv + LPSS_PRIV_SSP_REG);  in intel_lpss_init_dev()
305 	snprintf(name, sizeof(name), "%s-enable", devname);  in intel_lpss_register_clock_divider()
307 				lpss->priv, 0, 0, NULL);  in intel_lpss_register_clock_divider()
311 	snprintf(name, sizeof(name), "%s-div", devname);  in intel_lpss_register_clock_divider()
313 					      0, lpss->priv, 1, 15, 16, 15,  in intel_lpss_register_clock_divider()
320 	if (lpss->info->quirks & QUIRK_CLOCK_DIVIDER_UNITY) {  in intel_lpss_register_clock_divider()
321 		ret = clk_set_rate(tmp, lpss->info->clk_rate);  in intel_lpss_register_clock_divider()
326 	snprintf(name, sizeof(name), "%s-update", devname);  in intel_lpss_register_clock_divider()
328 				CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);  in intel_lpss_register_clock_divider()
338 	const struct mfd_cell *cell = lpss->cell;  in intel_lpss_register_clock()
343 	if (!lpss->info->clk_rate)  in intel_lpss_register_clock()
347 	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,  in intel_lpss_register_clock()
348 				      lpss->info->clk_rate);  in intel_lpss_register_clock()
352 	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);  in intel_lpss_register_clock()
358 	if (lpss->type != LPSS_DEV_I2C) {  in intel_lpss_register_clock()
364 	ret = -ENOMEM;  in intel_lpss_register_clock()
367 	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);  in intel_lpss_register_clock()
368 	if (!lpss->clock)  in intel_lpss_register_clock()
371 	lpss->clk = clk;  in intel_lpss_register_clock()
383 	if (IS_ERR_OR_NULL(lpss->clk))  in intel_lpss_unregister_clock()
386 	clkdev_drop(lpss->clock);  in intel_lpss_unregister_clock()
387 	intel_lpss_unregister_clock_tree(lpss->clk);  in intel_lpss_unregister_clock()
396 	if (!info || !info->mem)  in intel_lpss_probe()
397 		return -EINVAL;  in intel_lpss_probe()
399 	if (info->irq < 0)  in intel_lpss_probe()
400 		return info->irq;  in intel_lpss_probe()
404 		return -ENOMEM;  in intel_lpss_probe()
406 	lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,  in intel_lpss_probe()
408 	if (!lpss->priv)  in intel_lpss_probe()
409 		return -ENOMEM;  in intel_lpss_probe()
411 	lpss->info = info;  in intel_lpss_probe()
412 	lpss->dev = dev;  in intel_lpss_probe()
413 	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);  in intel_lpss_probe()
421 	lpss->cell->swnode = info->swnode;  in intel_lpss_probe()
422 	lpss->cell->ignore_resource_conflicts = info->quirks & QUIRK_IGNORE_RESOURCE_CONFLICTS;  in intel_lpss_probe()
426 	lpss->devid = ida_alloc(&intel_lpss_devid_ida, GFP_KERNEL);  in intel_lpss_probe()
427 	if (lpss->devid < 0)  in intel_lpss_probe()
428 		return lpss->devid;  in intel_lpss_probe()
441 		ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,  in intel_lpss_probe()
442 				      1, info->mem, info->irq, NULL);  in intel_lpss_probe()
448 	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,  in intel_lpss_probe()
449 			      1, info->mem, info->irq, NULL);  in intel_lpss_probe()
463 	ida_free(&intel_lpss_devid_ida, lpss->devid);  in intel_lpss_probe()
477 	ida_free(&intel_lpss_devid_ida, lpss->devid);  in intel_lpss_remove()
506 		lpss->priv_ctx[i] = readl(lpss->priv + i * 4);  in intel_lpss_suspend()
513 	if (lpss->type != LPSS_DEV_UART)  in intel_lpss_suspend()
514 		writel(0, lpss->priv + LPSS_PRIV_RESETS);  in intel_lpss_suspend()
528 		writel(lpss->priv_ctx[i], lpss->priv + i * 4);  in intel_lpss_resume()