42 #define CS42L43_MCU_UPDATE_OFFSET		0x100000
46 #define CS42L43_MCU_ROM_REV			0x2001
47 #define CS42L43_MCU_ROM_BIOS_REV		0x0000
49 #define CS42L43_MCU_SUPPORTED_REV		0x2105
50 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV	0x2200
51 #define CS42L43_MCU_SUPPORTED_BIOS_REV		0x0001
75 	{ 0x4000,					0x00000055 },
76 	{ 0x4000,					0x000000AA },
77 	{ 0x10084,					0x00000000 },
78 	{ 0x1741C,					0x00CD2000 },
79 	{ 0x1718C,					0x00000003 },
80 	{ 0x4000,					0x00000000 },
81 	{ CS42L43_CCM_BLK_CLK_CONTROL,			0x00000002 },
82 	{ CS42L43_HPPATHVOL,				0x011B011B },
83 	{ CS42L43_OSC_DIV_SEL,				0x00000001 },
84 	{ CS42L43_DACCNFG2,				0x00000005 },
85 	{ CS42L43_MIC_DETECT_CONTROL_ANDROID,		0x80790079 },
86 	{ CS42L43_RELID,				0x0000000F },
90 	{ CS42L43_DRV_CTRL1,				0x000186C0 },
91 	{ CS42L43_DRV_CTRL3,				0x286DB018 },
92 	{ CS42L43_DRV_CTRL4,				0x000006D8 },
93 	{ CS42L43_DRV_CTRL_5,				0x136C00C0 },
94 	{ CS42L43_GPIO_CTRL1,				0x00000707 },
95 	{ CS42L43_GPIO_CTRL2,				0x00000000 },
96 	{ CS42L43_GPIO_FN_SEL,				0x00000004 },
97 	{ CS42L43_MCLK_SRC_SEL,				0x00000000 },
98 	{ CS42L43_SAMPLE_RATE1,				0x00000003 },
99 	{ CS42L43_SAMPLE_RATE2,				0x00000003 },
100 	{ CS42L43_SAMPLE_RATE3,				0x00000003 },
101 	{ CS42L43_SAMPLE_RATE4,				0x00000003 },
102 	{ CS42L43_PLL_CONTROL,				0x00000000 },
103 	{ CS42L43_FS_SELECT1,				0x00000000 },
104 	{ CS42L43_FS_SELECT2,				0x00000000 },
105 	{ CS42L43_FS_SELECT3,				0x00000000 },
106 	{ CS42L43_FS_SELECT4,				0x00000000 },
107 	{ CS42L43_PDM_CONTROL,				0x00000000 },
108 	{ CS42L43_ASP_CLK_CONFIG1,			0x00010001 },
109 	{ CS42L43_ASP_CLK_CONFIG2,			0x00000000 },
110 	{ CS42L43_OSC_DIV_SEL,				0x00000001 },
111 	{ CS42L43_ADC_B_CTRL1,				0x00000000 },
112 	{ CS42L43_ADC_B_CTRL2,				0x00000000 },
113 	{ CS42L43_DECIM_HPF_WNF_CTRL1,			0x00000001 },
114 	{ CS42L43_DECIM_HPF_WNF_CTRL2,			0x00000001 },
115 	{ CS42L43_DECIM_HPF_WNF_CTRL3,			0x00000001 },
116 	{ CS42L43_DECIM_HPF_WNF_CTRL4,			0x00000001 },
117 	{ CS42L43_DMIC_PDM_CTRL,			0x00000000 },
118 	{ CS42L43_DECIM_VOL_CTRL_CH1_CH2,		0x20122012 },
119 	{ CS42L43_DECIM_VOL_CTRL_CH3_CH4,		0x20122012 },
120 	{ CS42L43_INTP_VOLUME_CTRL1,			0x00000180 },
121 	{ CS42L43_INTP_VOLUME_CTRL2,			0x00000180 },
122 	{ CS42L43_AMP1_2_VOL_RAMP,			0x00000022 },
123 	{ CS42L43_ASP_CTRL,				0x00000004 },
124 	{ CS42L43_ASP_FSYNC_CTRL1,			0x000000FA },
125 	{ CS42L43_ASP_FSYNC_CTRL2,			0x00000001 },
126 	{ CS42L43_ASP_FSYNC_CTRL3,			0x00000000 },
127 	{ CS42L43_ASP_FSYNC_CTRL4,			0x000001F4 },
128 	{ CS42L43_ASP_DATA_CTRL,			0x0000003A },
129 	{ CS42L43_ASP_RX_EN,				0x00000000 },
130 	{ CS42L43_ASP_TX_EN,				0x00000000 },
131 	{ CS42L43_ASP_RX_CH1_CTRL,			0x00170001 },
132 	{ CS42L43_ASP_RX_CH2_CTRL,			0x00170031 },
133 	{ CS42L43_ASP_RX_CH3_CTRL,			0x00170061 },
134 	{ CS42L43_ASP_RX_CH4_CTRL,			0x00170091 },
135 	{ CS42L43_ASP_RX_CH5_CTRL,			0x001700C1 },
136 	{ CS42L43_ASP_RX_CH6_CTRL,			0x001700F1 },
137 	{ CS42L43_ASP_TX_CH1_CTRL,			0x00170001 },
138 	{ CS42L43_ASP_TX_CH2_CTRL,			0x00170031 },
139 	{ CS42L43_ASP_TX_CH3_CTRL,			0x00170061 },
140 	{ CS42L43_ASP_TX_CH4_CTRL,			0x00170091 },
141 	{ CS42L43_ASP_TX_CH5_CTRL,			0x001700C1 },
142 	{ CS42L43_ASP_TX_CH6_CTRL,			0x001700F1 },
143 	{ CS42L43_ASPTX1_INPUT,				0x00000000 },
144 	{ CS42L43_ASPTX2_INPUT,				0x00000000 },
145 	{ CS42L43_ASPTX3_INPUT,				0x00000000 },
146 	{ CS42L43_ASPTX4_INPUT,				0x00000000 },
147 	{ CS42L43_ASPTX5_INPUT,				0x00000000 },
148 	{ CS42L43_ASPTX6_INPUT,				0x00000000 },
149 	{ CS42L43_SWIRE_DP1_CH1_INPUT,			0x00000000 },
150 	{ CS42L43_SWIRE_DP1_CH2_INPUT,			0x00000000 },
151 	{ CS42L43_SWIRE_DP1_CH3_INPUT,			0x00000000 },
152 	{ CS42L43_SWIRE_DP1_CH4_INPUT,			0x00000000 },
153 	{ CS42L43_SWIRE_DP2_CH1_INPUT,			0x00000000 },
154 	{ CS42L43_SWIRE_DP2_CH2_INPUT,			0x00000000 },
155 	{ CS42L43_SWIRE_DP3_CH1_INPUT,			0x00000000 },
156 	{ CS42L43_SWIRE_DP3_CH2_INPUT,			0x00000000 },
157 	{ CS42L43_SWIRE_DP4_CH1_INPUT,			0x00000000 },
158 	{ CS42L43_SWIRE_DP4_CH2_INPUT,			0x00000000 },
159 	{ CS42L43_ASRC_INT1_INPUT1,			0x00000000 },
160 	{ CS42L43_ASRC_INT2_INPUT1,			0x00000000 },
161 	{ CS42L43_ASRC_INT3_INPUT1,			0x00000000 },
162 	{ CS42L43_ASRC_INT4_INPUT1,			0x00000000 },
163 	{ CS42L43_ASRC_DEC1_INPUT1,			0x00000000 },
164 	{ CS42L43_ASRC_DEC2_INPUT1,			0x00000000 },
165 	{ CS42L43_ASRC_DEC3_INPUT1,			0x00000000 },
166 	{ CS42L43_ASRC_DEC4_INPUT1,			0x00000000 },
167 	{ CS42L43_ISRC1INT1_INPUT1,			0x00000000 },
168 	{ CS42L43_ISRC1INT2_INPUT1,			0x00000000 },
169 	{ CS42L43_ISRC1DEC1_INPUT1,			0x00000000 },
170 	{ CS42L43_ISRC1DEC2_INPUT1,			0x00000000 },
171 	{ CS42L43_ISRC2INT1_INPUT1,			0x00000000 },
172 	{ CS42L43_ISRC2INT2_INPUT1,			0x00000000 },
173 	{ CS42L43_ISRC2DEC1_INPUT1,			0x00000000 },
174 	{ CS42L43_ISRC2DEC2_INPUT1,			0x00000000 },
175 	{ CS42L43_EQ1MIX_INPUT1,			0x00800000 },
176 	{ CS42L43_EQ1MIX_INPUT2,			0x00800000 },
177 	{ CS42L43_EQ1MIX_INPUT3,			0x00800000 },
178 	{ CS42L43_EQ1MIX_INPUT4,			0x00800000 },
179 	{ CS42L43_EQ2MIX_INPUT1,			0x00800000 },
180 	{ CS42L43_EQ2MIX_INPUT2,			0x00800000 },
181 	{ CS42L43_EQ2MIX_INPUT3,			0x00800000 },
182 	{ CS42L43_EQ2MIX_INPUT4,			0x00800000 },
183 	{ CS42L43_SPDIF1_INPUT1,			0x00000000 },
184 	{ CS42L43_SPDIF2_INPUT1,			0x00000000 },
185 	{ CS42L43_AMP1MIX_INPUT1,			0x00800000 },
186 	{ CS42L43_AMP1MIX_INPUT2,			0x00800000 },
187 	{ CS42L43_AMP1MIX_INPUT3,			0x00800000 },
188 	{ CS42L43_AMP1MIX_INPUT4,			0x00800000 },
189 	{ CS42L43_AMP2MIX_INPUT1,			0x00800000 },
190 	{ CS42L43_AMP2MIX_INPUT2,			0x00800000 },
191 	{ CS42L43_AMP2MIX_INPUT3,			0x00800000 },
192 	{ CS42L43_AMP2MIX_INPUT4,			0x00800000 },
193 	{ CS42L43_AMP3MIX_INPUT1,			0x00800000 },
194 	{ CS42L43_AMP3MIX_INPUT2,			0x00800000 },
195 	{ CS42L43_AMP3MIX_INPUT3,			0x00800000 },
196 	{ CS42L43_AMP3MIX_INPUT4,			0x00800000 },
197 	{ CS42L43_AMP4MIX_INPUT1,			0x00800000 },
198 	{ CS42L43_AMP4MIX_INPUT2,			0x00800000 },
199 	{ CS42L43_AMP4MIX_INPUT3,			0x00800000 },
200 	{ CS42L43_AMP4MIX_INPUT4,			0x00800000 },
201 	{ CS42L43_ASRC_INT_ENABLES,			0x00000100 },
202 	{ CS42L43_ASRC_DEC_ENABLES,			0x00000100 },
203 	{ CS42L43_PDNCNTL,				0x00000000 },
204 	{ CS42L43_RINGSENSE_DEB_CTRL,			0x0000001B },
205 	{ CS42L43_TIPSENSE_DEB_CTRL,			0x0000001B },
206 	{ CS42L43_HS2,					0x050106F3 },
207 	{ CS42L43_STEREO_MIC_CTRL,			0x00000000 },
208 	{ CS42L43_STEREO_MIC_CLAMP_CTRL,		0x00000001 },
209 	{ CS42L43_BLOCK_EN2,				0x00000000 },
210 	{ CS42L43_BLOCK_EN3,				0x00000000 },
211 	{ CS42L43_BLOCK_EN4,				0x00000000 },
212 	{ CS42L43_BLOCK_EN5,				0x00000000 },
213 	{ CS42L43_BLOCK_EN6,				0x00000000 },
214 	{ CS42L43_BLOCK_EN7,				0x00000000 },
215 	{ CS42L43_BLOCK_EN8,				0x00000000 },
216 	{ CS42L43_BLOCK_EN9,				0x00000000 },
217 	{ CS42L43_BLOCK_EN10,				0x00000000 },
218 	{ CS42L43_BLOCK_EN11,				0x00000000 },
219 	{ CS42L43_TONE_CH1_CTRL,			0x00000000 },
220 	{ CS42L43_TONE_CH2_CTRL,			0x00000000 },
221 	{ CS42L43_MIC_DETECT_CONTROL_1,			0x00000003 },
222 	{ CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,	0x02000003 },
223 	{ CS42L43_MIC_DETECT_CONTROL_ANDROID,		0x80790079 },
224 	{ CS42L43_ISRC1_CTRL,				0x00000000 },
225 	{ CS42L43_ISRC2_CTRL,				0x00000000 },
226 	{ CS42L43_CTRL_REG,				0x00000006 },
227 	{ CS42L43_FDIV_FRAC,				0x40000000 },
228 	{ CS42L43_CAL_RATIO,				0x00000080 },
229 	{ CS42L43_SPI_CLK_CONFIG1,			0x00000001 },
230 	{ CS42L43_SPI_CONFIG1,				0x00000000 },
231 	{ CS42L43_SPI_CONFIG2,				0x00000000 },
232 	{ CS42L43_SPI_CONFIG3,				0x00000001 },
233 	{ CS42L43_SPI_CONFIG4,				0x00000000 },
234 	{ CS42L43_TRAN_CONFIG3,				0x00000000 },
235 	{ CS42L43_TRAN_CONFIG4,				0x00000000 },
236 	{ CS42L43_TRAN_CONFIG5,				0x00000000 },
237 	{ CS42L43_TRAN_CONFIG6,				0x00000000 },
238 	{ CS42L43_TRAN_CONFIG7,				0x00000000 },
239 	{ CS42L43_TRAN_CONFIG8,				0x00000000 },
240 	{ CS42L43_DACCNFG1,				0x00000008 },
241 	{ CS42L43_DACCNFG2,				0x00000005 },
242 	{ CS42L43_HPPATHVOL,				0x011B011B },
243 	{ CS42L43_PGAVOL,				0x00003470 },
244 	{ CS42L43_LOADDETENA,				0x00000000 },
245 	{ CS42L43_CTRL,					0x00000037 },
246 	{ CS42L43_COEFF_DATA_IN0,			0x00000000 },
247 	{ CS42L43_COEFF_RD_WR0,				0x00000000 },
248 	{ CS42L43_START_EQZ0,				0x00000000 },
249 	{ CS42L43_MUTE_EQ_IN0,				0x00000000 },
250 	{ CS42L43_DECIM_MASK,				0x0000000F },
251 	{ CS42L43_EQ_MIX_MASK,				0x0000000F },
252 	{ CS42L43_ASP_MASK,				0x000000FF },
253 	{ CS42L43_PLL_MASK,				0x00000003 },
254 	{ CS42L43_SOFT_MASK,				0x0000FFFF },
255 	{ CS42L43_SWIRE_MASK,				0x00007FFF },
256 	{ CS42L43_MSM_MASK,				0x00000FFF },
257 	{ CS42L43_ACC_DET_MASK,				0x00000FFF },
258 	{ CS42L43_I2C_TGT_MASK,				0x00000003 },
259 	{ CS42L43_SPI_MSTR_MASK,			0x00000007 },
260 	{ CS42L43_SW_TO_SPI_BRIDGE_MASK,		0x00000001 },
261 	{ CS42L43_OTP_MASK,				0x00000007 },
262 	{ CS42L43_CLASS_D_AMP_MASK,			0x00003FFF },
263 	{ CS42L43_GPIO_INT_MASK,			0x0000003F },
264 	{ CS42L43_ASRC_MASK,				0x0000000F },
265 	{ CS42L43_HPOUT_MASK,				0x00000003 },
584 	return 0;  in cs42l43_wait_for_attach()
605 	regmap_write(cs42l43->regmap, need_reg, 0);  in cs42l43_mcu_stage_2_3()
611 		dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val);  in cs42l43_mcu_stage_2_3()
622  * setting the HAVE configuration register to 0, and soft resetting. The
635 	regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0);  in cs42l43_mcu_stage_3_2()
654 	regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);  in cs42l43_mcu_disable()
660 		dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val);  in cs42l43_mcu_disable()
684 	hdr = (const struct cs42l43_patch_header *)&firmware->data[0];  in cs42l43_mcu_load_firmware()
695 			  &firmware->data[0], firmware->size / sizeof(u32));  in cs42l43_mcu_load_firmware()
698 	regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);  in cs42l43_mcu_load_firmware()
704 		dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val);  in cs42l43_mcu_load_firmware()
729 	return 0;  in cs42l43_mcu_is_hw_compatible()
791 	dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n",  in cs42l43_mcu_update_step()
826 		return 0;  in cs42l43_mcu_update_step()
840 	for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) {  in cs42l43_mcu_update()
888 				       cs42l43->irq, irq_flags, 0,  in cs42l43_irq_config()
895 	dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n",  in cs42l43_irq_config()
898 	return 0;  in cs42l43_irq_config()
921 		dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);  in cs42l43_boot_work()
938 		 "devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp);  in cs42l43_boot_work()
957 				   NULL, 0, NULL);  in cs42l43_boot_work()
1001 	return 0;  in cs42l43_power_up()
1006 	gpiod_set_value_cansleep(cs42l43->reset, 0);  in cs42l43_power_up()
1028 	gpiod_set_value_cansleep(cs42l43->reset, 0);  in cs42l43_power_down()
1036 	return 0;  in cs42l43_power_down()
1070 	for (i = 0; i < CS42L43_N_SUPPLIES; i++)  in cs42l43_dev_probe()
1097 	return 0;  in cs42l43_dev_probe()
1113 		{ CS42L43_DECIM_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1114 		{ CS42L43_EQ_MIX_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1115 		{ CS42L43_ASP_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1116 		{ CS42L43_PLL_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1117 		{ CS42L43_SOFT_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1118 		{ CS42L43_SWIRE_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1119 		{ CS42L43_MSM_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1120 		{ CS42L43_ACC_DET_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1121 		{ CS42L43_I2C_TGT_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1122 		{ CS42L43_SPI_MSTR_MASK,		0xFFFFFFFF, },  in cs42l43_suspend()
1123 		{ CS42L43_SW_TO_SPI_BRIDGE_MASK,	0xFFFFFFFF, },  in cs42l43_suspend()
1124 		{ CS42L43_OTP_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1125 		{ CS42L43_CLASS_D_AMP_MASK,		0xFFFFFFFF, },  in cs42l43_suspend()
1126 		{ CS42L43_GPIO_INT_MASK,		0xFFFFFFFF, },  in cs42l43_suspend()
1127 		{ CS42L43_ASRC_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1128 		{ CS42L43_HPOUT_MASK,			0xFFFFFFFF, },  in cs42l43_suspend()
1161 	return 0;  in cs42l43_suspend()
1170 	return 0;  in cs42l43_suspend_noirq()
1179 	return 0;  in cs42l43_resume_noirq()
1199 	return 0;  in cs42l43_resume()
1213 	return 0;  in cs42l43_runtime_suspend()
1250 	return 0;  in cs42l43_runtime_resume()