Lines Matching refs:str

51 	str	r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
54 	str	r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
57 	str     r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
60 	str     r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
63 	str     r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
66 	str     r1, [r2, #EMIF_PMCR_VAL_OFFSET]
69 	str     r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
72 	str     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
75 	str     r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
78 	str     r1, [r2, #EMIF_COS_CONFIG_OFFSET]
81 	str     r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
84 	str     r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
87 	str     r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
90 	str     r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
97 	str     r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
100 	str     r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
103 	str     r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
106 	str     r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
109 	str     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
112 	str     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
120 	str	r1, [r4, r5]
143 	str	r1, [r0, #EMIF_DDR_PHY_CTRL_1]
144 	str	r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
147 	str	r1, [r0, #EMIF_SDRAM_TIMING_1]
148 	str	r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
151 	str	r1, [r0, #EMIF_SDRAM_TIMING_2]
152 	str	r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
155 	str	r1, [r0, #EMIF_SDRAM_TIMING_3]
156 	str	r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
159 	str	r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
160 	str	r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
163 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
166 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
169 	str	r1, [r0, #EMIF_COS_CONFIG]
172 	str	r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
175 	str	r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
178 	str	r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
181 	str	r1, [r0, #EMIF_OCP_CONFIG]
188 	str	r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
191 	str	r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
194 	str	r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
197 	str	r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
200 	str	r1, [r0, #EMIF_DLL_CALIB_CTRL]
203 	str	r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
206 	str	r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
217 	str	r1, [r4, r5]
230 	str	r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
258 	str	r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
298 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
326 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
328 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
354 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]