Lines Matching +full:tegra124 +full:- +full:emc
1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
387 * There are multiple sources in the EMC driver which could request
392 /* protect shared rate-change code path */
398 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
418 struct tegra_emc *emc = data; in tegra_emc_isr() local
422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
428 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
432 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
437 static struct emc_timing *emc_find_timing(struct tegra_emc *emc, in emc_find_timing() argument
443 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
444 if (emc->timings[i].rate >= rate) { in emc_find_timing()
445 timing = &emc->timings[i]; in emc_find_timing()
451 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
464 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
465 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
469 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
475 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
476 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
480 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
486 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
487 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
491 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
501 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate) in emc_prepare_mc_clk_cfg() argument
503 struct tegra_mc *mc = emc->mc; in emc_prepare_mc_clk_cfg()
508 for (i = 0; i < mc->num_timings; i++) { in emc_prepare_mc_clk_cfg()
509 if (mc->timings[i].rate != rate) in emc_prepare_mc_clk_cfg()
512 if (mc->timings[i].emem_data[misc0_index] & BIT(27)) in emc_prepare_mc_clk_cfg()
517 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same); in emc_prepare_mc_clk_cfg()
520 return -EINVAL; in emc_prepare_mc_clk_cfg()
523 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
525 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_prepare_timing_change()
538 if (!timing || emc->bad_state) in emc_prepare_timing_change()
539 return -EINVAL; in emc_prepare_timing_change()
541 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
542 __func__, timing->rate, rate); in emc_prepare_timing_change()
544 emc->bad_state = true; in emc_prepare_timing_change()
546 err = emc_prepare_mc_clk_cfg(emc, rate); in emc_prepare_timing_change()
548 dev_err(emc->dev, "mc clock preparation failed: %d\n", err); in emc_prepare_timing_change()
552 emc->vref_cal_toggle = false; in emc_prepare_timing_change()
553 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
554 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
555 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_prepare_timing_change()
557 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1)) in emc_prepare_timing_change()
559 else if (timing->emc_mode_1 & 0x1) in emc_prepare_timing_change()
564 emc->dll_on = !!(timing->emc_mode_1 & 0x1); in emc_prepare_timing_change()
566 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) in emc_prepare_timing_change()
567 emc->zcal_long = true; in emc_prepare_timing_change()
569 emc->zcal_long = false; in emc_prepare_timing_change()
571 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_prepare_timing_change()
574 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_prepare_timing_change()
576 /* disable dynamic self-refresh */ in emc_prepare_timing_change()
577 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
578 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
585 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
591 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
592 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in emc_prepare_timing_change()
595 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK) in emc_prepare_timing_change()
596 mc_writel(emc->mc, in emc_prepare_timing_change()
597 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK, in emc_prepare_timing_change()
601 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) { in emc_prepare_timing_change()
607 err = emc_seq_update_timing(emc); in emc_prepare_timing_change()
614 /* disable auto-calibration if VREF mode is switching */ in emc_prepare_timing_change()
615 if (timing->emc_auto_cal_interval) { in emc_prepare_timing_change()
616 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL); in emc_prepare_timing_change()
617 val ^= timing->data[74]; in emc_prepare_timing_change()
620 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_prepare_timing_change()
623 emc->regs + EMC_AUTO_CAL_STATUS, val, in emc_prepare_timing_change()
626 dev_err(emc->dev, in emc_prepare_timing_change()
627 "auto-cal finish timeout: %d\n", err); in emc_prepare_timing_change()
631 emc->vref_cal_toggle = true; in emc_prepare_timing_change()
636 for (i = 0; i < ARRAY_SIZE(timing->data); i++) { in emc_prepare_timing_change()
639 writel_relaxed(timing->data[i], in emc_prepare_timing_change()
640 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
643 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate); in emc_prepare_timing_change()
651 if (emc->zcal_long) in emc_prepare_timing_change()
652 cnt -= dram_num * 256; in emc_prepare_timing_change()
654 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK; in emc_prepare_timing_change()
658 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; in emc_prepare_timing_change()
662 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT); in emc_prepare_timing_change()
666 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); in emc_prepare_timing_change()
674 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK; in emc_prepare_timing_change()
685 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE); in emc_prepare_timing_change()
690 emc->regs + EMC_DBG); in emc_prepare_timing_change()
691 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
692 emc->regs + EMC_CFG); in emc_prepare_timing_change()
693 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
696 /* disable auto-refresh to save time after clock change */ in emc_prepare_timing_change()
698 emc->regs + EMC_REFCTRL); in emc_prepare_timing_change()
700 /* turn off DLL and enter self-refresh on DDR3 */ in emc_prepare_timing_change()
703 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
704 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
708 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
712 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in emc_prepare_timing_change()
714 /* enable write-active MUX, update unshadowed pad control */ in emc_prepare_timing_change()
715 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
716 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL); in emc_prepare_timing_change()
718 /* restore periodic QRST and disable write-active MUX */ in emc_prepare_timing_change()
719 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
720 if (qrst_used || timing->emc_cfg_periodic_qrst != val) { in emc_prepare_timing_change()
721 if (timing->emc_cfg_periodic_qrst) in emc_prepare_timing_change()
722 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
724 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
726 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
728 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
730 /* exit self-refresh on DDR3 */ in emc_prepare_timing_change()
733 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
735 /* set DRAM-mode registers */ in emc_prepare_timing_change()
737 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
738 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
739 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
741 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
742 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
743 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
745 if (timing->emc_mode_reset != emc->emc_mode_reset || in emc_prepare_timing_change()
747 val = timing->emc_mode_reset; in emc_prepare_timing_change()
754 writel_relaxed(val, emc->regs + EMC_MRS); in emc_prepare_timing_change()
757 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
758 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
759 emc->regs + EMC_MRW); in emc_prepare_timing_change()
761 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
762 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
763 emc->regs + EMC_MRW); in emc_prepare_timing_change()
766 emc->emc_mode_1 = timing->emc_mode_1; in emc_prepare_timing_change()
767 emc->emc_mode_2 = timing->emc_mode_2; in emc_prepare_timing_change()
768 emc->emc_mode_reset = timing->emc_mode_reset; in emc_prepare_timing_change()
771 if (emc->zcal_long) { in emc_prepare_timing_change()
773 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
777 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
781 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE); in emc_prepare_timing_change()
784 * Read and discard an arbitrary MC register (Note: EMC registers in emc_prepare_timing_change()
787 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
792 static int emc_complete_timing_change(struct tegra_emc *emc, in emc_complete_timing_change() argument
795 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_complete_timing_change()
800 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
804 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
808 /* re-enable auto-refresh */ in emc_complete_timing_change()
809 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_complete_timing_change()
811 emc->regs + EMC_REFCTRL); in emc_complete_timing_change()
813 /* restore auto-calibration */ in emc_complete_timing_change()
814 if (emc->vref_cal_toggle) in emc_complete_timing_change()
815 writel_relaxed(timing->emc_auto_cal_interval, in emc_complete_timing_change()
816 emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_complete_timing_change()
818 /* restore dynamic self-refresh */ in emc_complete_timing_change()
819 if (timing->emc_cfg_dyn_self_ref) { in emc_complete_timing_change()
820 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; in emc_complete_timing_change()
821 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
825 if (emc->zcal_long) in emc_complete_timing_change()
826 writel_relaxed(timing->emc_zcal_cnt_long, in emc_complete_timing_change()
827 emc->regs + EMC_ZCAL_WAIT_CNT); in emc_complete_timing_change()
833 err = emc_seq_update_timing(emc); in emc_complete_timing_change()
835 emc->bad_state = false; in emc_complete_timing_change()
838 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); in emc_complete_timing_change()
843 static int emc_unprepare_timing_change(struct tegra_emc *emc, in emc_unprepare_timing_change() argument
846 if (!emc->bad_state) { in emc_unprepare_timing_change()
848 dev_err(emc->dev, "timing configuration can't be reverted\n"); in emc_unprepare_timing_change()
849 emc->bad_state = true; in emc_unprepare_timing_change()
858 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); in emc_clk_change_notify() local
868 disable_irq(emc->irq); in emc_clk_change_notify()
869 err = emc_prepare_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
870 enable_irq(emc->irq); in emc_clk_change_notify()
874 err = emc_unprepare_timing_change(emc, cnd->old_rate); in emc_clk_change_notify()
878 err = emc_complete_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
888 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
895 err = of_property_read_u32(node, "clock-frequency", &value); in load_one_timing_from_dt()
897 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
902 timing->rate = value; in load_one_timing_from_dt()
904 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
905 timing->data, in load_one_timing_from_dt()
908 dev_err(emc->dev, in load_one_timing_from_dt()
909 "timing %pOF: failed to read emc timing data: %d\n", in load_one_timing_from_dt()
915 timing->prop = of_property_read_bool(node, dtprop); in load_one_timing_from_dt()
918 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
920 dev_err(emc->dev, \ in load_one_timing_from_dt()
926 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
927 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
928 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
929 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
930 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
931 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref") in load_one_timing_from_dt()
932 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst") in load_one_timing_from_dt()
937 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate); in load_one_timing_from_dt()
947 if (a->rate < b->rate) in cmp_timings()
948 return -1; in cmp_timings()
950 if (a->rate > b->rate) in cmp_timings()
956 static int emc_check_mc_timings(struct tegra_emc *emc) in emc_check_mc_timings() argument
958 struct tegra_mc *mc = emc->mc; in emc_check_mc_timings()
961 if (emc->num_timings != mc->num_timings) { in emc_check_mc_timings()
962 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n", in emc_check_mc_timings()
963 emc->num_timings, mc->num_timings); in emc_check_mc_timings()
964 return -EINVAL; in emc_check_mc_timings()
967 for (i = 0; i < mc->num_timings; i++) { in emc_check_mc_timings()
968 if (emc->timings[i].rate != mc->timings[i].rate) { in emc_check_mc_timings()
969 dev_err(emc->dev, in emc_check_mc_timings()
970 "emc/mc timing rate mismatch: %lu %lu\n", in emc_check_mc_timings()
971 emc->timings[i].rate, mc->timings[i].rate); in emc_check_mc_timings()
972 return -EINVAL; in emc_check_mc_timings()
979 static int emc_load_timings_from_dt(struct tegra_emc *emc, in emc_load_timings_from_dt() argument
988 dev_err(emc->dev, "no memory timings in: %pOF\n", node); in emc_load_timings_from_dt()
989 return -EINVAL; in emc_load_timings_from_dt()
992 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in emc_load_timings_from_dt()
994 if (!emc->timings) in emc_load_timings_from_dt()
995 return -ENOMEM; in emc_load_timings_from_dt()
997 emc->num_timings = child_count; in emc_load_timings_from_dt()
998 timing = emc->timings; in emc_load_timings_from_dt()
1001 err = load_one_timing_from_dt(emc, timing++, child); in emc_load_timings_from_dt()
1006 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in emc_load_timings_from_dt()
1009 err = emc_check_mc_timings(emc); in emc_load_timings_from_dt()
1013 dev_info_once(emc->dev, in emc_load_timings_from_dt()
1015 emc->num_timings, in emc_load_timings_from_dt()
1017 emc->timings[0].rate / 1000000, in emc_load_timings_from_dt()
1018 emc->timings[emc->num_timings - 1].rate / 1000000); in emc_load_timings_from_dt()
1023 static struct device_node *emc_find_node_by_ram_code(struct tegra_emc *emc) in emc_find_node_by_ram_code() argument
1025 struct device *dev = emc->dev; in emc_find_node_by_ram_code()
1030 if (emc->mrr_error) { in emc_find_node_by_ram_code()
1035 if (of_get_child_count(dev->of_node) == 0) { in emc_find_node_by_ram_code()
1036 dev_info_once(dev, "device-tree doesn't have memory timings\n"); in emc_find_node_by_ram_code()
1042 for_each_child_of_node(dev->of_node, np) { in emc_find_node_by_ram_code()
1043 err = of_property_read_u32(np, "nvidia,ram-code", &value); in emc_find_node_by_ram_code()
1050 dev_err(dev, "no memory timings for RAM code %u found in device-tree\n", in emc_find_node_by_ram_code()
1056 static int emc_read_lpddr_mode_register(struct tegra_emc *emc, in emc_read_lpddr_mode_register() argument
1065 /* clear data-valid interrupt status */ in emc_read_lpddr_mode_register()
1066 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS); in emc_read_lpddr_mode_register()
1072 writel_relaxed(val, emc->regs + EMC_MRR); in emc_read_lpddr_mode_register()
1074 /* wait for the LPDDR2 data-valid interrupt */ in emc_read_lpddr_mode_register()
1075 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val, in emc_read_lpddr_mode_register()
1079 dev_err(emc->dev, "mode register %u read failed: %d\n", in emc_read_lpddr_mode_register()
1081 emc->mrr_error = true; in emc_read_lpddr_mode_register()
1086 val = readl_relaxed(emc->regs + EMC_MRR); in emc_read_lpddr_mode_register()
1092 static void emc_read_lpddr_sdram_info(struct tegra_emc *emc, in emc_read_lpddr_sdram_info() argument
1101 emc_read_lpddr_mode_register(emc, emem_dev, 5, &manufacturer_id); in emc_read_lpddr_sdram_info()
1102 emc_read_lpddr_mode_register(emc, emem_dev, 6, &revision_id1); in emc_read_lpddr_sdram_info()
1103 emc_read_lpddr_mode_register(emc, emem_dev, 7, &revision_id2); in emc_read_lpddr_sdram_info()
1104 emc_read_lpddr_mode_register(emc, emem_dev, 8, &basic_conf4.value); in emc_read_lpddr_sdram_info()
1106 …dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u dens… in emc_read_lpddr_sdram_info()
1115 static int emc_setup_hw(struct tegra_emc *emc) in emc_setup_hw() argument
1124 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
1127 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1129 /* enable EMC and CAR to handshake on PLL divider/source changes */ in emc_setup_hw()
1145 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
1148 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
1149 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
1152 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
1157 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
1174 emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG); in emc_setup_hw()
1177 dev_info_once(emc->dev, "%u %s %s attached\n", emem_numdev, in emc_setup_hw()
1181 while (emem_numdev--) in emc_setup_hw()
1182 emc_read_lpddr_sdram_info(emc, emem_numdev); in emc_setup_hw()
1196 struct tegra_emc *emc = arg; in emc_round_rate() local
1199 if (!emc->num_timings) in emc_round_rate()
1200 return clk_get_rate(emc->clk); in emc_round_rate()
1202 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
1204 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
1205 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
1208 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
1209 i = max(i, 1u) - 1; in emc_round_rate()
1211 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1215 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1218 timing = &emc->timings[i]; in emc_round_rate()
1223 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
1225 return -EINVAL; in emc_round_rate()
1228 return timing->rate; in emc_round_rate()
1231 static void tegra_emc_rate_requests_init(struct tegra_emc *emc) in tegra_emc_rate_requests_init() argument
1236 emc->requested_rate[i].min_rate = 0; in tegra_emc_rate_requests_init()
1237 emc->requested_rate[i].max_rate = ULONG_MAX; in tegra_emc_rate_requests_init()
1241 static int emc_request_rate(struct tegra_emc *emc, in emc_request_rate() argument
1246 struct emc_rate_request *req = emc->requested_rate; in emc_request_rate()
1257 min_rate = max(req->min_rate, min_rate); in emc_request_rate()
1258 max_rate = min(req->max_rate, max_rate); in emc_request_rate()
1263 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", in emc_request_rate()
1265 return -ERANGE; in emc_request_rate()
1269 * EMC rate-changes should go via OPP API because it manages voltage in emc_request_rate()
1272 err = dev_pm_opp_set_rate(emc->dev, min_rate); in emc_request_rate()
1276 emc->requested_rate[type].min_rate = new_min_rate; in emc_request_rate()
1277 emc->requested_rate[type].max_rate = new_max_rate; in emc_request_rate()
1282 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_min_rate() argument
1285 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_min_rate()
1288 mutex_lock(&emc->rate_lock); in emc_set_min_rate()
1289 ret = emc_request_rate(emc, rate, req->max_rate, type); in emc_set_min_rate()
1290 mutex_unlock(&emc->rate_lock); in emc_set_min_rate()
1295 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_max_rate() argument
1298 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_max_rate()
1301 mutex_lock(&emc->rate_lock); in emc_set_max_rate()
1302 ret = emc_request_rate(emc, req->min_rate, rate, type); in emc_set_max_rate()
1303 mutex_unlock(&emc->rate_lock); in emc_set_max_rate()
1312 * to control the EMC frequency. The top-level directory can be found here:
1314 * /sys/kernel/debug/emc
1318 * - available_rates: This file contains a list of valid, space-separated
1319 * EMC frequencies.
1321 * - min_rate: Writing a value to this file sets the given frequency as the
1323 * configured EMC frequency, this will cause the frequency to be
1326 * - max_rate: Similarily to the min_rate file, writing a value to this file
1328 * the value is lower than the currently configured EMC frequency, this
1333 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
1337 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1338 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1346 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
1350 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1351 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1363 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
1365 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1372 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
1375 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
1376 return -EINVAL; in tegra_emc_debug_min_rate_set()
1378 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_min_rate_set()
1382 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1393 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
1395 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1402 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
1405 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
1406 return -EINVAL; in tegra_emc_debug_max_rate_set()
1408 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_max_rate_set()
1412 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1421 static void tegra_emc_debugfs_init(struct tegra_emc *emc) in tegra_emc_debugfs_init() argument
1423 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
1427 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
1428 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
1430 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
1431 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
1432 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1434 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
1435 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1438 if (!emc->num_timings) { in tegra_emc_debugfs_init()
1439 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
1440 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
1443 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
1444 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
1446 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in tegra_emc_debugfs_init()
1447 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
1448 emc->clk); in tegra_emc_debugfs_init()
1451 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
1453 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
1454 emc, &tegra_emc_debug_available_rates_fops); in tegra_emc_debugfs_init()
1455 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1456 emc, &tegra_emc_debug_min_rate_fops); in tegra_emc_debugfs_init()
1457 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1458 emc, &tegra_emc_debug_max_rate_fops); in tegra_emc_debugfs_init()
1475 list_for_each_entry(node, &provider->nodes, node_list) { in emc_of_icc_xlate_extended()
1476 if (node->id != TEGRA_ICC_EMEM) in emc_of_icc_xlate_extended()
1481 return ERR_PTR(-ENOMEM); in emc_of_icc_xlate_extended()
1487 ndata->tag = TEGRA_MC_ICC_TAG_ISO; in emc_of_icc_xlate_extended()
1488 ndata->node = node; in emc_of_icc_xlate_extended()
1493 return ERR_PTR(-EPROBE_DEFER); in emc_of_icc_xlate_extended()
1498 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); in emc_icc_set() local
1499 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); in emc_icc_set()
1500 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); in emc_icc_set()
1507 * Tegra30 EMC runs on a clock rate of SDRAM bus. This means that in emc_icc_set()
1508 * EMC clock rate is twice smaller than the peak data rate because in emc_icc_set()
1509 * data is sampled on both EMC clock edges. in emc_icc_set()
1514 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); in emc_icc_set()
1521 static int tegra_emc_interconnect_init(struct tegra_emc *emc) in tegra_emc_interconnect_init() argument
1523 const struct tegra_mc_soc *soc = emc->mc->soc; in tegra_emc_interconnect_init()
1527 emc->provider.dev = emc->dev; in tegra_emc_interconnect_init()
1528 emc->provider.set = emc_icc_set; in tegra_emc_interconnect_init()
1529 emc->provider.data = &emc->provider; in tegra_emc_interconnect_init()
1530 emc->provider.aggregate = soc->icc_ops->aggregate; in tegra_emc_interconnect_init()
1531 emc->provider.xlate_extended = emc_of_icc_xlate_extended; in tegra_emc_interconnect_init()
1533 icc_provider_init(&emc->provider); in tegra_emc_interconnect_init()
1542 node->name = "External Memory Controller"; in tegra_emc_interconnect_init()
1543 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1557 node->name = "External Memory (DRAM)"; in tegra_emc_interconnect_init()
1558 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1560 err = icc_provider_register(&emc->provider); in tegra_emc_interconnect_init()
1567 icc_nodes_remove(&emc->provider); in tegra_emc_interconnect_init()
1569 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); in tegra_emc_interconnect_init()
1581 struct tegra_emc *emc = data; in devm_tegra_emc_unreg_clk_notifier() local
1583 clk_notifier_unregister(emc->clk, &emc->clk_nb); in devm_tegra_emc_unreg_clk_notifier()
1586 static int tegra_emc_init_clk(struct tegra_emc *emc) in tegra_emc_init_clk() argument
1590 tegra20_clk_set_emc_round_callback(emc_round_rate, emc); in tegra_emc_init_clk()
1592 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, in tegra_emc_init_clk()
1597 emc->clk = devm_clk_get(emc->dev, NULL); in tegra_emc_init_clk()
1598 if (IS_ERR(emc->clk)) { in tegra_emc_init_clk()
1599 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); in tegra_emc_init_clk()
1600 return PTR_ERR(emc->clk); in tegra_emc_init_clk()
1603 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_init_clk()
1605 dev_err(emc->dev, "failed to register clk notifier: %d\n", err); in tegra_emc_init_clk()
1609 err = devm_add_action_or_reset(emc->dev, in tegra_emc_init_clk()
1610 devm_tegra_emc_unreg_clk_notifier, emc); in tegra_emc_init_clk()
1621 struct tegra_emc *emc; in tegra_emc_probe() local
1624 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1625 if (!emc) in tegra_emc_probe()
1626 return -ENOMEM; in tegra_emc_probe()
1628 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); in tegra_emc_probe()
1629 if (IS_ERR(emc->mc)) in tegra_emc_probe()
1630 return PTR_ERR(emc->mc); in tegra_emc_probe()
1632 mutex_init(&emc->rate_lock); in tegra_emc_probe()
1633 emc->clk_nb.notifier_call = emc_clk_change_notify; in tegra_emc_probe()
1634 emc->dev = &pdev->dev; in tegra_emc_probe()
1636 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1637 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1638 return PTR_ERR(emc->regs); in tegra_emc_probe()
1640 err = emc_setup_hw(emc); in tegra_emc_probe()
1644 np = emc_find_node_by_ram_code(emc); in tegra_emc_probe()
1646 err = emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1656 emc->irq = err; in tegra_emc_probe()
1658 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, in tegra_emc_probe()
1659 dev_name(&pdev->dev), emc); in tegra_emc_probe()
1661 dev_err(&pdev->dev, "failed to request irq: %d\n", err); in tegra_emc_probe()
1665 err = tegra_emc_init_clk(emc); in tegra_emc_probe()
1671 err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); in tegra_emc_probe()
1675 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1676 tegra_emc_rate_requests_init(emc); in tegra_emc_probe()
1677 tegra_emc_debugfs_init(emc); in tegra_emc_probe()
1678 tegra_emc_interconnect_init(emc); in tegra_emc_probe()
1692 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_suspend() local
1696 err = clk_rate_exclusive_get(emc->clk); in tegra_emc_suspend()
1698 dev_err(emc->dev, "failed to acquire clk: %d\n", err); in tegra_emc_suspend()
1703 if (WARN(emc->bad_state, "hardware in a bad state\n")) in tegra_emc_suspend()
1704 return -EINVAL; in tegra_emc_suspend()
1706 emc->bad_state = true; in tegra_emc_suspend()
1713 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_resume() local
1715 emc_setup_hw(emc); in tegra_emc_resume()
1716 emc->bad_state = false; in tegra_emc_resume()
1718 clk_rate_exclusive_put(emc->clk); in tegra_emc_resume()
1729 { .compatible = "nvidia,tegra30-emc", },
1737 .name = "tegra30-emc",
1747 MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver");