Lines Matching full:emc
21 #include "tegra210-emc.h"
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = timer_container_of(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
578 static void tegra210_emc_training_start(struct tegra210_emc *emc) in tegra210_emc_training_start() argument
580 mod_timer(&emc->training, in tegra210_emc_training_start()
581 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_training_start()
584 static void tegra210_emc_training_stop(struct tegra210_emc *emc) in tegra210_emc_training_stop() argument
586 timer_delete(&emc->training); in tegra210_emc_training_stop()
589 static unsigned int tegra210_emc_get_temperature(struct tegra210_emc *emc) in tegra210_emc_get_temperature() argument
595 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_get_temperature()
597 for (i = 0; i < emc->num_devices; i++) { in tegra210_emc_get_temperature()
598 value = tegra210_emc_mrr_read(emc, i, 4); in tegra210_emc_get_temperature()
601 dev_dbg(emc->dev, in tegra210_emc_get_temperature()
610 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_get_temperature()
617 struct tegra210_emc *emc = timer_container_of(emc, timer, in tegra210_emc_poll_refresh() local
621 if (!emc->debugfs.temperature) in tegra210_emc_poll_refresh()
622 temperature = tegra210_emc_get_temperature(emc); in tegra210_emc_poll_refresh()
624 temperature = emc->debugfs.temperature; in tegra210_emc_poll_refresh()
626 if (temperature == emc->temperature) in tegra210_emc_poll_refresh()
632 dev_dbg(emc->dev, "switching to nominal refresh...\n"); in tegra210_emc_poll_refresh()
633 tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_NOMINAL); in tegra210_emc_poll_refresh()
637 dev_dbg(emc->dev, "switching to 2x refresh...\n"); in tegra210_emc_poll_refresh()
638 tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_2X); in tegra210_emc_poll_refresh()
642 dev_dbg(emc->dev, "switching to 4x refresh...\n"); in tegra210_emc_poll_refresh()
643 tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_4X); in tegra210_emc_poll_refresh()
647 dev_dbg(emc->dev, "switching to throttle refresh...\n"); in tegra210_emc_poll_refresh()
648 tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_THROTTLE); in tegra210_emc_poll_refresh()
656 emc->temperature = temperature; in tegra210_emc_poll_refresh()
659 if (atomic_read(&emc->refresh_poll) > 0) { in tegra210_emc_poll_refresh()
660 unsigned int interval = emc->refresh_poll_interval; in tegra210_emc_poll_refresh()
663 mod_timer(&emc->refresh_timer, jiffies + timeout); in tegra210_emc_poll_refresh()
667 static void tegra210_emc_poll_refresh_stop(struct tegra210_emc *emc) in tegra210_emc_poll_refresh_stop() argument
669 atomic_set(&emc->refresh_poll, 0); in tegra210_emc_poll_refresh_stop()
670 timer_delete_sync(&emc->refresh_timer); in tegra210_emc_poll_refresh_stop()
673 static void tegra210_emc_poll_refresh_start(struct tegra210_emc *emc) in tegra210_emc_poll_refresh_start() argument
675 atomic_set(&emc->refresh_poll, 1); in tegra210_emc_poll_refresh_start()
677 mod_timer(&emc->refresh_timer, in tegra210_emc_poll_refresh_start()
678 jiffies + msecs_to_jiffies(emc->refresh_poll_interval)); in tegra210_emc_poll_refresh_start()
692 struct tegra210_emc *emc = cd->devdata; in tegra210_emc_cd_get_state() local
694 *state = atomic_read(&emc->refresh_poll); in tegra210_emc_cd_get_state()
702 struct tegra210_emc *emc = cd->devdata; in tegra210_emc_cd_set_state() local
704 if (state == atomic_read(&emc->refresh_poll)) in tegra210_emc_cd_set_state()
708 tegra210_emc_poll_refresh_start(emc); in tegra210_emc_cd_set_state()
710 tegra210_emc_poll_refresh_stop(emc); in tegra210_emc_cd_set_state()
721 static void tegra210_emc_set_clock(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_set_clock() argument
723 emc->sequence->set_clock(emc, clksrc); in tegra210_emc_set_clock()
725 if (emc->next->periodic_training) in tegra210_emc_set_clock()
726 tegra210_emc_training_start(emc); in tegra210_emc_set_clock()
728 tegra210_emc_training_stop(emc); in tegra210_emc_set_clock()
731 static void tegra210_change_dll_src(struct tegra210_emc *emc, in tegra210_change_dll_src() argument
734 u32 dll_setting = emc->next->dll_clk_src; in tegra210_change_dll_src()
761 if (emc->next->clk_out_enb_x_0_clk_enb_emc_dll) in tegra210_change_dll_src()
767 int tegra210_emc_set_refresh(struct tegra210_emc *emc, in tegra210_emc_set_refresh() argument
773 if ((emc->dram_type != DRAM_TYPE_LPDDR2 && in tegra210_emc_set_refresh()
774 emc->dram_type != DRAM_TYPE_LPDDR4) || in tegra210_emc_set_refresh()
775 !emc->last) in tegra210_emc_set_refresh()
781 if (refresh == emc->refresh) in tegra210_emc_set_refresh()
784 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_set_refresh()
786 if (refresh == TEGRA210_EMC_REFRESH_THROTTLE && emc->derated) in tegra210_emc_set_refresh()
787 timings = emc->derated; in tegra210_emc_set_refresh()
789 timings = emc->nominal; in tegra210_emc_set_refresh()
791 if (timings != emc->timings) { in tegra210_emc_set_refresh()
792 unsigned int index = emc->last - emc->timings; in tegra210_emc_set_refresh()
795 clksrc = emc->provider.configs[index].value | in tegra210_emc_set_refresh()
798 emc->next = &timings[index]; in tegra210_emc_set_refresh()
799 emc->timings = timings; in tegra210_emc_set_refresh()
801 tegra210_emc_set_clock(emc, clksrc); in tegra210_emc_set_refresh()
803 tegra210_emc_adjust_timing(emc, emc->last); in tegra210_emc_set_refresh()
804 tegra210_emc_timing_update(emc); in tegra210_emc_set_refresh()
807 emc_writel(emc, EMC_REF_REF_CMD, EMC_REF); in tegra210_emc_set_refresh()
810 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_set_refresh()
815 u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip, in tegra210_emc_mrr_read() argument
823 emc_writel(emc, value, EMC_MRR); in tegra210_emc_mrr_read()
825 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_mrr_read()
826 WARN(tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS, in tegra210_emc_mrr_read()
830 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_mrr_read()
831 value = emc_channel_readl(emc, i, EMC_MRR); in tegra210_emc_mrr_read()
840 void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_do_clock_change() argument
844 mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_do_clock_change()
845 emc_readl(emc, EMC_INTSTATUS); in tegra210_emc_do_clock_change()
849 err = tegra210_emc_wait_for_update(emc, 0, EMC_INTSTATUS, in tegra210_emc_do_clock_change()
853 dev_warn(emc->dev, "clock change completion error: %d\n", err); in tegra210_emc_do_clock_change()
856 struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc, in tegra210_emc_find_timing() argument
861 for (i = 0; i < emc->num_timings; i++) in tegra210_emc_find_timing()
862 if (emc->timings[i].rate * 1000UL == rate) in tegra210_emc_find_timing()
863 return &emc->timings[i]; in tegra210_emc_find_timing()
868 int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel, in tegra210_emc_wait_for_update() argument
875 value = emc_channel_readl(emc, channel, offset); in tegra210_emc_wait_for_update()
885 void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set) in tegra210_emc_set_shadow_bypass() argument
887 u32 emc_dbg = emc_readl(emc, EMC_DBG); in tegra210_emc_set_shadow_bypass()
890 emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
892 emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG); in tegra210_emc_set_shadow_bypass()
903 void tegra210_emc_timing_update(struct tegra210_emc *emc) in tegra210_emc_timing_update() argument
908 emc_writel(emc, 0x1, EMC_TIMING_CONTROL); in tegra210_emc_timing_update()
910 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_timing_update()
911 err |= tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS, in tegra210_emc_timing_update()
917 dev_warn(emc->dev, "timing update error: %d\n", err); in tegra210_emc_timing_update()
932 void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc) in tegra210_emc_start_periodic_compensation() argument
936 emc_writel(emc, mpc_req, EMC_MPC); in tegra210_emc_start_periodic_compensation()
937 mpc_req = emc_readl(emc, EMC_MPC); in tegra210_emc_start_periodic_compensation()
1140 u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_dll_prelock() argument
1145 value = emc_readl(emc, EMC_CFG_DIG_DLL); in tegra210_emc_dll_prelock()
1154 emc_writel(emc, value, EMC_CFG_DIG_DLL); in tegra210_emc_dll_prelock()
1155 emc_writel(emc, 1, EMC_TIMING_CONTROL); in tegra210_emc_dll_prelock()
1157 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_dll_prelock()
1158 tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS, in tegra210_emc_dll_prelock()
1162 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_dll_prelock()
1164 value = emc_channel_readl(emc, i, EMC_CFG_DIG_DLL); in tegra210_emc_dll_prelock()
1170 value = emc->next->burst_regs[EMC_DLL_CFG_0_INDEX]; in tegra210_emc_dll_prelock()
1171 emc_writel(emc, value, EMC_DLL_CFG_0); in tegra210_emc_dll_prelock()
1173 value = emc_readl(emc, EMC_DLL_CFG_1); in tegra210_emc_dll_prelock()
1176 if (emc->next->rate >= 400000 && emc->next->rate < 600000) in tegra210_emc_dll_prelock()
1178 else if (emc->next->rate >= 600000 && emc->next->rate < 800000) in tegra210_emc_dll_prelock()
1180 else if (emc->next->rate >= 800000 && emc->next->rate < 1000000) in tegra210_emc_dll_prelock()
1182 else if (emc->next->rate >= 1000000 && emc->next->rate < 1200000) in tegra210_emc_dll_prelock()
1187 emc_writel(emc, value, EMC_DLL_CFG_1); in tegra210_emc_dll_prelock()
1189 tegra210_change_dll_src(emc, clksrc); in tegra210_emc_dll_prelock()
1191 value = emc_readl(emc, EMC_CFG_DIG_DLL); in tegra210_emc_dll_prelock()
1193 emc_writel(emc, value, EMC_CFG_DIG_DLL); in tegra210_emc_dll_prelock()
1195 tegra210_emc_timing_update(emc); in tegra210_emc_dll_prelock()
1197 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_dll_prelock()
1199 value = emc_channel_readl(emc, 0, EMC_CFG_DIG_DLL); in tegra210_emc_dll_prelock()
1206 value = emc_readl(emc, EMC_DIG_DLL_STATUS); in tegra210_emc_dll_prelock()
1217 value = emc_readl(emc, EMC_DIG_DLL_STATUS); in tegra210_emc_dll_prelock()
1222 u32 tegra210_emc_dvfs_power_ramp_up(struct tegra210_emc *emc, u32 clk, in tegra210_emc_dvfs_power_ramp_up() argument
1229 timing = emc->last; in tegra210_emc_dvfs_power_ramp_up()
1231 timing = emc->next; in tegra210_emc_dvfs_power_ramp_up()
1242 ccfifo_writel(emc, common_tx & 0xa, in tegra210_emc_dvfs_power_ramp_up()
1244 ccfifo_writel(emc, common_tx & 0xf, in tegra210_emc_dvfs_power_ramp_up()
1249 ccfifo_writel(emc, common_tx | 0x8, in tegra210_emc_dvfs_power_ramp_up()
1261 ccfifo_writel(emc, cmd_pad, in tegra210_emc_dvfs_power_ramp_up()
1272 ccfifo_writel(emc, dq_pad, in tegra210_emc_dvfs_power_ramp_up()
1274 ccfifo_writel(emc, rfu1 & 0xfe40fe40, in tegra210_emc_dvfs_power_ramp_up()
1277 ccfifo_writel(emc, rfu1 & 0xfe40fe40, in tegra210_emc_dvfs_power_ramp_up()
1283 ccfifo_writel(emc, rfu1 & 0xfeedfeed, in tegra210_emc_dvfs_power_ramp_up()
1293 ccfifo_writel(emc, cmd_pad, in tegra210_emc_dvfs_power_ramp_up()
1303 ccfifo_writel(emc, dq_pad, in tegra210_emc_dvfs_power_ramp_up()
1305 ccfifo_writel(emc, rfu1, in tegra210_emc_dvfs_power_ramp_up()
1308 ccfifo_writel(emc, rfu1, in tegra210_emc_dvfs_power_ramp_up()
1314 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_up()
1318 ccfifo_writel(emc, rfu1 | 0x06000600, in tegra210_emc_dvfs_power_ramp_up()
1320 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_up()
1324 ccfifo_writel(emc, rfu1 | 0x00000600, in tegra210_emc_dvfs_power_ramp_up()
1326 ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_up()
1332 ccfifo_writel(emc, cmd_pad, EMC_PMACRO_CMD_PAD_TX_CTRL, 5); in tegra210_emc_dvfs_power_ramp_up()
1337 u32 tegra210_emc_dvfs_power_ramp_down(struct tegra210_emc *emc, u32 clk, in tegra210_emc_dvfs_power_ramp_down() argument
1345 entry = emc->next; in tegra210_emc_dvfs_power_ramp_down()
1347 entry = emc->last; in tegra210_emc_dvfs_power_ramp_down()
1357 ccfifo_writel(emc, cmd_pad, EMC_PMACRO_CMD_PAD_TX_CTRL, 0); in tegra210_emc_dvfs_power_ramp_down()
1358 ccfifo_writel(emc, cfg5 | EMC_FBIO_CFG5_CMD_TX_DIS, in tegra210_emc_dvfs_power_ramp_down()
1372 ccfifo_writel(emc, cmd_pad, in tegra210_emc_dvfs_power_ramp_down()
1382 ccfifo_writel(emc, dq_pad, in tegra210_emc_dvfs_power_ramp_down()
1384 ccfifo_writel(emc, rfu1 & ~0x01120112, in tegra210_emc_dvfs_power_ramp_down()
1387 ccfifo_writel(emc, rfu1 & ~0x01120112, in tegra210_emc_dvfs_power_ramp_down()
1392 ccfifo_writel(emc, rfu1 & ~0x01bf01bf, in tegra210_emc_dvfs_power_ramp_down()
1402 ccfifo_writel(emc, cmd_pad, in tegra210_emc_dvfs_power_ramp_down()
1411 ccfifo_writel(emc, dq_pad, in tegra210_emc_dvfs_power_ramp_down()
1413 ccfifo_writel(emc, rfu1 & ~0x07ff07ff, in tegra210_emc_dvfs_power_ramp_down()
1416 ccfifo_writel(emc, rfu1 & ~0x07ff07ff, in tegra210_emc_dvfs_power_ramp_down()
1421 ccfifo_writel(emc, rfu1 & ~0xffff07ff, in tegra210_emc_dvfs_power_ramp_down()
1428 ccfifo_writel(emc, common_tx & ~0x5, in tegra210_emc_dvfs_power_ramp_down()
1431 ccfifo_writel(emc, common_tx & ~0xf, in tegra210_emc_dvfs_power_ramp_down()
1434 ccfifo_writel(emc, 0, 0, seq_wait); in tegra210_emc_dvfs_power_ramp_down()
1437 ccfifo_writel(emc, common_tx & ~0xf, in tegra210_emc_dvfs_power_ramp_down()
1460 static void update_dll_control(struct tegra210_emc *emc, u32 value, bool state) in update_dll_control() argument
1464 emc_writel(emc, value, EMC_CFG_DIG_DLL); in update_dll_control()
1465 tegra210_emc_timing_update(emc); in update_dll_control()
1467 for (i = 0; i < emc->num_channels; i++) in update_dll_control()
1468 tegra210_emc_wait_for_update(emc, i, EMC_CFG_DIG_DLL, in update_dll_control()
1473 void tegra210_emc_dll_disable(struct tegra210_emc *emc) in tegra210_emc_dll_disable() argument
1477 value = emc_readl(emc, EMC_CFG_DIG_DLL); in tegra210_emc_dll_disable()
1480 update_dll_control(emc, value, false); in tegra210_emc_dll_disable()
1483 void tegra210_emc_dll_enable(struct tegra210_emc *emc) in tegra210_emc_dll_enable() argument
1487 value = emc_readl(emc, EMC_CFG_DIG_DLL); in tegra210_emc_dll_enable()
1490 update_dll_control(emc, value, true); in tegra210_emc_dll_enable()
1493 void tegra210_emc_adjust_timing(struct tegra210_emc *emc, in tegra210_emc_adjust_timing() argument
1500 switch (emc->refresh) { in tegra210_emc_adjust_timing()
1518 dev_warn(emc->dev, "failed to set refresh: %d\n", emc->refresh); in tegra210_emc_adjust_timing()
1522 emc_writel(emc, ref, emc->offsets->burst[EMC_REFRESH_INDEX]); in tegra210_emc_adjust_timing()
1523 emc_writel(emc, pre_ref, in tegra210_emc_adjust_timing()
1524 emc->offsets->burst[EMC_PRE_REFRESH_REQ_CNT_INDEX]); in tegra210_emc_adjust_timing()
1525 emc_writel(emc, dsr_cntrl, in tegra210_emc_adjust_timing()
1526 emc->offsets->burst[EMC_DYN_SELF_REF_CONTROL_INDEX]); in tegra210_emc_adjust_timing()
1532 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_set_rate() local
1539 if (rate == emc->last->rate * 1000UL) in tegra210_emc_set_rate()
1542 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_set_rate()
1543 if (emc->timings[i].rate * 1000UL == rate) { in tegra210_emc_set_rate()
1544 timing = &emc->timings[i]; in tegra210_emc_set_rate()
1555 emc->next = timing; in tegra210_emc_set_rate()
1556 last_change_delay = ktime_us_delta(ktime_get(), emc->clkchange_time); in tegra210_emc_set_rate()
1560 (last_change_delay < emc->clkchange_delay)) in tegra210_emc_set_rate()
1561 udelay(emc->clkchange_delay - (int)last_change_delay); in tegra210_emc_set_rate()
1563 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_set_rate()
1564 tegra210_emc_set_clock(emc, config->value); in tegra210_emc_set_rate()
1565 emc->clkchange_time = ktime_get(); in tegra210_emc_set_rate()
1566 emc->last = timing; in tegra210_emc_set_rate()
1567 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_set_rate()
1576 * to control the EMC frequency. The top-level directory can be found here:
1578 * /sys/kernel/debug/emc
1583 * EMC frequencies.
1587 * configured EMC frequency, this will cause the frequency to be
1592 * the value is lower than the currently configured EMC frequency, this
1597 static bool tegra210_emc_validate_rate(struct tegra210_emc *emc, in tegra210_emc_validate_rate() argument
1602 for (i = 0; i < emc->num_timings; i++) in tegra210_emc_validate_rate()
1603 if (rate == emc->timings[i].rate * 1000UL) in tegra210_emc_validate_rate()
1612 struct tegra210_emc *emc = s->private; in tegra210_emc_debug_available_rates_show() local
1616 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_debug_available_rates_show()
1617 seq_printf(s, "%s%u", prefix, emc->timings[i].rate * 1000); in tegra210_emc_debug_available_rates_show()
1629 struct tegra210_emc *emc = data; in tegra210_emc_debug_min_rate_get() local
1631 *rate = emc->debugfs.min_rate; in tegra210_emc_debug_min_rate_get()
1638 struct tegra210_emc *emc = data; in tegra210_emc_debug_min_rate_set() local
1641 if (!tegra210_emc_validate_rate(emc, rate)) in tegra210_emc_debug_min_rate_set()
1644 err = clk_set_min_rate(emc->clk, rate); in tegra210_emc_debug_min_rate_set()
1648 emc->debugfs.min_rate = rate; in tegra210_emc_debug_min_rate_set()
1659 struct tegra210_emc *emc = data; in tegra210_emc_debug_max_rate_get() local
1661 *rate = emc->debugfs.max_rate; in tegra210_emc_debug_max_rate_get()
1668 struct tegra210_emc *emc = data; in tegra210_emc_debug_max_rate_set() local
1671 if (!tegra210_emc_validate_rate(emc, rate)) in tegra210_emc_debug_max_rate_set()
1674 err = clk_set_max_rate(emc->clk, rate); in tegra210_emc_debug_max_rate_set()
1678 emc->debugfs.max_rate = rate; in tegra210_emc_debug_max_rate_set()
1689 struct tegra210_emc *emc = data; in tegra210_emc_debug_temperature_get() local
1692 if (!emc->debugfs.temperature) in tegra210_emc_debug_temperature_get()
1693 value = tegra210_emc_get_temperature(emc); in tegra210_emc_debug_temperature_get()
1695 value = emc->debugfs.temperature; in tegra210_emc_debug_temperature_get()
1704 struct tegra210_emc *emc = data; in tegra210_emc_debug_temperature_set() local
1709 emc->debugfs.temperature = temperature; in tegra210_emc_debug_temperature_set()
1718 static void tegra210_emc_debugfs_init(struct tegra210_emc *emc) in tegra210_emc_debugfs_init() argument
1720 struct device *dev = emc->dev; in tegra210_emc_debugfs_init()
1724 emc->debugfs.min_rate = ULONG_MAX; in tegra210_emc_debugfs_init()
1725 emc->debugfs.max_rate = 0; in tegra210_emc_debugfs_init()
1727 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_debugfs_init()
1728 if (emc->timings[i].rate * 1000UL < emc->debugfs.min_rate) in tegra210_emc_debugfs_init()
1729 emc->debugfs.min_rate = emc->timings[i].rate * 1000UL; in tegra210_emc_debugfs_init()
1731 if (emc->timings[i].rate * 1000UL > emc->debugfs.max_rate) in tegra210_emc_debugfs_init()
1732 emc->debugfs.max_rate = emc->timings[i].rate * 1000UL; in tegra210_emc_debugfs_init()
1735 if (!emc->num_timings) { in tegra210_emc_debugfs_init()
1736 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra210_emc_debugfs_init()
1737 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra210_emc_debugfs_init()
1740 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra210_emc_debugfs_init()
1741 emc->debugfs.max_rate); in tegra210_emc_debugfs_init()
1744 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra210_emc_debugfs_init()
1745 emc->clk); in tegra210_emc_debugfs_init()
1749 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra210_emc_debugfs_init()
1751 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1753 debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1755 debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1757 debugfs_create_file("temperature", 0644, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1761 static void tegra210_emc_detect(struct tegra210_emc *emc) in tegra210_emc_detect() argument
1766 value = mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_detect()
1769 emc->num_devices = 2; in tegra210_emc_detect()
1771 emc->num_devices = 1; in tegra210_emc_detect()
1774 value = emc_readl(emc, EMC_FBIO_CFG5); in tegra210_emc_detect()
1775 emc->dram_type = value & 0x3; in tegra210_emc_detect()
1778 value = emc_readl(emc, EMC_FBIO_CFG7); in tegra210_emc_detect()
1782 emc->num_channels = 2; in tegra210_emc_detect()
1784 emc->num_channels = 1; in tegra210_emc_detect()
1787 static int tegra210_emc_validate_timings(struct tegra210_emc *emc, in tegra210_emc_validate_timings() argument
1815 struct tegra210_emc *emc; in tegra210_emc_probe() local
1820 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra210_emc_probe()
1821 if (!emc) in tegra210_emc_probe()
1824 emc->clk = devm_clk_get(&pdev->dev, "emc"); in tegra210_emc_probe()
1825 if (IS_ERR(emc->clk)) in tegra210_emc_probe()
1826 return PTR_ERR(emc->clk); in tegra210_emc_probe()
1828 platform_set_drvdata(pdev, emc); in tegra210_emc_probe()
1829 spin_lock_init(&emc->lock); in tegra210_emc_probe()
1830 emc->dev = &pdev->dev; in tegra210_emc_probe()
1832 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); in tegra210_emc_probe()
1833 if (IS_ERR(emc->mc)) in tegra210_emc_probe()
1834 return PTR_ERR(emc->mc); in tegra210_emc_probe()
1836 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra210_emc_probe()
1837 if (IS_ERR(emc->regs)) in tegra210_emc_probe()
1838 return PTR_ERR(emc->regs); in tegra210_emc_probe()
1841 emc->channel[i] = devm_platform_ioremap_resource(pdev, 1 + i); in tegra210_emc_probe()
1842 if (IS_ERR(emc->channel[i])) in tegra210_emc_probe()
1843 return PTR_ERR(emc->channel[i]); in tegra210_emc_probe()
1847 tegra210_emc_detect(emc); in tegra210_emc_probe()
1851 err = of_reserved_mem_device_init_by_name(emc->dev, np, "nominal"); in tegra210_emc_probe()
1853 dev_err(emc->dev, "failed to get nominal EMC table: %d\n", err); in tegra210_emc_probe()
1857 err = of_reserved_mem_device_init_by_name(emc->dev, np, "derated"); in tegra210_emc_probe()
1859 dev_err(emc->dev, "failed to get derated EMC table: %d\n", err); in tegra210_emc_probe()
1864 if (emc->nominal) { in tegra210_emc_probe()
1865 err = tegra210_emc_validate_timings(emc, emc->nominal, in tegra210_emc_probe()
1866 emc->num_timings); in tegra210_emc_probe()
1871 if (emc->derated) { in tegra210_emc_probe()
1872 err = tegra210_emc_validate_timings(emc, emc->derated, in tegra210_emc_probe()
1873 emc->num_timings); in tegra210_emc_probe()
1879 emc->timings = emc->nominal; in tegra210_emc_probe()
1881 /* pick the current timing based on the current EMC clock rate */ in tegra210_emc_probe()
1882 current_rate = clk_get_rate(emc->clk) / 1000; in tegra210_emc_probe()
1884 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_probe()
1885 if (emc->timings[i].rate == current_rate) { in tegra210_emc_probe()
1886 emc->last = &emc->timings[i]; in tegra210_emc_probe()
1891 if (i == emc->num_timings) { in tegra210_emc_probe()
1892 dev_err(emc->dev, "no EMC table entry found for %lu kHz\n", in tegra210_emc_probe()
1898 /* pick a compatible clock change sequence for the EMC table */ in tegra210_emc_probe()
1903 if (emc->timings[0].revision == sequence->revision) { in tegra210_emc_probe()
1904 emc->sequence = sequence; in tegra210_emc_probe()
1909 if (!emc->sequence) { in tegra210_emc_probe()
1911 emc->timings[0].revision); in tegra210_emc_probe()
1916 emc->offsets = &tegra210_emc_table_register_offsets; in tegra210_emc_probe()
1917 emc->refresh = TEGRA210_EMC_REFRESH_NOMINAL; in tegra210_emc_probe()
1919 emc->provider.owner = THIS_MODULE; in tegra210_emc_probe()
1920 emc->provider.dev = &pdev->dev; in tegra210_emc_probe()
1921 emc->provider.set_rate = tegra210_emc_set_rate; in tegra210_emc_probe()
1923 emc->provider.configs = devm_kcalloc(&pdev->dev, emc->num_timings, in tegra210_emc_probe()
1924 sizeof(*emc->provider.configs), in tegra210_emc_probe()
1926 if (!emc->provider.configs) { in tegra210_emc_probe()
1931 emc->provider.num_configs = emc->num_timings; in tegra210_emc_probe()
1933 for (i = 0; i < emc->provider.num_configs; i++) { in tegra210_emc_probe()
1934 struct tegra210_emc_timing *timing = &emc->timings[i]; in tegra210_emc_probe()
1936 &emc->provider.configs[i]; in tegra210_emc_probe()
1950 err = tegra210_clk_emc_attach(emc->clk, &emc->provider); in tegra210_emc_probe()
1952 dev_err(&pdev->dev, "failed to attach to EMC clock: %d\n", err); in tegra210_emc_probe()
1956 emc->clkchange_delay = 100; in tegra210_emc_probe()
1957 emc->training_interval = 100; in tegra210_emc_probe()
1958 dev_set_drvdata(emc->dev, emc); in tegra210_emc_probe()
1960 timer_setup(&emc->refresh_timer, tegra210_emc_poll_refresh, in tegra210_emc_probe()
1962 atomic_set(&emc->refresh_poll, 0); in tegra210_emc_probe()
1963 emc->refresh_poll_interval = 1000; in tegra210_emc_probe()
1965 timer_setup(&emc->training, tegra210_emc_train, 0); in tegra210_emc_probe()
1967 tegra210_emc_debugfs_init(emc); in tegra210_emc_probe()
1969 cd = devm_thermal_of_cooling_device_register(emc->dev, np, "emc", emc, in tegra210_emc_probe()
1973 dev_err(emc->dev, "failed to register cooling device: %d\n", in tegra210_emc_probe()
1981 debugfs_remove_recursive(emc->debugfs.root); in tegra210_emc_probe()
1982 tegra210_clk_emc_detach(emc->clk); in tegra210_emc_probe()
1984 of_reserved_mem_device_release(emc->dev); in tegra210_emc_probe()
1991 struct tegra210_emc *emc = platform_get_drvdata(pdev); in tegra210_emc_remove() local
1993 debugfs_remove_recursive(emc->debugfs.root); in tegra210_emc_remove()
1994 tegra210_clk_emc_detach(emc->clk); in tegra210_emc_remove()
1995 of_reserved_mem_device_release(emc->dev); in tegra210_emc_remove()
2000 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_suspend() local
2003 err = clk_rate_exclusive_get(emc->clk); in tegra210_emc_suspend()
2005 dev_err(emc->dev, "failed to acquire clock: %d\n", err); in tegra210_emc_suspend()
2009 emc->resume_rate = clk_get_rate(emc->clk); in tegra210_emc_suspend()
2011 clk_set_rate(emc->clk, 204000000); in tegra210_emc_suspend()
2012 tegra210_clk_emc_detach(emc->clk); in tegra210_emc_suspend()
2014 dev_dbg(dev, "suspending at %lu Hz\n", clk_get_rate(emc->clk)); in tegra210_emc_suspend()
2021 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_resume() local
2024 err = tegra210_clk_emc_attach(emc->clk, &emc->provider); in tegra210_emc_resume()
2026 dev_err(dev, "failed to attach to EMC clock: %d\n", err); in tegra210_emc_resume()
2030 clk_set_rate(emc->clk, emc->resume_rate); in tegra210_emc_resume()
2031 clk_rate_exclusive_put(emc->clk); in tegra210_emc_resume()
2033 dev_dbg(dev, "resuming at %lu Hz\n", clk_get_rate(emc->clk)); in tegra210_emc_resume()
2043 { .compatible = "nvidia,tegra210-emc", },
2050 .name = "tegra210-emc",
2062 MODULE_DESCRIPTION("NVIDIA Tegra210 EMC driver");